1/*	$NetBSD: tmureg.h,v 1.10 2005/12/11 12:18:58 christos Exp $	*/
2
3/*-
4 * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 *    derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _SH3_TMUREG_H_
30#define	_SH3_TMUREG_H_
31#include <sh3/devreg.h>
32
33/*
34 * TMU
35 */
36#define	SH3_TOCR			0xfffffe90
37#define	SH3_TSTR			0xfffffe92
38#define	SH3_TCOR0			0xfffffe94
39#define	SH3_TCNT0			0xfffffe98
40#define	SH3_TCR0			0xfffffe9c
41#define	SH3_TCOR1			0xfffffea0
42#define	SH3_TCNT1			0xfffffea4
43#define	SH3_TCR1			0xfffffea8
44#define	SH3_TCOR2			0xfffffeac
45#define	SH3_TCNT2			0xfffffeb0
46#define	SH3_TCR2			0xfffffeb4
47#define	SH3_TCPR2			0xfffffeb8
48
49#define	SH4_TOCR			0xffd80000
50#define	SH4_TSTR			0xffd80004
51#define	SH4_TCOR0			0xffd80008
52#define	SH4_TCNT0			0xffd8000c
53#define	SH4_TCR0			0xffd80010
54#define	SH4_TCOR1			0xffd80014
55#define	SH4_TCNT1			0xffd80018
56#define	SH4_TCR1			0xffd8001c
57#define	SH4_TCOR2			0xffd80020
58#define	SH4_TCNT2			0xffd80024
59#define	SH4_TCR2			0xffd80028
60#define	SH4_TCPR2			0xffd8002c
61#define	SH4_TSTR2			0xfe100004
62#define	SH4_TCOR3			0xfe100008
63#define	SH4_TCNT3			0xfe10000c
64#define	SH4_TCR3			0xfe100010
65#define	SH4_TCOR4			0xfe100014
66#define	SH4_TCNT4			0xfe100018
67#define	SH4_TCR4			0xfe10001c
68
69
70#define	TOCR_TCOE			0x01
71#define	TSTR_STR2			0x04
72#define	TSTR_STR1			0x02
73#define	TSTR_STR0			0x01
74#define	TCR_ICPF			0x0200
75#define	TCR_UNF				0x0100
76#define	TCR_ICPE1			0x0080
77#define	TCR_ICPE0			0x0040
78#define	TCR_UNIE			0x0020
79#define	TCR_CKEG1			0x0010
80#define	TCR_CKEG0			0x0008
81#define	TCR_TPSC2			0x0004
82#define	TCR_TPSC1			0x0002
83#define	TCR_TPSC0			0x0001
84#define	TCR_TPSC_P4			0x0000
85#define	TCR_TPSC_P16			0x0001
86#define	TCR_TPSC_P64			0x0002
87#define	TCR_TPSC_P256			0x0003
88#define	SH3_TCR_TPSC_RTC		0x0004
89#define	SH3_TCR_TPSC_TCLK		0x0005
90#define	SH4_TCR_TPSC_P1024		0x0004
91#define	SH4_TCR_TPSC_RTC		0x0006
92#define	SH4_TCR_TPSC_TCLK		0x0007
93#define	SH4_TSTR2_STR4			0x02
94#define	SH4_TSTR2_STR3			0x01
95
96
97#ifndef _LOCORE
98#if defined(SH3) && defined(SH4)
99extern uint32_t __sh_TOCR;
100extern uint32_t __sh_TSTR;
101extern uint32_t __sh_TCOR0;
102extern uint32_t __sh_TCNT0;
103extern uint32_t __sh_TCR0;
104extern uint32_t __sh_TCOR1;
105extern uint32_t __sh_TCNT1;
106extern uint32_t __sh_TCR1;
107extern uint32_t __sh_TCOR2;
108extern uint32_t __sh_TCNT2;
109extern uint32_t __sh_TCR2;
110extern uint32_t __sh_TCPR2;
111#endif /* SH3 && SH4 */
112#endif /* !_LOCORE */
113
114#endif	/* !_SH3_TMUREG_H_ */
115