1198160Srrs/* $NetBSD: devreg.h,v 1.7 2021/10/06 20:36:58 andvar Exp $ */ 2198160Srrs 3198160Srrs/*- 4198160Srrs * Copyright (c) 2002 The NetBSD Foundation, Inc. 5198160Srrs * All rights reserved. 6198160Srrs * 7198160Srrs * Redistribution and use in source and binary forms, with or without 8198160Srrs * modification, are permitted provided that the following conditions 9198160Srrs * are met: 10198160Srrs * 1. Redistributions of source code must retain the above copyright 11198160Srrs * notice, this list of conditions and the following disclaimer. 12198160Srrs * 2. Redistributions in binary form must reproduce the above copyright 13198160Srrs * notice, this list of conditions and the following disclaimer in the 14198160Srrs * documentation and/or other materials provided with the distribution. 15198160Srrs * 16198160Srrs * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17198160Srrs * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18198160Srrs * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19198160Srrs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20198160Srrs * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21198160Srrs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22198160Srrs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23198160Srrs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24198160Srrs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25198160Srrs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26198160Srrs * POSSIBILITY OF SUCH DAMAGE. 27198160Srrs */ 28211994Sjchandra 29211994Sjchandra#ifndef _SH3_DEVREG_H_ 30211994Sjchandra#define _SH3_DEVREG_H_ 31211994Sjchandra/* 32198160Srrs * SH embedded device register defines. 33198160Srrs */ 34198160Srrs 35198160Srrs/* 36198160Srrs * Access method 37208165Srrs */ 38208165Srrs#define _reg_read_1(a) (*(volatile uint8_t *)((vaddr_t)(a))) 39208165Srrs#define _reg_read_2(a) (*(volatile uint16_t *)((vaddr_t)(a))) 40198160Srrs#define _reg_read_4(a) (*(volatile uint32_t *)((vaddr_t)(a))) 41204130Srrs#define _reg_write_1(a, v) \ 42204130Srrs (*(volatile uint8_t *)(a) = (uint8_t)(v)) 43204130Srrs#define _reg_write_2(a, v) \ 44204130Srrs (*(volatile uint16_t *)(a) = (uint16_t)(v)) 45211893Sjchandra#define _reg_write_4(a, v) \ 46211893Sjchandra (*(volatile uint32_t *)(a) = (uint32_t)(v)) 47211893Sjchandra#define _reg_bset_1(a, v) \ 48211893Sjchandra (*(volatile uint8_t *)(a) |= (uint8_t)(v)) 49204130Srrs#define _reg_bset_2(a, v) \ 50198625Srrs (*(volatile uint16_t *)(a) |= (uint16_t)(v)) 51#define _reg_bset_4(a, v) \ 52 (*(volatile uint32_t *)(a) |= (uint32_t)(v)) 53#define _reg_bclr_1(a, v) \ 54 (*(volatile uint8_t *)(a) &= ~(uint8_t)(v)) 55#define _reg_bclr_2(a, v) \ 56 (*(volatile uint16_t *)(a) &= ~(uint16_t)(v)) 57#define _reg_bclr_4(a, v) \ 58 (*(volatile uint32_t *)(a) &= ~(uint32_t)(v)) 59 60/* 61 * Register address. 62 */ 63#if defined(SH3) && defined(SH4) 64#define SH_(x) __sh_ ## x 65#elif defined(SH3) 66#define SH_(x) SH3_ ## x 67#elif defined(SH4) 68#define SH_(x) SH4_ ## x 69#endif 70 71#ifndef _LOCORE 72/* Initialize register address for SH3 && SH4 kernel. */ 73void sh_devreg_init(void); 74#endif 75#endif /* !_SH3_DEVREG_H_ */ 76