1/*	$NetBSD: cache_sh3.h,v 1.9 2008/04/28 20:23:35 martin Exp $	*/
2
3/*-
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A
34 */
35#ifndef _SH3_CACHE_SH3_H_
36#define	_SH3_CACHE_SH3_H_
37#include <sh3/devreg.h>
38#ifdef _KERNEL
39
40#define	SH3_CCR			0xffffffec
41#define	  SH3_CCR_CE		  0x00000001
42#define	  SH3_CCR_WT		  0x00000002
43/* SH7708 don't have CB bit */
44#define	  SH3_CCR_CB		  0x00000004
45#define	  SH3_CCR_CF		  0x00000008
46/* SH7709A don't have RA bit */
47#define	  SH3_CCR_RA		  0x00000020
48
49/* SH7709A specific cache-lock control register */
50#define	SH7709A_CCR2		0xa40000b0
51#define	  SH7709A_CCR2_W2LOCK	  0x00000001
52#define	  SH7709A_CCR2_W2LOAD	  0x00000002
53#define	  SH7709A_CCR2_W3LOCK	  0x00000100
54#define	  SH7709A_CCR2_W3LOAD	  0x00000200
55
56#define	SH3_CCA			0xf0000000
57/* Address specification */
58#define	  CCA_A			  0x00000008
59#define	  CCA_ENTRY_SHIFT	  4
60/* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */
61#define	  CCA_8K_ENTRY		  128
62#define	  CCA_8K_ENTRY_MASK	  0x000007f0	/* [10:4] */
63#define	  CCA_8K_WAY_SHIFT	  11
64#define	  CCA_8K_WAY_MASK	  0x00001800	/* [12:11] */
65/* 16KB cache (SH7709A) */
66#define	  CCA_16K_ENTRY		  256
67#define	  CCA_16K_ENTRY_MASK	  0x00000ff0	/* [11:4] */
68#define	  CCA_16K_WAY_SHIFT	  12
69#define	  CCA_16K_WAY_MASK	  0x00003000	/* [13:12] */
70
71/* Data specification */
72#define	  CCA_V			  0x00000001
73#define	  CCA_U			  0x00000002
74#define	  CCA_LRU_SHIFT		  4
75#define	  CCA_LRU_MASK		  0x000003f0	/* [9:4] */
76#define	  CCA_TAGADDR_SHIFT	  10
77#define	  CCA_TAGADDR_MASK	  0xfffffc00	/* [31:10] */
78
79#define	SH3_CCD			0xf1000000
80/* Address specification */
81#define	  CCD_L_SHIFT		  2
82#define	  CCD_L_MASK		  0x0000000c	/* [3:2] */
83#define	  CCD_E_SHIFT		  4
84#define	  CCD_8K_E_MASK		  0x000007f0	/* [10:4] */
85#define	  CCD_16K_E_MASK	  0x00000ff0	/* [11:4] */
86#define	  CCD_8K_W_SHIFT	  11
87#define	  CCD_8K_W_MASK		  0x00001800	/* [12:11] */
88#define	  CCD_16K_W_SHIFT	  12
89#define	  CCD_16K_W_MASK	  0x00003000	/* [13:12] */
90/* Data specification */
91
92/*
93 * Configuration
94 */
95#define	SH3_CACHE_LINESZ		16
96#define	SH3_CACHE_NORMAL_WAY		4
97#define	SH3_CACHE_RAMMODE_WAY		2
98
99#define	SH3_CACHE_8K_ENTRY		128
100#define	SH3_CACHE_8K_WAY_NORMAL		4
101#define	SH3_CACHE_8K_WAY_RAMMODE	2
102
103#define	SH3_CACHE_16K_ENTRY		256
104#define	SH3_CACHE_16K_WAY		4
105
106/*
107 * cache flush macro for locore level code.
108 */
109#define	SH3_CACHE_8K_FLUSH(maxway)					\
110do {									\
111	uint32_t __e, __w, __wa, __a;					\
112									\
113	for (__w = 0; __w < maxway; __w++) {				\
114		__wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT;		\
115		for (__e = 0; __e < CCA_8K_ENTRY; __e++)	{	\
116			__a = __wa |(__e << CCA_ENTRY_SHIFT);		\
117			(*(volatile uint32_t *)__a) &=		\
118				~(CCA_U | CCA_V);			\
119		}							\
120	}								\
121} while (/*CONSTCOND*/0)
122
123#define	SH3_CACHE_16K_FLUSH()						\
124do {									\
125	uint32_t __e, __w, __wa, __a;					\
126									\
127	for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) {			\
128		__wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT;		\
129		for (__e = 0; __e < CCA_16K_ENTRY; __e++)	{	\
130			__a = __wa |(__e << CCA_ENTRY_SHIFT);		\
131			(*(volatile uint32_t *)__a) &=		\
132				~(CCA_U | CCA_V);			\
133		}							\
134	}								\
135} while (/*CONSTCOND*/0)
136
137#define	SH7708_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
138#define	SH7708_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
139#define	SH7708S_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
140#define	SH7708S_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
141#define	SH7708R_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
142#define	SH7708R_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
143#define	SH7709_CACHE_FLUSH()		SH3_CACHE_8K_FLUSH(4)
144#define	SH7709_CACHE_FLUSH_RAMMODE()	SH3_CACHE_8K_FLUSH(2)
145#define	SH7709A_CACHE_FLUSH()		SH3_CACHE_16K_FLUSH()
146#define	SH7706_CACHE_FLUSH()		SH3_CACHE_16K_FLUSH()
147
148#ifndef _LOCORE
149extern void sh3_cache_config(void);
150#endif
151#endif /* _KERNEL */
152#endif /* !_SH3_CACHE_SH3_H_ */
153