if_mec.c revision 1.64
1/* $NetBSD: if_mec.c,v 1.64 2022/09/18 13:26:40 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2004, 2008 Izumi Tsutsui. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * Copyright (c) 2003 Christopher SEKIYA 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. All advertising materials mentioning features or use of this software 40 * must display the following acknowledgement: 41 * This product includes software developed for the 42 * NetBSD Project. See http://www.NetBSD.org/ for 43 * information about NetBSD. 44 * 4. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59/* 60 * MACE MAC-110 Ethernet driver 61 */ 62 63#include <sys/cdefs.h> 64__KERNEL_RCSID(0, "$NetBSD: if_mec.c,v 1.64 2022/09/18 13:26:40 thorpej Exp $"); 65 66#include "opt_ddb.h" 67 68#include <sys/param.h> 69#include <sys/systm.h> 70#include <sys/device.h> 71#include <sys/callout.h> 72#include <sys/mbuf.h> 73#include <sys/malloc.h> 74#include <sys/kernel.h> 75#include <sys/socket.h> 76#include <sys/ioctl.h> 77#include <sys/errno.h> 78 79#include <sys/rndsource.h> 80 81#include <net/if.h> 82#include <net/if_dl.h> 83#include <net/if_media.h> 84#include <net/if_ether.h> 85 86#include <netinet/in.h> 87#include <netinet/in_systm.h> 88#include <netinet/ip.h> 89#include <netinet/tcp.h> 90#include <netinet/udp.h> 91 92#include <net/bpf.h> 93 94#include <sys/bus.h> 95#include <machine/intr.h> 96#include <machine/machtype.h> 97 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100 101#include <sgimips/mace/macevar.h> 102#include <sgimips/mace/if_mecreg.h> 103 104#include <dev/arcbios/arcbios.h> 105#include <dev/arcbios/arcbiosvar.h> 106 107/* #define MEC_DEBUG */ 108 109#ifdef MEC_DEBUG 110#define MEC_DEBUG_RESET 0x01 111#define MEC_DEBUG_START 0x02 112#define MEC_DEBUG_STOP 0x04 113#define MEC_DEBUG_INTR 0x08 114#define MEC_DEBUG_RXINTR 0x10 115#define MEC_DEBUG_TXINTR 0x20 116#define MEC_DEBUG_TXSEGS 0x40 117uint32_t mec_debug = 0; 118#define DPRINTF(x, y) if (mec_debug & (x)) printf y 119#else 120#define DPRINTF(x, y) /* nothing */ 121#endif 122 123/* #define MEC_EVENT_COUNTERS */ 124 125#ifdef MEC_EVENT_COUNTERS 126#define MEC_EVCNT_INCR(ev) (ev)->ev_count++ 127#else 128#define MEC_EVCNT_INCR(ev) do {} while (/* CONSTCOND */ 0) 129#endif 130 131/* 132 * Transmit descriptor list size 133 */ 134#define MEC_NTXDESC 64 135#define MEC_NTXDESC_MASK (MEC_NTXDESC - 1) 136#define MEC_NEXTTX(x) (((x) + 1) & MEC_NTXDESC_MASK) 137#define MEC_NTXDESC_RSVD 4 138#define MEC_NTXDESC_INTR 8 139 140/* 141 * software state for TX 142 */ 143struct mec_txsoft { 144 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 145 bus_dmamap_t txs_dmamap; /* our DMA map */ 146 uint32_t txs_flags; 147#define MEC_TXS_BUFLEN_MASK 0x0000007f /* data len in txd_buf */ 148#define MEC_TXS_TXDPTR 0x00000080 /* concat txd_ptr is used */ 149}; 150 151/* 152 * Transmit buffer descriptor 153 */ 154#define MEC_TXDESCSIZE 128 155#define MEC_NTXPTR 3 156#define MEC_TXD_BUFOFFSET sizeof(uint64_t) 157#define MEC_TXD_BUFOFFSET1 \ 158 (sizeof(uint64_t) + sizeof(uint64_t) * MEC_NTXPTR) 159#define MEC_TXD_BUFSIZE (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET) 160#define MEC_TXD_BUFSIZE1 (MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET1) 161#define MEC_TXD_BUFSTART(len) (MEC_TXD_BUFSIZE - (len)) 162#define MEC_TXD_ALIGN 8 163#define MEC_TXD_ALIGNMASK (MEC_TXD_ALIGN - 1) 164#define MEC_TXD_ROUNDUP(addr) \ 165 (((addr) + MEC_TXD_ALIGNMASK) & ~(uint64_t)MEC_TXD_ALIGNMASK) 166#define MEC_NTXSEG 16 167 168struct mec_txdesc { 169 volatile uint64_t txd_cmd; 170#define MEC_TXCMD_DATALEN 0x000000000000ffff /* data length */ 171#define MEC_TXCMD_BUFSTART 0x00000000007f0000 /* start byte offset */ 172#define TXCMD_BUFSTART(x) ((x) << 16) 173#define MEC_TXCMD_TERMDMA 0x0000000000800000 /* stop DMA on abort */ 174#define MEC_TXCMD_TXINT 0x0000000001000000 /* INT after TX done */ 175#define MEC_TXCMD_PTR1 0x0000000002000000 /* valid 1st txd_ptr */ 176#define MEC_TXCMD_PTR2 0x0000000004000000 /* valid 2nd txd_ptr */ 177#define MEC_TXCMD_PTR3 0x0000000008000000 /* valid 3rd txd_ptr */ 178#define MEC_TXCMD_UNUSED 0xfffffffff0000000ULL /* should be zero */ 179 180#define txd_stat txd_cmd 181#define MEC_TXSTAT_LEN 0x000000000000ffff /* TX length */ 182#define MEC_TXSTAT_COLCNT 0x00000000000f0000 /* collision count */ 183#define MEC_TXSTAT_COLCNT_SHIFT 16 184#define MEC_TXSTAT_LATE_COL 0x0000000000100000 /* late collision */ 185#define MEC_TXSTAT_CRCERROR 0x0000000000200000 /* */ 186#define MEC_TXSTAT_DEFERRED 0x0000000000400000 /* */ 187#define MEC_TXSTAT_SUCCESS 0x0000000000800000 /* TX complete */ 188#define MEC_TXSTAT_TOOBIG 0x0000000001000000 /* */ 189#define MEC_TXSTAT_UNDERRUN 0x0000000002000000 /* */ 190#define MEC_TXSTAT_COLLISIONS 0x0000000004000000 /* */ 191#define MEC_TXSTAT_EXDEFERRAL 0x0000000008000000 /* */ 192#define MEC_TXSTAT_COLLIDED 0x0000000010000000 /* */ 193#define MEC_TXSTAT_UNUSED 0x7fffffffe0000000ULL /* should be zero */ 194#define MEC_TXSTAT_SENT 0x8000000000000000ULL /* packet sent */ 195 196 union { 197 uint64_t txptr[MEC_NTXPTR]; 198#define MEC_TXPTR_UNUSED2 0x0000000000000007 /* should be zero */ 199#define MEC_TXPTR_DMAADDR 0x00000000fffffff8 /* TX DMA address */ 200#define MEC_TXPTR_LEN 0x0000ffff00000000ULL /* buffer length */ 201#define TXPTR_LEN(x) ((uint64_t)(x) << 32) 202#define MEC_TXPTR_UNUSED1 0xffff000000000000ULL /* should be zero */ 203 204 uint8_t txbuf[MEC_TXD_BUFSIZE]; 205 } txd_data; 206#define txd_ptr txd_data.txptr 207#define txd_buf txd_data.txbuf 208}; 209 210/* 211 * Receive buffer size 212 */ 213#define MEC_NRXDESC 16 214#define MEC_NRXDESC_MASK (MEC_NRXDESC - 1) 215#define MEC_NEXTRX(x) (((x) + 1) & MEC_NRXDESC_MASK) 216 217/* 218 * Receive buffer description 219 */ 220#define MEC_RXDESCSIZE 4096 /* umm, should be 4kbyte aligned */ 221#define MEC_RXD_NRXPAD 3 222#define MEC_RXD_DMAOFFSET (1 + MEC_RXD_NRXPAD) 223#define MEC_RXD_BUFOFFSET (MEC_RXD_DMAOFFSET * sizeof(uint64_t)) 224#define MEC_RXD_BUFSIZE (MEC_RXDESCSIZE - MEC_RXD_BUFOFFSET) 225 226struct mec_rxdesc { 227 volatile uint64_t rxd_stat; 228#define MEC_RXSTAT_LEN 0x000000000000ffff /* data length */ 229#define MEC_RXSTAT_VIOLATION 0x0000000000010000 /* code violation (?) */ 230#define MEC_RXSTAT_UNUSED2 0x0000000000020000 /* unknown (?) */ 231#define MEC_RXSTAT_CRCERROR 0x0000000000040000 /* CRC error */ 232#define MEC_RXSTAT_MULTICAST 0x0000000000080000 /* multicast packet */ 233#define MEC_RXSTAT_BROADCAST 0x0000000000100000 /* broadcast packet */ 234#define MEC_RXSTAT_INVALID 0x0000000000200000 /* invalid preamble */ 235#define MEC_RXSTAT_LONGEVENT 0x0000000000400000 /* long packet */ 236#define MEC_RXSTAT_BADPACKET 0x0000000000800000 /* bad packet */ 237#define MEC_RXSTAT_CAREVENT 0x0000000001000000 /* carrier event */ 238#define MEC_RXSTAT_MATCHMCAST 0x0000000002000000 /* match multicast */ 239#define MEC_RXSTAT_MATCHMAC 0x0000000004000000 /* match MAC */ 240#define MEC_RXSTAT_SEQNUM 0x00000000f8000000 /* sequence number */ 241#define MEC_RXSTAT_CKSUM 0x0000ffff00000000ULL /* IP checksum */ 242#define RXSTAT_CKSUM(x) (((uint64_t)(x) & MEC_RXSTAT_CKSUM) >> 32) 243#define MEC_RXSTAT_UNUSED1 0x7fff000000000000ULL /* should be zero */ 244#define MEC_RXSTAT_RECEIVED 0x8000000000000000ULL /* set to 1 on RX */ 245 uint64_t rxd_pad1[MEC_RXD_NRXPAD]; 246 uint8_t rxd_buf[MEC_RXD_BUFSIZE]; 247}; 248 249/* 250 * control structures for DMA ops 251 */ 252struct mec_control_data { 253 /* 254 * TX descriptors and buffers 255 */ 256 struct mec_txdesc mcd_txdesc[MEC_NTXDESC]; 257 258 /* 259 * RX descriptors and buffers 260 */ 261 struct mec_rxdesc mcd_rxdesc[MEC_NRXDESC]; 262}; 263 264/* 265 * It _seems_ there are some restrictions on descriptor address: 266 * 267 * - Base address of txdescs should be 8kbyte aligned 268 * - Each txdesc should be 128byte aligned 269 * - Each rxdesc should be 4kbyte aligned 270 * 271 * So we should specify 8k align to allocalte txdescs. 272 * In this case, sizeof(struct mec_txdesc) * MEC_NTXDESC is 8192 273 * so rxdescs are also allocated at 4kbyte aligned. 274 */ 275#define MEC_CONTROL_DATA_ALIGN (8 * 1024) 276 277#define MEC_CDOFF(x) offsetof(struct mec_control_data, x) 278#define MEC_CDTXOFF(x) MEC_CDOFF(mcd_txdesc[(x)]) 279#define MEC_CDRXOFF(x) MEC_CDOFF(mcd_rxdesc[(x)]) 280 281/* 282 * software state per device 283 */ 284struct mec_softc { 285 device_t sc_dev; /* generic device structures */ 286 287 bus_space_tag_t sc_st; /* bus_space tag */ 288 bus_space_handle_t sc_sh; /* bus_space handle */ 289 bus_dma_tag_t sc_dmat; /* bus_dma tag */ 290 291 struct ethercom sc_ethercom; /* Ethernet common part */ 292 293 struct mii_data sc_mii; /* MII/media information */ 294 int sc_phyaddr; /* MII address */ 295 struct callout sc_tick_ch; /* tick callout */ 296 297 uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */ 298 299 bus_dmamap_t sc_cddmamap; /* bus_dma map for control data */ 300#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 301 302 /* pointer to allocated control data */ 303 struct mec_control_data *sc_control_data; 304#define sc_txdesc sc_control_data->mcd_txdesc 305#define sc_rxdesc sc_control_data->mcd_rxdesc 306 307 /* software state for TX descs */ 308 struct mec_txsoft sc_txsoft[MEC_NTXDESC]; 309 310 int sc_txpending; /* number of TX requests pending */ 311 int sc_txdirty; /* first dirty TX descriptor */ 312 int sc_txlast; /* last used TX descriptor */ 313 314 int sc_rxptr; /* next ready RX buffer */ 315 316 krndsource_t sc_rnd_source; /* random source */ 317#ifdef MEC_EVENT_COUNTERS 318 struct evcnt sc_ev_txpkts; /* TX packets queued total */ 319 struct evcnt sc_ev_txdpad; /* TX packets padded in txdesc buf */ 320 struct evcnt sc_ev_txdbuf; /* TX packets copied to txdesc buf */ 321 struct evcnt sc_ev_txptr1; /* TX packets using concat ptr1 */ 322 struct evcnt sc_ev_txptr1a; /* TX packets w/ptr1 ~160bytes */ 323 struct evcnt sc_ev_txptr1b; /* TX packets w/ptr1 ~256bytes */ 324 struct evcnt sc_ev_txptr1c; /* TX packets w/ptr1 ~512bytes */ 325 struct evcnt sc_ev_txptr1d; /* TX packets w/ptr1 ~1024bytes */ 326 struct evcnt sc_ev_txptr1e; /* TX packets w/ptr1 >1024bytes */ 327 struct evcnt sc_ev_txptr2; /* TX packets using concat ptr1,2 */ 328 struct evcnt sc_ev_txptr2a; /* TX packets w/ptr2 ~160bytes */ 329 struct evcnt sc_ev_txptr2b; /* TX packets w/ptr2 ~256bytes */ 330 struct evcnt sc_ev_txptr2c; /* TX packets w/ptr2 ~512bytes */ 331 struct evcnt sc_ev_txptr2d; /* TX packets w/ptr2 ~1024bytes */ 332 struct evcnt sc_ev_txptr2e; /* TX packets w/ptr2 >1024bytes */ 333 struct evcnt sc_ev_txptr3; /* TX packets using concat ptr1,2,3 */ 334 struct evcnt sc_ev_txptr3a; /* TX packets w/ptr3 ~160bytes */ 335 struct evcnt sc_ev_txptr3b; /* TX packets w/ptr3 ~256bytes */ 336 struct evcnt sc_ev_txptr3c; /* TX packets w/ptr3 ~512bytes */ 337 struct evcnt sc_ev_txptr3d; /* TX packets w/ptr3 ~1024bytes */ 338 struct evcnt sc_ev_txptr3e; /* TX packets w/ptr3 >1024bytes */ 339 struct evcnt sc_ev_txmbuf; /* TX packets copied to new mbufs */ 340 struct evcnt sc_ev_txmbufa; /* TX packets w/mbuf ~160bytes */ 341 struct evcnt sc_ev_txmbufb; /* TX packets w/mbuf ~256bytes */ 342 struct evcnt sc_ev_txmbufc; /* TX packets w/mbuf ~512bytes */ 343 struct evcnt sc_ev_txmbufd; /* TX packets w/mbuf ~1024bytes */ 344 struct evcnt sc_ev_txmbufe; /* TX packets w/mbuf >1024bytes */ 345 struct evcnt sc_ev_txptrs; /* TX packets using ptrs total */ 346 struct evcnt sc_ev_txptrc0; /* TX packets w/ptrs no hdr chain */ 347 struct evcnt sc_ev_txptrc1; /* TX packets w/ptrs 1 hdr chain */ 348 struct evcnt sc_ev_txptrc2; /* TX packets w/ptrs 2 hdr chains */ 349 struct evcnt sc_ev_txptrc3; /* TX packets w/ptrs 3 hdr chains */ 350 struct evcnt sc_ev_txptrc4; /* TX packets w/ptrs 4 hdr chains */ 351 struct evcnt sc_ev_txptrc5; /* TX packets w/ptrs 5 hdr chains */ 352 struct evcnt sc_ev_txptrc6; /* TX packets w/ptrs >5 hdr chains */ 353 struct evcnt sc_ev_txptrh0; /* TX packets w/ptrs ~8bytes hdr */ 354 struct evcnt sc_ev_txptrh1; /* TX packets w/ptrs ~16bytes hdr */ 355 struct evcnt sc_ev_txptrh2; /* TX packets w/ptrs ~32bytes hdr */ 356 struct evcnt sc_ev_txptrh3; /* TX packets w/ptrs ~64bytes hdr */ 357 struct evcnt sc_ev_txptrh4; /* TX packets w/ptrs ~80bytes hdr */ 358 struct evcnt sc_ev_txptrh5; /* TX packets w/ptrs ~96bytes hdr */ 359 struct evcnt sc_ev_txdstall; /* TX stalled due to no txdesc */ 360 struct evcnt sc_ev_txempty; /* TX empty interrupts */ 361 struct evcnt sc_ev_txsent; /* TX sent interrupts */ 362#endif 363}; 364 365#define MEC_CDTXADDR(sc, x) ((sc)->sc_cddma + MEC_CDTXOFF(x)) 366#define MEC_CDRXADDR(sc, x) ((sc)->sc_cddma + MEC_CDRXOFF(x)) 367 368#define MEC_TXDESCSYNC(sc, x, ops) \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 MEC_CDTXOFF(x), MEC_TXDESCSIZE, (ops)) 371#define MEC_TXCMDSYNC(sc, x, ops) \ 372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 373 MEC_CDTXOFF(x), sizeof(uint64_t), (ops)) 374 375#define MEC_RXSTATSYNC(sc, x, ops) \ 376 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 377 MEC_CDRXOFF(x), sizeof(uint64_t), (ops)) 378#define MEC_RXBUFSYNC(sc, x, len, ops) \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 MEC_CDRXOFF(x) + MEC_RXD_BUFOFFSET, \ 381 MEC_ETHER_ALIGN + (len), (ops)) 382 383/* XXX these values should be moved to <net/if_ether.h> ? */ 384#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 385#define MEC_ETHER_ALIGN 2 386 387static int mec_match(device_t, cfdata_t, void *); 388static void mec_attach(device_t, device_t, void *); 389 390static int mec_mii_readreg(device_t, int, int, uint16_t *); 391static int mec_mii_writereg(device_t, int, int, uint16_t); 392static int mec_mii_wait(struct mec_softc *); 393static void mec_statchg(struct ifnet *); 394 395static int mec_init(struct ifnet * ifp); 396static void mec_start(struct ifnet *); 397static void mec_watchdog(struct ifnet *); 398static void mec_tick(void *); 399static int mec_ioctl(struct ifnet *, u_long, void *); 400static void mec_reset(struct mec_softc *); 401static void mec_setfilter(struct mec_softc *); 402static int mec_intr(void *arg); 403static void mec_stop(struct ifnet *, int); 404static void mec_rxintr(struct mec_softc *); 405static void mec_rxcsum(struct mec_softc *, struct mbuf *, uint16_t, 406 uint32_t); 407static void mec_txintr(struct mec_softc *, uint32_t); 408static bool mec_shutdown(device_t, int); 409 410CFATTACH_DECL_NEW(mec, sizeof(struct mec_softc), 411 mec_match, mec_attach, NULL, NULL); 412 413static int mec_matched = 0; 414 415static int 416mec_match(device_t parent, cfdata_t cf, void *aux) 417{ 418 419 /* allow only one device */ 420 if (mec_matched) 421 return 0; 422 423 mec_matched = 1; 424 return 1; 425} 426 427static void 428mec_attach(device_t parent, device_t self, void *aux) 429{ 430 struct mec_softc *sc = device_private(self); 431 struct mace_attach_args *maa = aux; 432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 433 struct mii_data *mii = &sc->sc_mii; 434 uint64_t address, command; 435 const char *macaddr; 436 struct mii_softc *child; 437 bus_dma_segment_t seg; 438 int i, err, rseg; 439 bool mac_is_fake; 440 441 sc->sc_dev = self; 442 sc->sc_st = maa->maa_st; 443 if (bus_space_subregion(sc->sc_st, maa->maa_sh, 444 maa->maa_offset, 0, &sc->sc_sh) != 0) { 445 aprint_error(": can't map i/o space\n"); 446 return; 447 } 448 449 /* set up DMA structures */ 450 sc->sc_dmat = maa->maa_dmat; 451 452 /* 453 * Allocate the control data structures, and create and load the 454 * DMA map for it. 455 */ 456 if ((err = bus_dmamem_alloc(sc->sc_dmat, 457 sizeof(struct mec_control_data), MEC_CONTROL_DATA_ALIGN, 0, 458 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 459 aprint_error(": unable to allocate control data, error = %d\n", 460 err); 461 goto fail_0; 462 } 463 /* 464 * XXX needs re-think... 465 * control data structures contain whole RX data buffer, so 466 * BUS_DMA_COHERENT (which disables cache) may cause some performance 467 * issue on copying data from the RX buffer to mbuf on normal memory, 468 * though we have to make sure all bus_dmamap_sync(9) ops are called 469 * properly in that case. 470 */ 471 if ((err = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 472 sizeof(struct mec_control_data), 473 (void **)&sc->sc_control_data, /*BUS_DMA_COHERENT*/ 0)) != 0) { 474 aprint_error(": unable to map control data, error = %d\n", err); 475 goto fail_1; 476 } 477 memset(sc->sc_control_data, 0, sizeof(struct mec_control_data)); 478 479 if ((err = bus_dmamap_create(sc->sc_dmat, 480 sizeof(struct mec_control_data), 1, 481 sizeof(struct mec_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 482 aprint_error(": unable to create control data DMA map," 483 " error = %d\n", err); 484 goto fail_2; 485 } 486 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 487 sc->sc_control_data, sizeof(struct mec_control_data), NULL, 488 BUS_DMA_NOWAIT)) != 0) { 489 aprint_error(": unable to load control data DMA map," 490 " error = %d\n", err); 491 goto fail_3; 492 } 493 494 /* create TX buffer DMA maps */ 495 for (i = 0; i < MEC_NTXDESC; i++) { 496 if ((err = bus_dmamap_create(sc->sc_dmat, 497 MCLBYTES, MEC_NTXSEG, MCLBYTES, PAGE_SIZE, 0, 498 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 499 aprint_error(": unable to create tx DMA map %d," 500 " error = %d\n", i, err); 501 goto fail_4; 502 } 503 } 504 505 callout_init(&sc->sc_tick_ch, 0); 506 507 /* get Ethernet address from ARCBIOS */ 508 if ((macaddr = arcbios_GetEnvironmentVariable("eaddr")) == NULL) { 509 aprint_error(": unable to get MAC address!\n"); 510 goto fail_4; 511 } 512 /* 513 * On some machines the DS2502 chip storing the serial number/ 514 * mac address is on the pci riser board - if this board is 515 * missing, ARCBIOS will not know a good ethernet address (but 516 * otherwise the machine will work fine). 517 */ 518 mac_is_fake = false; 519 if (strcmp(macaddr, "ff:ff:ff:ff:ff:ff") == 0) { 520 uint32_t ui = 0; 521 const char * netaddr = 522 arcbios_GetEnvironmentVariable("netaddr"); 523 524 /* 525 * Create a MAC address by abusing the "netaddr" env var 526 */ 527 sc->sc_enaddr[0] = 0xf2; 528 sc->sc_enaddr[1] = 0x0b; 529 sc->sc_enaddr[2] = 0xa4; 530 if (netaddr) { 531 mac_is_fake = true; 532 while (*netaddr) { 533 int v = 0; 534 while (*netaddr && *netaddr != '.') { 535 if (*netaddr >= '0' && *netaddr <= '9') 536 v = v*10 + (*netaddr - '0'); 537 netaddr++; 538 } 539 ui <<= 8; 540 ui |= v; 541 if (*netaddr == '.') 542 netaddr++; 543 } 544 } 545 memcpy(sc->sc_enaddr+3, ((uint8_t *)&ui)+1, 3); 546 } 547 if (!mac_is_fake) 548 ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr); 549 550 /* set the Ethernet address */ 551 address = 0; 552 for (i = 0; i < ETHER_ADDR_LEN; i++) { 553 address = address << 8; 554 address |= sc->sc_enaddr[i]; 555 } 556 bus_space_write_8(sc->sc_st, sc->sc_sh, MEC_STATION, address); 557 558 /* reset device */ 559 mec_reset(sc); 560 561 command = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_MAC_CONTROL); 562 563 aprint_normal(": MAC-110 Ethernet, rev %u\n", 564 (u_int)((command & MEC_MAC_REVISION) >> MEC_MAC_REVISION_SHIFT)); 565 566 if (mac_is_fake) 567 aprint_normal_dev(self, 568 "could not get ethernet address from firmware" 569 " - generated one from the \"netaddr\" environment" 570 " variable\n"); 571 aprint_normal_dev(self, "Ethernet address %s\n", 572 ether_sprintf(sc->sc_enaddr)); 573 574 /* Done, now attach everything */ 575 576 mii->mii_ifp = ifp; 577 mii->mii_readreg = mec_mii_readreg; 578 mii->mii_writereg = mec_mii_writereg; 579 mii->mii_statchg = mec_statchg; 580 581 /* Set up PHY properties */ 582 sc->sc_ethercom.ec_mii = mii; 583 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 584 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 585 586 child = LIST_FIRST(&mii->mii_phys); 587 if (child == NULL) { 588 /* No PHY attached */ 589 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 590 0, NULL); 591 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 592 } else { 593 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 594 sc->sc_phyaddr = child->mii_phy; 595 } 596 597 strcpy(ifp->if_xname, device_xname(self)); 598 ifp->if_softc = sc; 599 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 600 ifp->if_ioctl = mec_ioctl; 601 ifp->if_start = mec_start; 602 ifp->if_watchdog = mec_watchdog; 603 ifp->if_init = mec_init; 604 ifp->if_stop = mec_stop; 605 ifp->if_mtu = ETHERMTU; 606 IFQ_SET_READY(&ifp->if_snd); 607 608 /* mec has dumb RX cksum support */ 609 ifp->if_capabilities = IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx; 610 611 /* We can support 802.1Q VLAN-sized frames. */ 612 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 613 614 /* attach the interface */ 615 if_attach(ifp); 616 if_deferred_start_init(ifp, NULL); 617 ether_ifattach(ifp, sc->sc_enaddr); 618 619 /* establish interrupt */ 620 cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, mec_intr, sc); 621 622 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 623 RND_TYPE_NET, RND_FLAG_DEFAULT); 624 625#ifdef MEC_EVENT_COUNTERS 626 evcnt_attach_dynamic(&sc->sc_ev_txpkts , EVCNT_TYPE_MISC, 627 NULL, device_xname(self), "TX pkts queued total"); 628 evcnt_attach_dynamic(&sc->sc_ev_txdpad , EVCNT_TYPE_MISC, 629 NULL, device_xname(self), "TX pkts padded in txdesc buf"); 630 evcnt_attach_dynamic(&sc->sc_ev_txdbuf , EVCNT_TYPE_MISC, 631 NULL, device_xname(self), "TX pkts copied to txdesc buf"); 632 evcnt_attach_dynamic(&sc->sc_ev_txptr1 , EVCNT_TYPE_MISC, 633 NULL, device_xname(self), "TX pkts using concat ptr1"); 634 evcnt_attach_dynamic(&sc->sc_ev_txptr1a , EVCNT_TYPE_MISC, 635 NULL, device_xname(self), "TX pkts w/ptr1 ~160bytes"); 636 evcnt_attach_dynamic(&sc->sc_ev_txptr1b , EVCNT_TYPE_MISC, 637 NULL, device_xname(self), "TX pkts w/ptr1 ~256bytes"); 638 evcnt_attach_dynamic(&sc->sc_ev_txptr1c , EVCNT_TYPE_MISC, 639 NULL, device_xname(self), "TX pkts w/ptr1 ~512bytes"); 640 evcnt_attach_dynamic(&sc->sc_ev_txptr1d , EVCNT_TYPE_MISC, 641 NULL, device_xname(self), "TX pkts w/ptr1 ~1024bytes"); 642 evcnt_attach_dynamic(&sc->sc_ev_txptr1e , EVCNT_TYPE_MISC, 643 NULL, device_xname(self), "TX pkts w/ptr1 >1024bytes"); 644 evcnt_attach_dynamic(&sc->sc_ev_txptr2 , EVCNT_TYPE_MISC, 645 NULL, device_xname(self), "TX pkts using concat ptr1,2"); 646 evcnt_attach_dynamic(&sc->sc_ev_txptr2a , EVCNT_TYPE_MISC, 647 NULL, device_xname(self), "TX pkts w/ptr2 ~160bytes"); 648 evcnt_attach_dynamic(&sc->sc_ev_txptr2b , EVCNT_TYPE_MISC, 649 NULL, device_xname(self), "TX pkts w/ptr2 ~256bytes"); 650 evcnt_attach_dynamic(&sc->sc_ev_txptr2c , EVCNT_TYPE_MISC, 651 NULL, device_xname(self), "TX pkts w/ptr2 ~512bytes"); 652 evcnt_attach_dynamic(&sc->sc_ev_txptr2d , EVCNT_TYPE_MISC, 653 NULL, device_xname(self), "TX pkts w/ptr2 ~1024bytes"); 654 evcnt_attach_dynamic(&sc->sc_ev_txptr2e , EVCNT_TYPE_MISC, 655 NULL, device_xname(self), "TX pkts w/ptr2 >1024bytes"); 656 evcnt_attach_dynamic(&sc->sc_ev_txptr3 , EVCNT_TYPE_MISC, 657 NULL, device_xname(self), "TX pkts using concat ptr1,2,3"); 658 evcnt_attach_dynamic(&sc->sc_ev_txptr3a , EVCNT_TYPE_MISC, 659 NULL, device_xname(self), "TX pkts w/ptr3 ~160bytes"); 660 evcnt_attach_dynamic(&sc->sc_ev_txptr3b , EVCNT_TYPE_MISC, 661 NULL, device_xname(self), "TX pkts w/ptr3 ~256bytes"); 662 evcnt_attach_dynamic(&sc->sc_ev_txptr3c , EVCNT_TYPE_MISC, 663 NULL, device_xname(self), "TX pkts w/ptr3 ~512bytes"); 664 evcnt_attach_dynamic(&sc->sc_ev_txptr3d , EVCNT_TYPE_MISC, 665 NULL, device_xname(self), "TX pkts w/ptr3 ~1024bytes"); 666 evcnt_attach_dynamic(&sc->sc_ev_txptr3e , EVCNT_TYPE_MISC, 667 NULL, device_xname(self), "TX pkts w/ptr3 >1024bytes"); 668 evcnt_attach_dynamic(&sc->sc_ev_txmbuf , EVCNT_TYPE_MISC, 669 NULL, device_xname(self), "TX pkts copied to new mbufs"); 670 evcnt_attach_dynamic(&sc->sc_ev_txmbufa , EVCNT_TYPE_MISC, 671 NULL, device_xname(self), "TX pkts w/mbuf ~160bytes"); 672 evcnt_attach_dynamic(&sc->sc_ev_txmbufb , EVCNT_TYPE_MISC, 673 NULL, device_xname(self), "TX pkts w/mbuf ~256bytes"); 674 evcnt_attach_dynamic(&sc->sc_ev_txmbufc , EVCNT_TYPE_MISC, 675 NULL, device_xname(self), "TX pkts w/mbuf ~512bytes"); 676 evcnt_attach_dynamic(&sc->sc_ev_txmbufd , EVCNT_TYPE_MISC, 677 NULL, device_xname(self), "TX pkts w/mbuf ~1024bytes"); 678 evcnt_attach_dynamic(&sc->sc_ev_txmbufe , EVCNT_TYPE_MISC, 679 NULL, device_xname(self), "TX pkts w/mbuf >1024bytes"); 680 evcnt_attach_dynamic(&sc->sc_ev_txptrs , EVCNT_TYPE_MISC, 681 NULL, device_xname(self), "TX pkts using ptrs total"); 682 evcnt_attach_dynamic(&sc->sc_ev_txptrc0 , EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "TX pkts w/ptrs no hdr chain"); 684 evcnt_attach_dynamic(&sc->sc_ev_txptrc1 , EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "TX pkts w/ptrs 1 hdr chain"); 686 evcnt_attach_dynamic(&sc->sc_ev_txptrc2 , EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "TX pkts w/ptrs 2 hdr chains"); 688 evcnt_attach_dynamic(&sc->sc_ev_txptrc3 , EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "TX pkts w/ptrs 3 hdr chains"); 690 evcnt_attach_dynamic(&sc->sc_ev_txptrc4 , EVCNT_TYPE_MISC, 691 NULL, device_xname(self), "TX pkts w/ptrs 4 hdr chains"); 692 evcnt_attach_dynamic(&sc->sc_ev_txptrc5 , EVCNT_TYPE_MISC, 693 NULL, device_xname(self), "TX pkts w/ptrs 5 hdr chains"); 694 evcnt_attach_dynamic(&sc->sc_ev_txptrc6 , EVCNT_TYPE_MISC, 695 NULL, device_xname(self), "TX pkts w/ptrs >5 hdr chains"); 696 evcnt_attach_dynamic(&sc->sc_ev_txptrh0 , EVCNT_TYPE_MISC, 697 NULL, device_xname(self), "TX pkts w/ptrs ~8bytes hdr"); 698 evcnt_attach_dynamic(&sc->sc_ev_txptrh1 , EVCNT_TYPE_MISC, 699 NULL, device_xname(self), "TX pkts w/ptrs ~16bytes hdr"); 700 evcnt_attach_dynamic(&sc->sc_ev_txptrh2 , EVCNT_TYPE_MISC, 701 NULL, device_xname(self), "TX pkts w/ptrs ~32bytes hdr"); 702 evcnt_attach_dynamic(&sc->sc_ev_txptrh3 , EVCNT_TYPE_MISC, 703 NULL, device_xname(self), "TX pkts w/ptrs ~64bytes hdr"); 704 evcnt_attach_dynamic(&sc->sc_ev_txptrh4 , EVCNT_TYPE_MISC, 705 NULL, device_xname(self), "TX pkts w/ptrs ~80bytes hdr"); 706 evcnt_attach_dynamic(&sc->sc_ev_txptrh5 , EVCNT_TYPE_MISC, 707 NULL, device_xname(self), "TX pkts w/ptrs ~96bytes hdr"); 708 evcnt_attach_dynamic(&sc->sc_ev_txdstall , EVCNT_TYPE_MISC, 709 NULL, device_xname(self), "TX stalled due to no txdesc"); 710 evcnt_attach_dynamic(&sc->sc_ev_txempty , EVCNT_TYPE_MISC, 711 NULL, device_xname(self), "TX empty interrupts"); 712 evcnt_attach_dynamic(&sc->sc_ev_txsent , EVCNT_TYPE_MISC, 713 NULL, device_xname(self), "TX sent interrupts"); 714#endif 715 716 /* set shutdown hook to reset interface on powerdown */ 717 if (pmf_device_register1(self, NULL, NULL, mec_shutdown)) 718 pmf_class_network_register(self, ifp); 719 else 720 aprint_error_dev(self, "couldn't establish power handler\n"); 721 722 return; 723 724 /* 725 * Free any resources we've allocated during the failed attach 726 * attempt. Do this in reverse order and fall though. 727 */ 728 fail_4: 729 for (i = 0; i < MEC_NTXDESC; i++) { 730 if (sc->sc_txsoft[i].txs_dmamap != NULL) 731 bus_dmamap_destroy(sc->sc_dmat, 732 sc->sc_txsoft[i].txs_dmamap); 733 } 734 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 735 fail_3: 736 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 737 fail_2: 738 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 739 sizeof(struct mec_control_data)); 740 fail_1: 741 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 742 fail_0: 743 return; 744} 745 746static int 747mec_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 748{ 749 struct mec_softc *sc = device_private(self); 750 bus_space_tag_t st = sc->sc_st; 751 bus_space_handle_t sh = sc->sc_sh; 752 uint64_t data; 753 int i, rv; 754 755 if ((rv = mec_mii_wait(sc)) != 0) 756 return rv; 757 758 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 759 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 760 delay(25); 761 bus_space_write_8(st, sh, MEC_PHY_READ_INITIATE, 1); 762 delay(25); 763 mec_mii_wait(sc); 764 765 for (i = 0; i < 20; i++) { 766 delay(30); 767 768 data = bus_space_read_8(st, sh, MEC_PHY_DATA); 769 770 if ((data & MEC_PHY_DATA_BUSY) == 0) { 771 *val = data & MEC_PHY_DATA_VALUE; 772 return 0; 773 } 774 } 775 return -1; 776} 777 778static int 779mec_mii_writereg(device_t self, int phy, int reg, uint16_t val) 780{ 781 struct mec_softc *sc = device_private(self); 782 bus_space_tag_t st = sc->sc_st; 783 bus_space_handle_t sh = sc->sc_sh; 784 int rv; 785 786 if ((rv = mec_mii_wait(sc)) != 0) { 787 printf("timed out writing %x: %hx\n", reg, val); 788 return rv; 789 } 790 791 bus_space_write_8(st, sh, MEC_PHY_ADDRESS, 792 (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER)); 793 794 delay(60); 795 796 bus_space_write_8(st, sh, MEC_PHY_DATA, val & MEC_PHY_DATA_VALUE); 797 798 delay(60); 799 800 mec_mii_wait(sc); 801 802 return 0; 803} 804 805static int 806mec_mii_wait(struct mec_softc *sc) 807{ 808 uint32_t busy; 809 int i, s; 810 811 for (i = 0; i < 100; i++) { 812 delay(30); 813 814 s = splhigh(); 815 busy = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_PHY_DATA); 816 splx(s); 817 818 if ((busy & MEC_PHY_DATA_BUSY) == 0) 819 return 0; 820#if 0 821 if (busy == 0xffff) /* XXX ? */ 822 return 0; 823#endif 824 } 825 826 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 827 return ETIMEDOUT; 828} 829 830static void 831mec_statchg(struct ifnet *ifp) 832{ 833 struct mec_softc *sc = ifp->if_softc; 834 bus_space_tag_t st = sc->sc_st; 835 bus_space_handle_t sh = sc->sc_sh; 836 uint32_t control; 837 838 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 839 control &= ~(MEC_MAC_IPGT | MEC_MAC_IPGR1 | MEC_MAC_IPGR2 | 840 MEC_MAC_FULL_DUPLEX | MEC_MAC_SPEED_SELECT); 841 842 /* must also set IPG here for duplex stuff ... */ 843 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) { 844 control |= MEC_MAC_FULL_DUPLEX; 845 } else { 846 /* set IPG */ 847 control |= MEC_MAC_IPG_DEFAULT; 848 } 849 850 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 851} 852 853static int 854mec_init(struct ifnet *ifp) 855{ 856 struct mec_softc *sc = ifp->if_softc; 857 bus_space_tag_t st = sc->sc_st; 858 bus_space_handle_t sh = sc->sc_sh; 859 struct mec_rxdesc *rxd; 860 int i, rc; 861 862 /* cancel any pending I/O */ 863 mec_stop(ifp, 0); 864 865 /* reset device */ 866 mec_reset(sc); 867 868 /* setup filter for multicast or promisc mode */ 869 mec_setfilter(sc); 870 871 /* set the TX ring pointer to the base address */ 872 bus_space_write_8(st, sh, MEC_TX_RING_BASE, MEC_CDTXADDR(sc, 0)); 873 874 sc->sc_txpending = 0; 875 sc->sc_txdirty = 0; 876 sc->sc_txlast = MEC_NTXDESC - 1; 877 878 /* put RX buffers into FIFO */ 879 for (i = 0; i < MEC_NRXDESC; i++) { 880 rxd = &sc->sc_rxdesc[i]; 881 rxd->rxd_stat = 0; 882 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 883 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 884 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 885 } 886 sc->sc_rxptr = 0; 887 888#if 0 /* XXX no info */ 889 bus_space_write_8(st, sh, MEC_TIMER, 0); 890#endif 891 892 /* 893 * MEC_DMA_TX_INT_ENABLE will be set later otherwise it causes 894 * spurious interrupts when TX buffers are empty 895 */ 896 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 897 (MEC_RXD_DMAOFFSET << MEC_DMA_RX_DMA_OFFSET_SHIFT) | 898 (MEC_NRXDESC << MEC_DMA_RX_INT_THRESH_SHIFT) | 899 MEC_DMA_TX_DMA_ENABLE | /* MEC_DMA_TX_INT_ENABLE | */ 900 MEC_DMA_RX_DMA_ENABLE | MEC_DMA_RX_INT_ENABLE); 901 902 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 903 904 if ((rc = ether_mediachange(ifp)) != 0) 905 return rc; 906 907 ifp->if_flags |= IFF_RUNNING; 908 mec_start(ifp); 909 910 return 0; 911} 912 913static void 914mec_reset(struct mec_softc *sc) 915{ 916 bus_space_tag_t st = sc->sc_st; 917 bus_space_handle_t sh = sc->sc_sh; 918 uint64_t control; 919 920 /* stop DMA first */ 921 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 922 923 /* reset chip */ 924 bus_space_write_8(st, sh, MEC_MAC_CONTROL, MEC_MAC_CORE_RESET); 925 delay(1000); 926 bus_space_write_8(st, sh, MEC_MAC_CONTROL, 0); 927 delay(1000); 928 929 /* Default to 100/half and let auto-negotiation work its magic */ 930 control = MEC_MAC_SPEED_SELECT | MEC_MAC_FILTER_MATCHMULTI | 931 MEC_MAC_IPG_DEFAULT; 932 933 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 934 /* stop DMA again for sanity */ 935 bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0); 936 937 DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n", 938 bus_space_read_8(st, sh, MEC_MAC_CONTROL))); 939} 940 941static void 942mec_start(struct ifnet *ifp) 943{ 944 struct mec_softc *sc = ifp->if_softc; 945 struct mbuf *m0, *m; 946 struct mec_txdesc *txd; 947 struct mec_txsoft *txs; 948 bus_dmamap_t dmamap; 949 bus_space_tag_t st = sc->sc_st; 950 bus_space_handle_t sh = sc->sc_sh; 951 int error, firsttx, nexttx, opending; 952 int len, bufoff, buflen, nsegs, align, resid, pseg, nptr, slen, i; 953 uint32_t txdcmd; 954 955 if ((ifp->if_flags & IFF_RUNNING) == 0) 956 return; 957 958 /* 959 * Remember the previous txpending and the first transmit descriptor. 960 */ 961 opending = sc->sc_txpending; 962 firsttx = MEC_NEXTTX(sc->sc_txlast); 963 964 DPRINTF(MEC_DEBUG_START, 965 ("%s: opending = %d, firsttx = %d\n", __func__, opending, firsttx)); 966 967 while (sc->sc_txpending < MEC_NTXDESC - 1) { 968 /* Grab a packet off the queue. */ 969 IFQ_POLL(&ifp->if_snd, m0); 970 if (m0 == NULL) 971 break; 972 m = NULL; 973 974 /* 975 * Get the next available transmit descriptor. 976 */ 977 nexttx = MEC_NEXTTX(sc->sc_txlast); 978 txd = &sc->sc_txdesc[nexttx]; 979 txs = &sc->sc_txsoft[nexttx]; 980 dmamap = txs->txs_dmamap; 981 txs->txs_flags = 0; 982 983 buflen = 0; 984 bufoff = 0; 985 resid = 0; 986 nptr = 0; /* XXX gcc */ 987 pseg = 0; /* XXX gcc */ 988 989 len = m0->m_pkthdr.len; 990 991 DPRINTF(MEC_DEBUG_START, 992 ("%s: len = %d, nexttx = %d, txpending = %d\n", 993 __func__, len, nexttx, sc->sc_txpending)); 994 995 if (len <= MEC_TXD_BUFSIZE) { 996 /* 997 * If a TX packet will fit into small txdesc buffer, 998 * just copy it into there. Maybe it's faster than 999 * checking alignment and calling bus_dma(9) etc. 1000 */ 1001 DPRINTF(MEC_DEBUG_START, ("%s: short packet\n", 1002 __func__)); 1003 IFQ_DEQUEUE(&ifp->if_snd, m0); 1004 1005 /* 1006 * I don't know if MEC chip does auto padding, 1007 * but do it manually for safety. 1008 */ 1009 if (len < ETHER_PAD_LEN) { 1010 MEC_EVCNT_INCR(&sc->sc_ev_txdpad); 1011 bufoff = MEC_TXD_BUFSTART(ETHER_PAD_LEN); 1012 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1013 memset(txd->txd_buf + bufoff + len, 0, 1014 ETHER_PAD_LEN - len); 1015 len = buflen = ETHER_PAD_LEN; 1016 } else { 1017 MEC_EVCNT_INCR(&sc->sc_ev_txdbuf); 1018 bufoff = MEC_TXD_BUFSTART(len); 1019 m_copydata(m0, 0, len, txd->txd_buf + bufoff); 1020 buflen = len; 1021 } 1022 } else { 1023 /* 1024 * If the packet won't fit the static buffer in txdesc, 1025 * we have to use the concatenate pointers to handle it. 1026 */ 1027 DPRINTF(MEC_DEBUG_START, ("%s: long packet\n", 1028 __func__)); 1029 txs->txs_flags = MEC_TXS_TXDPTR; 1030 1031 /* 1032 * Call bus_dmamap_load_mbuf(9) first to see 1033 * how many chains the TX mbuf has. 1034 */ 1035 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1036 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1037 if (error == 0) { 1038 /* 1039 * Check chains which might contain headers. 1040 * They might be so much fragmented and 1041 * it's better to copy them into txdesc buffer 1042 * since they would be small enough. 1043 */ 1044 nsegs = dmamap->dm_nsegs; 1045 for (pseg = 0; pseg < nsegs; pseg++) { 1046 slen = dmamap->dm_segs[pseg].ds_len; 1047 if (buflen + slen > 1048 MEC_TXD_BUFSIZE1 - MEC_TXD_ALIGN) 1049 break; 1050 buflen += slen; 1051 } 1052 /* 1053 * Check if the rest chains can be fit into 1054 * the concatinate pointers. 1055 */ 1056 align = dmamap->dm_segs[pseg].ds_addr & 1057 MEC_TXD_ALIGNMASK; 1058 if (align > 0) { 1059 /* 1060 * If the first chain isn't uint64_t 1061 * aligned, append the unaligned part 1062 * into txdesc buffer too. 1063 */ 1064 resid = MEC_TXD_ALIGN - align; 1065 buflen += resid; 1066 for (; pseg < nsegs; pseg++) { 1067 slen = 1068 dmamap->dm_segs[pseg].ds_len; 1069 if (slen > resid) 1070 break; 1071 resid -= slen; 1072 } 1073 } else if (pseg == 0) { 1074 /* 1075 * In this case, the first chain is 1076 * uint64_t aligned but it's too long 1077 * to put into txdesc buf. 1078 * We have to put some data into 1079 * txdesc buf even in this case, 1080 * so put MEC_TXD_ALIGN bytes there. 1081 */ 1082 buflen = resid = MEC_TXD_ALIGN; 1083 } 1084 nptr = nsegs - pseg; 1085 if (nptr <= MEC_NTXPTR) { 1086 bufoff = MEC_TXD_BUFSTART(buflen); 1087 1088 /* 1089 * Check if all the rest chains are 1090 * uint64_t aligned. 1091 */ 1092 align = 0; 1093 for (i = pseg + 1; i < nsegs; i++) 1094 align |= 1095 dmamap->dm_segs[i].ds_addr 1096 & MEC_TXD_ALIGNMASK; 1097 if (align != 0) { 1098 /* chains are not aligned */ 1099 error = -1; 1100 } 1101 } else { 1102 /* The TX mbuf chains doesn't fit. */ 1103 error = -1; 1104 } 1105 if (error == -1) 1106 bus_dmamap_unload(sc->sc_dmat, dmamap); 1107 } 1108 if (error != 0) { 1109 /* 1110 * The TX mbuf chains can't be put into 1111 * the concatinate buffers. In this case, 1112 * we have to allocate a new contiguous mbuf 1113 * and copy data into it. 1114 * 1115 * Even in this case, the Ethernet header in 1116 * the TX mbuf might be unaligned and trailing 1117 * data might be word aligned, so put 2 byte 1118 * (MEC_ETHER_ALIGN) padding at the top of the 1119 * allocated mbuf and copy TX packets. 1120 * 6 bytes (MEC_ALIGN_BYTES - MEC_ETHER_ALIGN) 1121 * at the top of the new mbuf won't be uint64_t 1122 * alignd, but we have to put some data into 1123 * txdesc buffer anyway even if the buffer 1124 * is uint64_t aligned. 1125 */ 1126 DPRINTF(MEC_DEBUG_START | MEC_DEBUG_TXSEGS, 1127 ("%s: re-allocating mbuf\n", __func__)); 1128 1129 MGETHDR(m, M_DONTWAIT, MT_DATA); 1130 if (m == NULL) { 1131 printf("%s: unable to allocate " 1132 "TX mbuf\n", 1133 device_xname(sc->sc_dev)); 1134 break; 1135 } 1136 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1137 MCLGET(m, M_DONTWAIT); 1138 if ((m->m_flags & M_EXT) == 0) { 1139 printf("%s: unable to allocate " 1140 "TX cluster\n", 1141 device_xname(sc->sc_dev)); 1142 m_freem(m); 1143 break; 1144 } 1145 } 1146 m->m_data += MEC_ETHER_ALIGN; 1147 1148 /* 1149 * Copy whole data (including unaligned part) 1150 * for following bpf_mtap(). 1151 */ 1152 m_copydata(m0, 0, len, mtod(m, void *)); 1153 m->m_pkthdr.len = m->m_len = len; 1154 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1155 dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1156 if (dmamap->dm_nsegs > 1) { 1157 /* should not happen, but for sanity */ 1158 bus_dmamap_unload(sc->sc_dmat, dmamap); 1159 error = -1; 1160 } 1161 if (error != 0) { 1162 printf("%s: unable to load TX buffer, " 1163 "error = %d\n", 1164 device_xname(sc->sc_dev), error); 1165 m_freem(m); 1166 break; 1167 } 1168 /* 1169 * Only the first segment should be put into 1170 * the concatinate pointer in this case. 1171 */ 1172 pseg = 0; 1173 nptr = 1; 1174 1175 /* 1176 * Set length of unaligned part which will be 1177 * copied into txdesc buffer. 1178 */ 1179 buflen = MEC_TXD_ALIGN - MEC_ETHER_ALIGN; 1180 bufoff = MEC_TXD_BUFSTART(buflen); 1181 resid = buflen; 1182#ifdef MEC_EVENT_COUNTERS 1183 MEC_EVCNT_INCR(&sc->sc_ev_txmbuf); 1184 if (len <= 160) 1185 MEC_EVCNT_INCR(&sc->sc_ev_txmbufa); 1186 else if (len <= 256) 1187 MEC_EVCNT_INCR(&sc->sc_ev_txmbufb); 1188 else if (len <= 512) 1189 MEC_EVCNT_INCR(&sc->sc_ev_txmbufc); 1190 else if (len <= 1024) 1191 MEC_EVCNT_INCR(&sc->sc_ev_txmbufd); 1192 else 1193 MEC_EVCNT_INCR(&sc->sc_ev_txmbufe); 1194#endif 1195 } 1196#ifdef MEC_EVENT_COUNTERS 1197 else { 1198 MEC_EVCNT_INCR(&sc->sc_ev_txptrs); 1199 if (nptr == 1) { 1200 MEC_EVCNT_INCR(&sc->sc_ev_txptr1); 1201 if (len <= 160) 1202 MEC_EVCNT_INCR( 1203 &sc->sc_ev_txptr1a); 1204 else if (len <= 256) 1205 MEC_EVCNT_INCR( 1206 &sc->sc_ev_txptr1b); 1207 else if (len <= 512) 1208 MEC_EVCNT_INCR( 1209 &sc->sc_ev_txptr1c); 1210 else if (len <= 1024) 1211 MEC_EVCNT_INCR( 1212 &sc->sc_ev_txptr1d); 1213 else 1214 MEC_EVCNT_INCR( 1215 &sc->sc_ev_txptr1e); 1216 } else if (nptr == 2) { 1217 MEC_EVCNT_INCR(&sc->sc_ev_txptr2); 1218 if (len <= 160) 1219 MEC_EVCNT_INCR( 1220 &sc->sc_ev_txptr2a); 1221 else if (len <= 256) 1222 MEC_EVCNT_INCR( 1223 &sc->sc_ev_txptr2b); 1224 else if (len <= 512) 1225 MEC_EVCNT_INCR( 1226 &sc->sc_ev_txptr2c); 1227 else if (len <= 1024) 1228 MEC_EVCNT_INCR( 1229 &sc->sc_ev_txptr2d); 1230 else 1231 MEC_EVCNT_INCR( 1232 &sc->sc_ev_txptr2e); 1233 } else if (nptr == 3) { 1234 MEC_EVCNT_INCR(&sc->sc_ev_txptr3); 1235 if (len <= 160) 1236 MEC_EVCNT_INCR( 1237 &sc->sc_ev_txptr3a); 1238 else if (len <= 256) 1239 MEC_EVCNT_INCR( 1240 &sc->sc_ev_txptr3b); 1241 else if (len <= 512) 1242 MEC_EVCNT_INCR( 1243 &sc->sc_ev_txptr3c); 1244 else if (len <= 1024) 1245 MEC_EVCNT_INCR( 1246 &sc->sc_ev_txptr3d); 1247 else 1248 MEC_EVCNT_INCR( 1249 &sc->sc_ev_txptr3e); 1250 } 1251 if (pseg == 0) 1252 MEC_EVCNT_INCR(&sc->sc_ev_txptrc0); 1253 else if (pseg == 1) 1254 MEC_EVCNT_INCR(&sc->sc_ev_txptrc1); 1255 else if (pseg == 2) 1256 MEC_EVCNT_INCR(&sc->sc_ev_txptrc2); 1257 else if (pseg == 3) 1258 MEC_EVCNT_INCR(&sc->sc_ev_txptrc3); 1259 else if (pseg == 4) 1260 MEC_EVCNT_INCR(&sc->sc_ev_txptrc4); 1261 else if (pseg == 5) 1262 MEC_EVCNT_INCR(&sc->sc_ev_txptrc5); 1263 else 1264 MEC_EVCNT_INCR(&sc->sc_ev_txptrc6); 1265 if (buflen <= 8) 1266 MEC_EVCNT_INCR(&sc->sc_ev_txptrh0); 1267 else if (buflen <= 16) 1268 MEC_EVCNT_INCR(&sc->sc_ev_txptrh1); 1269 else if (buflen <= 32) 1270 MEC_EVCNT_INCR(&sc->sc_ev_txptrh2); 1271 else if (buflen <= 64) 1272 MEC_EVCNT_INCR(&sc->sc_ev_txptrh3); 1273 else if (buflen <= 80) 1274 MEC_EVCNT_INCR(&sc->sc_ev_txptrh4); 1275 else 1276 MEC_EVCNT_INCR(&sc->sc_ev_txptrh5); 1277 } 1278#endif 1279 m_copydata(m0, 0, buflen, txd->txd_buf + bufoff); 1280 1281 IFQ_DEQUEUE(&ifp->if_snd, m0); 1282 if (m != NULL) { 1283 m_freem(m0); 1284 m0 = m; 1285 } 1286 1287 /* 1288 * sync the DMA map for TX mbuf 1289 */ 1290 bus_dmamap_sync(sc->sc_dmat, dmamap, buflen, 1291 len - buflen, BUS_DMASYNC_PREWRITE); 1292 } 1293 1294 /* 1295 * Pass packet to bpf if there is a listener. 1296 */ 1297 bpf_mtap(ifp, m0, BPF_D_OUT); 1298 MEC_EVCNT_INCR(&sc->sc_ev_txpkts); 1299 1300 /* 1301 * setup the transmit descriptor. 1302 */ 1303 txdcmd = TXCMD_BUFSTART(MEC_TXDESCSIZE - buflen) | (len - 1); 1304 1305 /* 1306 * Set MEC_TXCMD_TXINT every MEC_NTXDESC_INTR packets 1307 * if more than half txdescs have been queued 1308 * because TX_EMPTY interrupts will rarely happen 1309 * if TX queue is so stacked. 1310 */ 1311 if (sc->sc_txpending > (MEC_NTXDESC / 2) && 1312 (nexttx & (MEC_NTXDESC_INTR - 1)) == 0) 1313 txdcmd |= MEC_TXCMD_TXINT; 1314 1315 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1316 bus_dma_segment_t *segs = dmamap->dm_segs; 1317 1318 DPRINTF(MEC_DEBUG_TXSEGS, 1319 ("%s: nsegs = %d, pseg = %d, nptr = %d\n", 1320 __func__, dmamap->dm_nsegs, pseg, nptr)); 1321 1322 switch (nptr) { 1323 case 3: 1324 KASSERT((segs[pseg + 2].ds_addr & 1325 MEC_TXD_ALIGNMASK) == 0); 1326 txdcmd |= MEC_TXCMD_PTR3; 1327 txd->txd_ptr[2] = 1328 TXPTR_LEN(segs[pseg + 2].ds_len - 1) | 1329 segs[pseg + 2].ds_addr; 1330 /* FALLTHROUGH */ 1331 case 2: 1332 KASSERT((segs[pseg + 1].ds_addr & 1333 MEC_TXD_ALIGNMASK) == 0); 1334 txdcmd |= MEC_TXCMD_PTR2; 1335 txd->txd_ptr[1] = 1336 TXPTR_LEN(segs[pseg + 1].ds_len - 1) | 1337 segs[pseg + 1].ds_addr; 1338 /* FALLTHROUGH */ 1339 case 1: 1340 txdcmd |= MEC_TXCMD_PTR1; 1341 txd->txd_ptr[0] = 1342 TXPTR_LEN(segs[pseg].ds_len - resid - 1) | 1343 (segs[pseg].ds_addr + resid); 1344 break; 1345 default: 1346 panic("%s: impossible nptr in %s", 1347 device_xname(sc->sc_dev), __func__); 1348 /* NOTREACHED */ 1349 } 1350 /* 1351 * Store a pointer to the packet so we can 1352 * free it later. 1353 */ 1354 txs->txs_mbuf = m0; 1355 } else { 1356 /* 1357 * In this case all data are copied to buffer in txdesc, 1358 * we can free TX mbuf here. 1359 */ 1360 m_freem(m0); 1361 } 1362 txd->txd_cmd = txdcmd; 1363 1364 DPRINTF(MEC_DEBUG_START, 1365 ("%s: txd_cmd = 0x%016llx\n", 1366 __func__, txd->txd_cmd)); 1367 DPRINTF(MEC_DEBUG_START, 1368 ("%s: txd_ptr[0] = 0x%016llx\n", 1369 __func__, txd->txd_ptr[0])); 1370 DPRINTF(MEC_DEBUG_START, 1371 ("%s: txd_ptr[1] = 0x%016llx\n", 1372 __func__, txd->txd_ptr[1])); 1373 DPRINTF(MEC_DEBUG_START, 1374 ("%s: txd_ptr[2] = 0x%016llx\n", 1375 __func__, txd->txd_ptr[2])); 1376 DPRINTF(MEC_DEBUG_START, 1377 ("%s: len = %d (0x%04x), buflen = %d (0x%02x)\n", 1378 __func__, len, len, buflen, buflen)); 1379 1380 /* sync TX descriptor */ 1381 MEC_TXDESCSYNC(sc, nexttx, 1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1383 1384 /* start TX */ 1385 bus_space_write_8(st, sh, MEC_TX_RING_PTR, MEC_NEXTTX(nexttx)); 1386 1387 /* advance the TX pointer. */ 1388 sc->sc_txpending++; 1389 sc->sc_txlast = nexttx; 1390 } 1391 1392 if (sc->sc_txpending == MEC_NTXDESC - 1) { 1393 /* No more slots. */ 1394 MEC_EVCNT_INCR(&sc->sc_ev_txdstall); 1395 } 1396 1397 if (sc->sc_txpending != opending) { 1398 /* 1399 * If the transmitter was idle, 1400 * reset the txdirty pointer and re-enable TX interrupt. 1401 */ 1402 if (opending == 0) { 1403 sc->sc_txdirty = firsttx; 1404 bus_space_write_8(st, sh, MEC_TX_ALIAS, 1405 MEC_TX_ALIAS_INT_ENABLE); 1406 } 1407 1408 /* Set a watchdog timer in case the chip flakes out. */ 1409 ifp->if_timer = 5; 1410 } 1411} 1412 1413static void 1414mec_stop(struct ifnet *ifp, int disable) 1415{ 1416 struct mec_softc *sc = ifp->if_softc; 1417 struct mec_txsoft *txs; 1418 int i; 1419 1420 DPRINTF(MEC_DEBUG_STOP, ("%s\n", __func__)); 1421 1422 ifp->if_timer = 0; 1423 ifp->if_flags &= ~IFF_RUNNING; 1424 1425 callout_stop(&sc->sc_tick_ch); 1426 mii_down(&sc->sc_mii); 1427 1428 /* release any TX buffers */ 1429 for (i = 0; i < MEC_NTXDESC; i++) { 1430 txs = &sc->sc_txsoft[i]; 1431 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1432 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1433 m_freem(txs->txs_mbuf); 1434 txs->txs_mbuf = NULL; 1435 } 1436 } 1437} 1438 1439static int 1440mec_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1441{ 1442 int s, error; 1443 1444 s = splnet(); 1445 1446 error = ether_ioctl(ifp, cmd, data); 1447 if (error == ENETRESET) { 1448 /* 1449 * Multicast list has changed; set the hardware filter 1450 * accordingly. 1451 */ 1452 if (ifp->if_flags & IFF_RUNNING) 1453 error = mec_init(ifp); 1454 else 1455 error = 0; 1456 } 1457 1458 /* Try to get more packets going. */ 1459 mec_start(ifp); 1460 1461 splx(s); 1462 return error; 1463} 1464 1465static void 1466mec_watchdog(struct ifnet *ifp) 1467{ 1468 struct mec_softc *sc = ifp->if_softc; 1469 1470 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1471 if_statinc(ifp, if_oerrors); 1472 1473 mec_init(ifp); 1474} 1475 1476static void 1477mec_tick(void *arg) 1478{ 1479 struct mec_softc *sc = arg; 1480 int s; 1481 1482 s = splnet(); 1483 mii_tick(&sc->sc_mii); 1484 splx(s); 1485 1486 callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc); 1487} 1488 1489static void 1490mec_setfilter(struct mec_softc *sc) 1491{ 1492 struct ethercom *ec = &sc->sc_ethercom; 1493 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1494 struct ether_multi *enm; 1495 struct ether_multistep step; 1496 bus_space_tag_t st = sc->sc_st; 1497 bus_space_handle_t sh = sc->sc_sh; 1498 uint64_t mchash; 1499 uint32_t control, hash; 1500 int mcnt; 1501 1502 control = bus_space_read_8(st, sh, MEC_MAC_CONTROL); 1503 control &= ~MEC_MAC_FILTER_MASK; 1504 1505 if (ifp->if_flags & IFF_PROMISC) { 1506 control |= MEC_MAC_FILTER_PROMISC; 1507 bus_space_write_8(st, sh, MEC_MULTICAST, 0xffffffffffffffffULL); 1508 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1509 return; 1510 } 1511 1512 mcnt = 0; 1513 mchash = 0; 1514 ETHER_LOCK(ec); 1515 ETHER_FIRST_MULTI(step, ec, enm); 1516 while (enm != NULL) { 1517 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1518 /* set allmulti for a range of multicast addresses */ 1519 control |= MEC_MAC_FILTER_ALLMULTI; 1520 bus_space_write_8(st, sh, MEC_MULTICAST, 1521 0xffffffffffffffffULL); 1522 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1523 ETHER_UNLOCK(ec); 1524 return; 1525 } 1526 1527#define mec_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 1528 1529 hash = mec_calchash(enm->enm_addrlo); 1530 mchash |= 1 << hash; 1531 mcnt++; 1532 ETHER_NEXT_MULTI(step, enm); 1533 } 1534 ETHER_UNLOCK(ec); 1535 1536 ifp->if_flags &= ~IFF_ALLMULTI; 1537 1538 if (mcnt > 0) 1539 control |= MEC_MAC_FILTER_MATCHMULTI; 1540 1541 bus_space_write_8(st, sh, MEC_MULTICAST, mchash); 1542 bus_space_write_8(st, sh, MEC_MAC_CONTROL, control); 1543} 1544 1545static int 1546mec_intr(void *arg) 1547{ 1548 struct mec_softc *sc = arg; 1549 bus_space_tag_t st = sc->sc_st; 1550 bus_space_handle_t sh = sc->sc_sh; 1551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1552 uint32_t statreg, statack, txptr; 1553 int handled, sent; 1554 1555 DPRINTF(MEC_DEBUG_INTR, ("%s: called\n", __func__)); 1556 1557 handled = sent = 0; 1558 1559 for (;;) { 1560 statreg = bus_space_read_8(st, sh, MEC_INT_STATUS); 1561 1562 DPRINTF(MEC_DEBUG_INTR, 1563 ("%s: INT_STAT = 0x%08x\n", __func__, statreg)); 1564 1565 statack = statreg & MEC_INT_STATUS_MASK; 1566 if (statack == 0) 1567 break; 1568 bus_space_write_8(st, sh, MEC_INT_STATUS, statack); 1569 1570 handled = 1; 1571 1572 if (statack & 1573 (MEC_INT_RX_THRESHOLD | 1574 MEC_INT_RX_FIFO_UNDERFLOW)) { 1575 mec_rxintr(sc); 1576 } 1577 1578 if (statack & 1579 (MEC_INT_TX_EMPTY | 1580 MEC_INT_TX_PACKET_SENT | 1581 MEC_INT_TX_ABORT)) { 1582 txptr = (statreg & MEC_INT_TX_RING_BUFFER_ALIAS) 1583 >> MEC_INT_TX_RING_BUFFER_SHIFT; 1584 mec_txintr(sc, txptr); 1585 sent = 1; 1586 if ((statack & MEC_INT_TX_EMPTY) != 0) { 1587 /* 1588 * disable TX interrupt to stop 1589 * TX empty interrupt 1590 */ 1591 bus_space_write_8(st, sh, MEC_TX_ALIAS, 0); 1592 DPRINTF(MEC_DEBUG_INTR, 1593 ("%s: disable TX_INT\n", __func__)); 1594 } 1595#ifdef MEC_EVENT_COUNTERS 1596 if ((statack & MEC_INT_TX_EMPTY) != 0) 1597 MEC_EVCNT_INCR(&sc->sc_ev_txempty); 1598 if ((statack & MEC_INT_TX_PACKET_SENT) != 0) 1599 MEC_EVCNT_INCR(&sc->sc_ev_txsent); 1600#endif 1601 } 1602 1603 if (statack & 1604 (MEC_INT_TX_LINK_FAIL | 1605 MEC_INT_TX_MEM_ERROR | 1606 MEC_INT_TX_ABORT | 1607 MEC_INT_RX_DMA_UNDERFLOW)) { 1608 printf("%s: %s: interrupt status = 0x%08x\n", 1609 device_xname(sc->sc_dev), __func__, statreg); 1610 mec_init(ifp); 1611 break; 1612 } 1613 } 1614 1615 if (sent) { 1616 /* try to get more packets going */ 1617 if_schedule_deferred_start(ifp); 1618 } 1619 1620 if (handled) 1621 rnd_add_uint32(&sc->sc_rnd_source, statreg); 1622 1623 return handled; 1624} 1625 1626static void 1627mec_rxintr(struct mec_softc *sc) 1628{ 1629 bus_space_tag_t st = sc->sc_st; 1630 bus_space_handle_t sh = sc->sc_sh; 1631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1632 struct mbuf *m; 1633 struct mec_rxdesc *rxd; 1634 uint64_t rxstat; 1635 u_int len; 1636 int i; 1637 uint32_t crc; 1638 1639 DPRINTF(MEC_DEBUG_RXINTR, ("%s: called\n", __func__)); 1640 1641 for (i = sc->sc_rxptr;; i = MEC_NEXTRX(i)) { 1642 rxd = &sc->sc_rxdesc[i]; 1643 1644 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD); 1645 rxstat = rxd->rxd_stat; 1646 1647 DPRINTF(MEC_DEBUG_RXINTR, 1648 ("%s: rxstat = 0x%016llx, rxptr = %d\n", 1649 __func__, rxstat, i)); 1650 DPRINTF(MEC_DEBUG_RXINTR, ("%s: rxfifo = 0x%08x\n", 1651 __func__, (u_int)bus_space_read_8(st, sh, MEC_RX_FIFO))); 1652 1653 if ((rxstat & MEC_RXSTAT_RECEIVED) == 0) { 1654 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1655 break; 1656 } 1657 1658 len = rxstat & MEC_RXSTAT_LEN; 1659 1660 if (len < ETHER_MIN_LEN || 1661 len > (MCLBYTES - MEC_ETHER_ALIGN)) { 1662 /* invalid length packet; drop it. */ 1663 DPRINTF(MEC_DEBUG_RXINTR, 1664 ("%s: wrong packet\n", __func__)); 1665 dropit: 1666 if_statinc(ifp, if_ierrors); 1667 rxd->rxd_stat = 0; 1668 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1669 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, 1670 MEC_CDRXADDR(sc, i)); 1671 continue; 1672 } 1673 1674 /* 1675 * If 802.1Q VLAN MTU is enabled, ignore the bad packet error. 1676 */ 1677 if ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) != 0) 1678 rxstat &= ~MEC_RXSTAT_BADPACKET; 1679 1680 if (rxstat & 1681 (MEC_RXSTAT_BADPACKET | 1682 MEC_RXSTAT_LONGEVENT | 1683 MEC_RXSTAT_INVALID | 1684 MEC_RXSTAT_CRCERROR | 1685 MEC_RXSTAT_VIOLATION)) { 1686 printf("%s: mec_rxintr: status = 0x%016"PRIx64"\n", 1687 device_xname(sc->sc_dev), rxstat); 1688 goto dropit; 1689 } 1690 1691 /* 1692 * The MEC includes the CRC with every packet. Trim 1693 * it off here. 1694 */ 1695 len -= ETHER_CRC_LEN; 1696 1697 /* 1698 * now allocate an mbuf (and possibly a cluster) to hold 1699 * the received packet. 1700 */ 1701 MGETHDR(m, M_DONTWAIT, MT_DATA); 1702 if (m == NULL) { 1703 printf("%s: unable to allocate RX mbuf\n", 1704 device_xname(sc->sc_dev)); 1705 goto dropit; 1706 } 1707 if (len > (MHLEN - MEC_ETHER_ALIGN)) { 1708 MCLGET(m, M_DONTWAIT); 1709 if ((m->m_flags & M_EXT) == 0) { 1710 printf("%s: unable to allocate RX cluster\n", 1711 device_xname(sc->sc_dev)); 1712 m_freem(m); 1713 m = NULL; 1714 goto dropit; 1715 } 1716 } 1717 1718 /* 1719 * Note MEC chip seems to insert 2 byte padding at the top of 1720 * RX buffer, but we copy whole buffer to avoid unaligned copy. 1721 */ 1722 MEC_RXBUFSYNC(sc, i, len + ETHER_CRC_LEN, BUS_DMASYNC_POSTREAD); 1723 memcpy(mtod(m, void *), rxd->rxd_buf, MEC_ETHER_ALIGN + len); 1724 crc = be32dec(rxd->rxd_buf + MEC_ETHER_ALIGN + len); 1725 MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD); 1726 m->m_data += MEC_ETHER_ALIGN; 1727 1728 /* put RX buffer into FIFO again */ 1729 rxd->rxd_stat = 0; 1730 MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD); 1731 bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i)); 1732 1733 m_set_rcvif(m, ifp); 1734 m->m_pkthdr.len = m->m_len = len; 1735 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1736 mec_rxcsum(sc, m, RXSTAT_CKSUM(rxstat), crc); 1737 1738 /* Pass it on. */ 1739 if_percpuq_enqueue(ifp->if_percpuq, m); 1740 } 1741 1742 /* update RX pointer */ 1743 sc->sc_rxptr = i; 1744} 1745 1746static void 1747mec_rxcsum(struct mec_softc *sc, struct mbuf *m, uint16_t rxcsum, uint32_t crc) 1748{ 1749 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1750 struct ether_header *eh; 1751 struct ip *ip; 1752 struct udphdr *uh; 1753 u_int len, pktlen, hlen; 1754 uint32_t csum_data, dsum; 1755 int csum_flags; 1756 const uint16_t *dp; 1757 1758 csum_data = 0; 1759 csum_flags = 0; 1760 1761 len = m->m_len; 1762 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1763 goto out; 1764 pktlen = len - ETHER_HDR_LEN; 1765 eh = mtod(m, struct ether_header *); 1766 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1767 goto out; 1768 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1769 if (ip->ip_v != IPVERSION) 1770 goto out; 1771 1772 hlen = ip->ip_hl << 2; 1773 if (hlen < sizeof(struct ip)) 1774 goto out; 1775 1776 /* 1777 * Bail if too short, has random trailing garbage, truncated, 1778 * fragment, or has ethernet pad. 1779 */ 1780 if (ntohs(ip->ip_len) < hlen || 1781 ntohs(ip->ip_len) != pktlen || 1782 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1783 goto out; 1784 1785 switch (ip->ip_p) { 1786 case IPPROTO_TCP: 1787 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1788 pktlen < (hlen + sizeof(struct tcphdr))) 1789 goto out; 1790 csum_flags = M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1791 break; 1792 case IPPROTO_UDP: 1793 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1794 pktlen < (hlen + sizeof(struct udphdr))) 1795 goto out; 1796 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1797 if (uh->uh_sum == 0) 1798 goto out; /* no checksum */ 1799 csum_flags = M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1800 break; 1801 default: 1802 goto out; 1803 } 1804 1805 /* 1806 * The computed checksum includes Ethernet header, IP headers, 1807 * and CRC, so we have to deduct them. 1808 * Note IP header cksum should be 0xffff so we don't have to 1809 * dedecut them. 1810 */ 1811 dsum = 0; 1812 1813 /* deduct Ethernet header */ 1814 dp = (const uint16_t *)eh; 1815 for (hlen = 0; hlen < (ETHER_HDR_LEN / sizeof(uint16_t)); hlen++) 1816 dsum += ntohs(*dp++); 1817 1818 /* deduct CRC */ 1819 if (len & 1) { 1820 dsum += (crc >> 24) & 0x00ff; 1821 dsum += (crc >> 8) & 0xffff; 1822 dsum += (crc << 8) & 0xff00; 1823 } else { 1824 dsum += (crc >> 16) & 0xffff; 1825 dsum += (crc >> 0) & 0xffff; 1826 } 1827 while (dsum >> 16) 1828 dsum = (dsum >> 16) + (dsum & 0xffff); 1829 1830 csum_data = rxcsum; 1831 csum_data += (uint16_t)~dsum; 1832 1833 while (csum_data >> 16) 1834 csum_data = (csum_data >> 16) + (csum_data & 0xffff); 1835 1836 out: 1837 m->m_pkthdr.csum_flags = csum_flags; 1838 m->m_pkthdr.csum_data = csum_data; 1839} 1840 1841static void 1842mec_txintr(struct mec_softc *sc, uint32_t txptr) 1843{ 1844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1845 struct mec_txdesc *txd; 1846 struct mec_txsoft *txs; 1847 bus_dmamap_t dmamap; 1848 uint64_t txstat; 1849 int i; 1850 u_int col; 1851 1852 DPRINTF(MEC_DEBUG_TXINTR, ("%s: called\n", __func__)); 1853 1854 for (i = sc->sc_txdirty; i != txptr && sc->sc_txpending != 0; 1855 i = MEC_NEXTTX(i), sc->sc_txpending--) { 1856 txd = &sc->sc_txdesc[i]; 1857 1858 MEC_TXCMDSYNC(sc, i, 1859 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1860 1861 txstat = txd->txd_stat; 1862 DPRINTF(MEC_DEBUG_TXINTR, 1863 ("%s: dirty = %d, txstat = 0x%016llx\n", 1864 __func__, i, txstat)); 1865 if ((txstat & MEC_TXSTAT_SENT) == 0) { 1866 MEC_TXCMDSYNC(sc, i, BUS_DMASYNC_PREREAD); 1867 break; 1868 } 1869 1870 txs = &sc->sc_txsoft[i]; 1871 if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) { 1872 dmamap = txs->txs_dmamap; 1873 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, 1874 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1875 bus_dmamap_unload(sc->sc_dmat, dmamap); 1876 m_freem(txs->txs_mbuf); 1877 txs->txs_mbuf = NULL; 1878 } 1879 1880 col = (txstat & MEC_TXSTAT_COLCNT) >> MEC_TXSTAT_COLCNT_SHIFT; 1881 if (col) 1882 if_statadd(ifp, if_collisions, col); 1883 1884 if ((txstat & MEC_TXSTAT_SUCCESS) == 0) { 1885 printf("%s: TX error: txstat = 0x%016"PRIx64"\n", 1886 device_xname(sc->sc_dev), txstat); 1887 if_statinc(ifp, if_oerrors); 1888 } else 1889 if_statinc(ifp, if_opackets); 1890 } 1891 1892 /* update the dirty TX buffer pointer */ 1893 sc->sc_txdirty = i; 1894 DPRINTF(MEC_DEBUG_INTR, 1895 ("%s: sc_txdirty = %2d, sc_txpending = %2d\n", 1896 __func__, sc->sc_txdirty, sc->sc_txpending)); 1897 1898 /* cancel the watchdog timer if there are no pending TX packets */ 1899 if (sc->sc_txpending == 0) 1900 ifp->if_timer = 0; 1901} 1902 1903static bool 1904mec_shutdown(device_t self, int howto) 1905{ 1906 struct mec_softc *sc = device_private(self); 1907 1908 mec_stop(&sc->sc_ethercom.ec_if, 1); 1909 /* make sure to stop DMA etc. */ 1910 mec_reset(sc); 1911 1912 return true; 1913} 1914