1/* $NetBSD: sysreg.h,v 1.33 2024/05/14 15:17:57 riastradh Exp $ */ 2 3/* 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _RISCV_SYSREG_H_ 33#define _RISCV_SYSREG_H_ 34 35#ifndef _KERNEL 36#include <sys/param.h> 37#endif 38 39#include <riscv/reg.h> 40 41#define FCSR_FMASK 0 // no exception bits 42#define FCSR_FRM __BITS(7, 5) 43#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even 44#define FCSR_FRM_RTZ 0b001 // Round Towards Zero 45#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) 46#define FCSR_FRM_RUP 0b011 // Round UP (+infinity) 47#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude 48#define FCSR_FRM_DYN 0b111 // Dynamic rounding 49#define FCSR_FFLAGS __BITS(4, 0) // Sticky bits 50#define FCSR_NV __BIT(4) // iNValid operation 51#define FCSR_DZ __BIT(3) // Divide by Zero 52#define FCSR_OF __BIT(2) // OverFlow 53#define FCSR_UF __BIT(1) // UnderFlow 54#define FCSR_NX __BIT(0) // iNeXact 55 56static inline uint32_t 57fcsr_read(void) 58{ 59 uint32_t __fcsr; 60 asm("frcsr %0" : "=r"(__fcsr) :: "memory"); 61 return __fcsr; 62} 63 64static inline uint32_t 65fcsr_write(uint32_t __new) 66{ 67 uint32_t __old; 68 asm volatile("fscsr %0, %1" : "=r"(__old) : "r"(__new) : "memory"); 69 return __old; 70} 71 72static inline uint32_t 73fcsr_fflags_read(void) 74{ 75 uint32_t __old; 76 asm("frflags %0" : "=r"(__old) :: "memory"); 77 return __old; 78} 79 80static inline uint32_t 81fcsr_fflags_write(uint32_t __new) 82{ 83 uint32_t __old; 84 asm volatile("fsflags %0, %1" : "=r"(__old) : "r"(__new) : "memory"); 85 return __old; 86} 87 88static inline uint32_t 89fcsr_frm_read(void) 90{ 91 uint32_t __old; 92 asm("frrm\t%0" : "=r"(__old) :: "memory"); 93 return __old; 94} 95 96static inline uint32_t 97fcsr_frm_write(uint32_t __new) 98{ 99 uint32_t __old; 100 asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new) : "memory"); 101 return __old; 102} 103 104#define RISCVREG_READ_INLINE(regname) \ 105static inline uintptr_t \ 106csr_##regname##_read(void) \ 107{ \ 108 uintptr_t __rv; \ 109 asm volatile("csrr %0, " #regname : "=r"(__rv) :: "memory"); \ 110 return __rv; \ 111} 112 113#define RISCVREG_WRITE_INLINE(regname) \ 114static inline void \ 115csr_##regname##_write(uintptr_t __val) \ 116{ \ 117 asm volatile("csrw " #regname ", %0" :: "r"(__val) : "memory"); \ 118} 119 120#define RISCVREG_SET_INLINE(regname) \ 121static inline void \ 122csr_##regname##_set(uintptr_t __mask) \ 123{ \ 124 if (__builtin_constant_p(__mask) && __mask < 0x20) { \ 125 asm volatile("csrsi " #regname ", %0" :: "i"(__mask) : \ 126 "memory"); \ 127 } else { \ 128 asm volatile("csrs " #regname ", %0" :: "r"(__mask) : \ 129 "memory"); \ 130 } \ 131} 132 133#define RISCVREG_CLEAR_INLINE(regname) \ 134static inline void \ 135csr_##regname##_clear(uintptr_t __mask) \ 136{ \ 137 if (__builtin_constant_p(__mask) && __mask < 0x20) { \ 138 asm volatile("csrci " #regname ", %0" :: "i"(__mask) : \ 139 "memory"); \ 140 } else { \ 141 asm volatile("csrc " #regname ", %0" :: "r"(__mask) : \ 142 "memory"); \ 143 } \ 144} 145 146#define RISCVREG_READ_WRITE_INLINE(regname) \ 147RISCVREG_READ_INLINE(regname) \ 148RISCVREG_WRITE_INLINE(regname) 149#define RISCVREG_SET_CLEAR_INLINE(regname) \ 150RISCVREG_SET_INLINE(regname) \ 151RISCVREG_CLEAR_INLINE(regname) 152#define RISCVREG_READ_SET_CLEAR_INLINE(regname) \ 153RISCVREG_READ_INLINE(regname) \ 154RISCVREG_SET_CLEAR_INLINE(regname) 155#define RISCVREG_READ_WRITE_SET_CLEAR_INLINE(regname) \ 156RISCVREG_READ_WRITE_INLINE(regname) \ 157RISCVREG_SET_CLEAR_INLINE(regname) 158 159/* Supervisor Status Register */ 160RISCVREG_READ_SET_CLEAR_INLINE(sstatus) // supervisor status register 161#ifdef _LP64 162#define SR_WPRI __BITS(62, 34) | __BITS(31, 20) | \ 163 __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ 164 __BIT(0) 165#define SR_SD __BIT(63) // any of FS or VS or XS dirty 166 /* Bits 62-34 are WPRI */ 167#define SR_UXL __BITS(33, 32) // U-mode XLEN 168#define SR_UXL_32 1 // XLEN == 32 169#define SR_UXL_64 2 // XLEN == 64 170#define SR_UXL_128 3 // XLEN == 128 171 /* Bits 31-20 are WPRI*/ 172#else 173#define SR_WPRI __BITS(30, 20) | \ 174 __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ 175 __BIT(0) 176#define SR_SD __BIT(31) // any of FS or VS or XS dirty 177 /* Bits 30-20 are WPRI*/ 178#endif /* _LP64 */ 179 180/* Both RV32 and RV64 have the bottom 20 bits shared */ 181#define SR_MXR __BIT(19) // Make eXecutable Readable 182#define SR_SUM __BIT(18) // permit Supervisor User Memory access 183 /* Bit 17 is WPRI */ 184#define SR_XS __BITS(16, 15) // Vector extension state 185#define SR_XS_OFF 0 // All off 186#define SR_XS_SOME_ON 1 // None dirty or clean, some on 187#define SR_XS_SOME_CLEAN 2 // None dirty, some clean 188#define SR_XS_SOME_DIRTY 3 // Some dirty 189#define SR_FS __BITS(14, 13) // Floating-point unit state 190#define SR_FS_OFF 0 // Off 191#define SR_FS_INITIAL 1 // Initial 192#define SR_FS_CLEAN 2 // Clean 193#define SR_FS_DIRTY 3 // Dirty 194 /* Bits 12-11 are WPRI */ 195#define SR_VS __BITS(10, 9) // User-mode extension state 196#define SR_VS_OFF SR_FS_OFF // Off 197#define SR_VS_INITIAL SR_FS_INITIAL // Initial 198#define SR_VS_CLEAN SR_FS_CLEAN // Clean 199#define SR_VS_DIRTY SR_FS_DIRTY // Dirty 200#define SR_SPP __BIT(8) // Priv level before supervisor mode 201 /* Bit 7 is WPRI */ 202#define SR_UBE __BIT(6) // User-mode endianness 203#define SR_SPIE __BIT(5) // S-Mode interrupts enabled before trap 204 /* Bits 4-2 are WPRI */ 205#define SR_SIE __BIT(1) // Supervisor mode interrupt enable 206 /* Bit 0 is WPRI */ 207 208/* Supervisor interrupt registers */ 209/* ... interrupt pending register (sip) */ 210RISCVREG_READ_SET_CLEAR_INLINE(sip) // supervisor interrupt pending 211 /* Bit (XLEN-1) - 10 is WIRI */ 212#define SIP_SEIP __BIT(9) // S-mode interrupt pending 213 /* Bit 8-6 is WIRI */ 214#define SIP_STIP __BIT(5) // S-mode timer interrupt pending 215 /* Bit 4-2 is WIRI */ 216#define SIP_SSIP __BIT(1) // S-mode software interrupt pending 217 /* Bit 0 is WIRI */ 218 219/* ... interrupt-enable register (sie) */ 220RISCVREG_READ_SET_CLEAR_INLINE(sie) // supervisor interrupt enable 221 /* Bit (XLEN-1) - 10 is WIRI */ 222#define SIE_SEIE __BIT(9) // S-mode interrupt enable 223 /* Bit 8-6 is WIRI */ 224#define SIE_STIE __BIT(5) // S-mode timer interrupt enable 225 /* Bit 4-2 is WIRI */ 226#define SIE_SSIE __BIT(1) // S-mode software interrupt enable 227 /* Bit 0 is WIRI */ 228 229// U-mode sstatus values 230#ifdef _LP64 231#define SR_USER64 (SR_SPIE | __SHIFTIN(SR_UXL_64, SR_UXL)) 232#define SR_USER32 (SR_SPIE | __SHIFTIN(SR_UXL_32, SR_UXL)) 233#else 234#define SR_USER (SR_SPIE) 235#endif 236 237// Cause register 238#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN - 1)) 239#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN - 2, 0)) 240 241// Cause register - exceptions 242#define CAUSE_FETCH_MISALIGNED 0 243#define CAUSE_FETCH_ACCESS 1 244#define CAUSE_ILLEGAL_INSTRUCTION 2 245#define CAUSE_BREAKPOINT 3 246#define CAUSE_LOAD_MISALIGNED 4 247#define CAUSE_LOAD_ACCESS 5 248#define CAUSE_STORE_MISALIGNED 6 249#define CAUSE_STORE_ACCESS 7 250#define CAUSE_USER_ECALL 8 251#define CAUSE_SYSCALL CAUSE_USER_ECALL /* convenience alias */ 252#define CAUSE_SUPERVISOR_ECALL 9 253/* 10 is reserved */ 254#define CAUSE_MACHINE_ECALL 11 255#define CAUSE_FETCH_PAGE_FAULT 12 256#define CAUSE_LOAD_PAGE_FAULT 13 257/* 14 is Reserved */ 258#define CAUSE_STORE_PAGE_FAULT 15 259/* >= 16 is reserved/custom */ 260 261// Cause register - interrupts 262#define IRQ_SUPERVISOR_SOFTWARE 1 263#define IRQ_VIRTUAL_SUPERVISOR_SOFTWARE 2 264#define IRQ_MACHINE_SOFTWARE 3 265#define IRQ_SUPERVISOR_TIMER 5 266#define IRQ_VIRTUAL_SUPERVISOR_TIMER 6 267#define IRQ_MACHINE_TIMER 7 268#define IRQ_SUPERVISOR_EXTERNAL 9 269#define IRQ_VIRTUAL_SUPERVISOR_EXTERNAL 10 270#define IRQ_MACHINE_EXTERNAL 11 271#define IRQ_SUPERVISOR_GUEST_EXTERNAL 12 272#define IRQ_NSOURCES 16 273 274RISCVREG_READ_INLINE(time) 275#ifdef _LP64 276RISCVREG_READ_INLINE(cycle) 277#else /* !_LP64 */ 278static inline uint64_t 279csr_cycle_read(void) 280{ 281 uint32_t __hi0, __hi1, __lo0; 282 do { 283 asm volatile( 284 "csrr\t%[__hi0], cycleh" 285 "\n\t" "csrr\t%[__lo0], cycle" 286 "\n\t" "csrr\t%[__hi1], cycleh" 287 : [__hi0] "=r"(__hi0), 288 [__lo0] "=r"(__lo0), 289 [__hi1] "=r"(__hi1)); 290 } while (__hi0 != __hi1); 291 return 292 __SHIFTIN(__hi0, __BITS(63, 32)) | 293 __SHIFTIN(__lo0, __BITS(31, 0)); 294} 295#endif /* !_LP64 */ 296 297#ifdef _LP64 298#define SATP_MODE __BITS(63, 60) // Translation mode 299#define SATP_MODE_BARE 0 // No translation or protection 300 /* modes 1-7 reserved for standard use */ 301#define SATP_MODE_SV39 8 // Page-based 39-bit virt addr 302#define SATP_MODE_SV48 9 // Page-based 48-bit virt addr 303#define SATP_MODE_SV57 10 // Page-based 57-bit virt addr 304#define SATP_MODE_SV64 11 // Page-based 64-bit virt addr 305 /* modes 12-13 reserved for standard use */ 306 /* modes 14-15 designated for custom use */ 307#define SATP_ASID __BITS(59, 44) // Address Space Identifier 308#define SATP_PPN __BITS(43, 0) // Physical Page Number 309#else 310#define SATP_MODE __BIT(31) // Translation mode 311#define SATP_MODE_BARE 0 // No translation or protection 312#define SATP_MODE_SV32 1 // Page-based 32-bit virt addr 313#define SATP_ASID __BITS(30, 22) // Address Space Identifier 314#define SATP_PPN __BITS(21, 0) // Physical Page Number 315#endif 316 317RISCVREG_READ_WRITE_INLINE(satp) 318 319/* Fake "ASID" CSR (a field of SATP register) functions */ 320static inline uint32_t 321csr_asid_read(void) 322{ 323 uintptr_t satp = csr_satp_read(); 324 return __SHIFTOUT(satp, SATP_ASID); 325} 326 327static inline void 328csr_asid_write(uint32_t asid) 329{ 330 uintptr_t satp = csr_satp_read(); 331 satp &= ~SATP_ASID; 332 satp |= __SHIFTIN(asid, SATP_ASID); 333 csr_satp_write(satp); 334} 335 336#endif /* _RISCV_SYSREG_H_ */ 337