pci_machdep_common.c revision 1.21
1/* $NetBSD: pci_machdep_common.c,v 1.21 2016/10/19 00:08:42 nonaka Exp $ */
2
3/*-
4 * Copyright (c) 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tim Rightnour
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Generic PowerPC functions for dealing with a PCI bridge.  For most cases,
34 * these functions will work just fine, however, some machines may need
35 * specialized code, so those ports are free to write thier own functions
36 * and call those instead where appropriate.
37 */
38
39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: pci_machdep_common.c,v 1.21 2016/10/19 00:08:42 nonaka Exp $");
41
42#define _POWERPC_BUS_DMA_PRIVATE
43
44#include <sys/param.h>
45#include <sys/bus.h>
46#include <sys/device.h>
47#include <sys/errno.h>
48#include <sys/extent.h>
49#include <sys/intr.h>
50#include <sys/kmem.h>
51#include <sys/systm.h>
52#include <sys/time.h>
53
54#include <uvm/uvm_extern.h>
55
56#include <dev/pci/pcivar.h>
57#include <dev/pci/pcireg.h>
58#include <dev/pci/pcidevs.h>
59#include <dev/pci/pciconf.h>
60#include <dev/pci/pciidereg.h>
61
62/*
63 * PCI doesn't have any special needs; just use the generic versions
64 * of these functions.
65 */
66struct powerpc_bus_dma_tag pci_bus_dma_tag = {
67	._dmamap_create = _bus_dmamap_create,
68	._dmamap_destroy = _bus_dmamap_destroy,
69	._dmamap_load = _bus_dmamap_load,
70	._dmamap_load_mbuf = _bus_dmamap_load_mbuf,
71	._dmamap_load_uio = _bus_dmamap_load_uio,
72	._dmamap_load_raw = _bus_dmamap_load_raw,
73	._dmamap_unload = _bus_dmamap_unload,
74
75	._dmamem_alloc = _bus_dmamem_alloc,
76	._dmamem_free = _bus_dmamem_free,
77	._dmamem_map = _bus_dmamem_map,
78	._dmamem_unmap = _bus_dmamem_unmap,
79	._dmamem_mmap = _bus_dmamem_mmap,
80};
81
82int
83genppc_pci_bus_maxdevs(void *v, int busno)
84{
85	return 32;
86}
87
88const char *
89genppc_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
90{
91#ifdef ICU_LEN
92	if (ih == 0 || ih >= ICU_LEN
93/* XXX on macppc it's completely legal to have PCI interrupts on a slave PIC */
94#ifdef IRQ_SLAVE
95	    || ih == IRQ_SLAVE
96#endif
97	    )
98		panic("pci_intr_string: bogus handle 0x%x", ih);
99#endif
100
101	snprintf(buf, len, "irq %d", ih);
102	return buf;
103
104}
105
106const struct evcnt *
107genppc_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
108{
109
110	/* XXX for now, no evcnt parent reported */
111	return NULL;
112}
113
114void *
115genppc_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
116    int (*func)(void *), void *arg, const char *xname)
117{
118
119#ifdef ICU_LEN
120	if (ih == 0 || ih >= ICU_LEN
121#ifdef IRQ_SLAVE
122	    || ih == IRQ_SLAVE
123#endif
124	    )
125		panic("pci_intr_establish: bogus handle 0x%x", ih);
126#endif
127
128	return intr_establish_xname(ih, IST_LEVEL, level, func, arg, xname);
129}
130
131void
132genppc_pci_intr_disestablish(void *v, void *cookie)
133{
134
135	intr_disestablish(cookie);
136}
137
138int
139genppc_pci_intr_setattr(void *v, pci_intr_handle_t *ihp, int attr,
140    uint64_t data)
141{
142
143	return ENODEV;
144}
145
146pci_intr_type_t
147genppc_pci_intr_type(void *v, pci_intr_handle_t ih)
148{
149
150	return PCI_INTR_TYPE_INTX;
151}
152
153int
154genppc_pci_intr_alloc(const struct pci_attach_args *pa,
155    pci_intr_handle_t **ihps, int *counts, pci_intr_type_t max_type)
156{
157	pci_intr_handle_t *ihp;
158
159	if (counts != NULL && counts[PCI_INTR_TYPE_INTX] == 0)
160		return EINVAL;
161
162	ihp = kmem_alloc(sizeof(*ihp), KM_SLEEP);
163	if (ihp == NULL)
164		return ENOMEM;
165
166	if (pci_intr_map(pa, ihp)) {
167		kmem_free(ihp, sizeof(*ihp));
168		return EINVAL;
169	}
170
171	*ihps = ihp;
172	return 0;
173}
174
175void
176genppc_pci_intr_release(void *v, pci_intr_handle_t *pih, int count)
177{
178
179	if (pih == NULL)
180		return;
181
182	KASSERT(count == 1);
183	kmem_free(pih, sizeof(*pih));
184}
185
186int
187genppc_pci_intx_alloc(const struct pci_attach_args *pa,
188    pci_intr_handle_t **ihps)
189{
190	pci_intr_handle_t *handle;
191	int error;
192
193	handle = kmem_zalloc(sizeof(*handle), KM_SLEEP);
194	if (handle == NULL)
195		return ENOMEM;
196
197	error = pci_intr_map(pa, handle);
198	if (error != 0) {
199		kmem_free(handle, sizeof(*handle));
200		return error;
201	}
202
203	*ihps = handle;
204	return 0;
205}
206
207void
208genppc_pci_conf_interrupt(void *v, int bus, int dev, int pin,
209    int swiz, int *iline)
210{
211	/* do nothing */
212}
213
214int
215genppc_pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
216{
217	return (PCI_CONF_DEFAULT);
218}
219
220int
221genppc_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
222{
223	int pin = pa->pa_intrpin;
224	int line = pa->pa_intrline;
225
226#ifdef DEBUG
227	printf("%s: pin: %d, line: %d\n", __func__, pin, line);
228#endif
229
230	if (pin == 0) {
231		/* No IRQ used. */
232		aprint_error("pci_intr_map: interrupt pin %d\n", pin);
233		goto bad;
234	}
235
236	if (pin > 4) {
237		aprint_error("pci_intr_map: bad interrupt pin %d\n", pin);
238		goto bad;
239	}
240
241	/*
242	 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
243	 * `unknown' or `no connection' on a PC.  We assume that a device with
244	 * `no connection' either doesn't have an interrupt (in which case the
245	 * pin number should be 0, and would have been noticed above), or
246	 * wasn't configured by the BIOS (in which case we punt, since there's
247	 * no real way we can know how the interrupt lines are mapped in the
248	 * hardware).
249	 *
250	 * XXX
251	 * Since IRQ 0 is only used by the clock, and we can't actually be sure
252	 * that the BIOS did its job, we also recognize that as meaning that
253	 * the BIOS has not configured the device.
254	 */
255	if (line == 0 || line == 255) {
256		aprint_error("pci_intr_map: no mapping for pin %c\n", '@' + pin);
257		goto bad;
258#ifdef ICU_LEN
259	} else {
260		if (line >= ICU_LEN) {
261			aprint_error("pci_intr_map: bad interrupt line %d\n", line);
262			goto bad;
263		}
264#endif
265	}
266
267	*ihp = line;
268	return 0;
269
270bad:
271	*ihp = -1;
272	return 1;
273}
274
275/* experimental MSI support */
276int
277genppc_pci_msi_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
278    int *count, bool exact)
279{
280
281	return EOPNOTSUPP;
282}
283
284/* experimental MSI-X support */
285int
286genppc_pci_msix_alloc(const struct pci_attach_args *pa,
287    pci_intr_handle_t **ihps, u_int *table_indexes, int *count, bool exact)
288{
289
290	return EOPNOTSUPP;
291}
292
293void
294genppc_pci_chipset_msi_init(pci_chipset_tag_t pc)
295{
296	pc->pc_msi_alloc = genppc_pci_msi_alloc;
297}
298
299void
300genppc_pci_chipset_msix_init(pci_chipset_tag_t pc)
301{
302	pc->pc_msix_alloc = genppc_pci_msix_alloc;
303}
304
305#ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
306#include <machine/isa_machdep.h>
307#include "isa.h"
308
309void *genppc_pciide_machdep_compat_intr_establish(device_t,
310    struct pci_attach_args *, int, int (*)(void *), void *);
311
312void *
313genppc_pciide_machdep_compat_intr_establish(device_t dev,
314    struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
315{
316#if NISA > 0
317	int irq;
318	void *cookie;
319
320	irq = PCIIDE_COMPAT_IRQ(chan);
321	cookie = isa_intr_establish(NULL, irq, IST_LEVEL, IPL_BIO, func, arg);
322	if (cookie == NULL)
323		return (NULL);
324	aprint_normal_dev(dev, "%s channel interrupting at irq %d\n",
325	    PCIIDE_CHANNEL_NAME(chan), irq);
326	return (cookie);
327#else
328	panic("pciide_machdep_compat_intr_establish() called");
329#endif
330}
331#endif /* __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH */
332