if_emac.c revision 1.45
1/* $NetBSD: if_emac.c,v 1.45 2016/06/10 13:27:12 ozaki-r Exp $ */ 2 3/* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * emac(4) supports following ibm4xx's EMACs. 40 * XXXX: ZMII and 'TCP Accelaration Hardware' not support yet... 41 * 42 * tested 43 * ------ 44 * 405EP - 10/100 x2 45 * 405EX/EXr o 10/100/1000 x2 (EXr x1), STA v2, 256bit hash-Table, RGMII 46 * 405GP/GPr o 10/100 47 * 440EP - 10/100 x2, ZMII 48 * 440GP - 10/100 x2, ZMII 49 * 440GX - 10/100/1000 x4, ZMII/RGMII(ch 2, 3), TAH(ch 2, 3) 50 * 440SP - 10/100/1000 51 * 440SPe - 10/100/1000, STA v2 52 */ 53 54#include <sys/cdefs.h> 55__KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.45 2016/06/10 13:27:12 ozaki-r Exp $"); 56 57#include "opt_emac.h" 58 59#include <sys/param.h> 60#include <sys/systm.h> 61#include <sys/mbuf.h> 62#include <sys/kernel.h> 63#include <sys/socket.h> 64#include <sys/ioctl.h> 65#include <sys/cpu.h> 66#include <sys/device.h> 67 68#include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70#include <net/if.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73#include <net/if_ether.h> 74 75#include <net/bpf.h> 76 77#include <powerpc/ibm4xx/cpu.h> 78#include <powerpc/ibm4xx/dcr4xx.h> 79#include <powerpc/ibm4xx/mal405gp.h> 80#include <powerpc/ibm4xx/dev/emacreg.h> 81#include <powerpc/ibm4xx/dev/if_emacreg.h> 82#include <powerpc/ibm4xx/dev/if_emacvar.h> 83#include <powerpc/ibm4xx/dev/malvar.h> 84#include <powerpc/ibm4xx/dev/opbreg.h> 85#include <powerpc/ibm4xx/dev/opbvar.h> 86#include <powerpc/ibm4xx/dev/plbvar.h> 87#if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 88#include <powerpc/ibm4xx/dev/rmiivar.h> 89#endif 90 91#include <dev/mii/miivar.h> 92 93#include "locators.h" 94 95 96/* 97 * Transmit descriptor list size. There are two Tx channels, each with 98 * up to 256 hardware descriptors available. We currently use one Tx 99 * channel. We tell the upper layers that they can queue a lot of 100 * packets, and we go ahead and manage up to 64 of them at a time. We 101 * allow up to 16 DMA segments per packet. 102 */ 103#define EMAC_NTXSEGS 16 104#define EMAC_TXQUEUELEN 64 105#define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 106#define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 107#define EMAC_NTXDESC 256 108#define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 109#define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 110#define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 111 112/* 113 * Receive descriptor list size. There is one Rx channel with up to 256 114 * hardware descriptors available. We allocate 64 receive descriptors, 115 * each with a 2k buffer (MCLBYTES). 116 */ 117#define EMAC_NRXDESC 64 118#define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 119#define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 120#define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 121 122/* 123 * Transmit/receive descriptors that are DMA'd to the EMAC. 124 */ 125struct emac_control_data { 126 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 127 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 128}; 129 130#define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 131#define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 132#define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 133 134/* 135 * Software state for transmit jobs. 136 */ 137struct emac_txsoft { 138 struct mbuf *txs_mbuf; /* head of mbuf chain */ 139 bus_dmamap_t txs_dmamap; /* our DMA map */ 140 int txs_firstdesc; /* first descriptor in packet */ 141 int txs_lastdesc; /* last descriptor in packet */ 142 int txs_ndesc; /* # of descriptors used */ 143}; 144 145/* 146 * Software state for receive descriptors. 147 */ 148struct emac_rxsoft { 149 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 150 bus_dmamap_t rxs_dmamap; /* our DMA map */ 151}; 152 153/* 154 * Software state per device. 155 */ 156struct emac_softc { 157 device_t sc_dev; /* generic device information */ 158 int sc_instance; /* instance no. */ 159 bus_space_tag_t sc_st; /* bus space tag */ 160 bus_space_handle_t sc_sh; /* bus space handle */ 161 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 162 struct ethercom sc_ethercom; /* ethernet common data */ 163 void *sc_sdhook; /* shutdown hook */ 164 void *sc_powerhook; /* power management hook */ 165 166 struct mii_data sc_mii; /* MII/media information */ 167 struct callout sc_callout; /* tick callout */ 168 169 uint32_t sc_mr1; /* copy of Mode Register 1 */ 170 uint32_t sc_stacr_read; /* Read opcode of STAOPC of STACR */ 171 uint32_t sc_stacr_write; /* Write opcode of STAOPC of STACR */ 172 uint32_t sc_stacr_bits; /* misc bits of STACR */ 173 bool sc_stacr_completed; /* Operation completed of STACR */ 174 int sc_htsize; /* Hash Table size */ 175 176 bus_dmamap_t sc_cddmamap; /* control data dma map */ 177#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 178 179 /* Software state for transmit/receive descriptors. */ 180 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 181 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 182 183 /* Control data structures. */ 184 struct emac_control_data *sc_control_data; 185#define sc_txdescs sc_control_data->ecd_txdesc 186#define sc_rxdescs sc_control_data->ecd_rxdesc 187 188#ifdef EMAC_EVENT_COUNTERS 189 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 190 struct evcnt sc_ev_txintr; /* Tx interrupts */ 191 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 192 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 193 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 194 195 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 196 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 197 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 198 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 199 struct evcnt sc_ev_tu; /* Tx underrun */ 200#endif /* EMAC_EVENT_COUNTERS */ 201 202 int sc_txfree; /* number of free Tx descriptors */ 203 int sc_txnext; /* next ready Tx descriptor */ 204 205 int sc_txsfree; /* number of free Tx jobs */ 206 int sc_txsnext; /* next ready Tx job */ 207 int sc_txsdirty; /* dirty Tx jobs */ 208 209 int sc_rxptr; /* next ready RX descriptor/descsoft */ 210 211 void (*sc_rmii_enable)(device_t, int); /* reduced MII enable */ 212 void (*sc_rmii_disable)(device_t, int); /* reduced MII disable*/ 213 void (*sc_rmii_speed)(device_t, int, int); /* reduced MII speed */ 214}; 215 216#ifdef EMAC_EVENT_COUNTERS 217#define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 218#else 219#define EMAC_EVCNT_INCR(ev) /* nothing */ 220#endif 221 222#define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 223#define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 224 225#define EMAC_CDTXSYNC(sc, x, n, ops) \ 226do { \ 227 int __x, __n; \ 228 \ 229 __x = (x); \ 230 __n = (n); \ 231 \ 232 /* If it will wrap around, sync to the end of the ring. */ \ 233 if ((__x + __n) > EMAC_NTXDESC) { \ 234 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 235 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 236 (EMAC_NTXDESC - __x), (ops)); \ 237 __n -= (EMAC_NTXDESC - __x); \ 238 __x = 0; \ 239 } \ 240 \ 241 /* Now sync whatever is left. */ \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 243 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 244} while (/*CONSTCOND*/0) 245 246#define EMAC_CDRXSYNC(sc, x, ops) \ 247do { \ 248 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 249 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 250} while (/*CONSTCOND*/0) 251 252#define EMAC_INIT_RXDESC(sc, x) \ 253do { \ 254 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 255 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 256 struct mbuf *__m = __rxs->rxs_mbuf; \ 257 \ 258 /* \ 259 * Note: We scoot the packet forward 2 bytes in the buffer \ 260 * so that the payload after the Ethernet header is aligned \ 261 * to a 4-byte boundary. \ 262 */ \ 263 __m->m_data = __m->m_ext.ext_buf + 2; \ 264 \ 265 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 266 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 267 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 268 /* Set wrap on last descriptor. */ \ 269 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 270 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 271} while (/*CONSTCOND*/0) 272 273#define EMAC_WRITE(sc, reg, val) \ 274 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 275#define EMAC_READ(sc, reg) \ 276 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 277 278#define EMAC_SET_FILTER(aht, crc) \ 279do { \ 280 (aht)[3 - (((crc) >> 26) >> 4)] |= 1 << (((crc) >> 26) & 0xf); \ 281} while (/*CONSTCOND*/0) 282#define EMAC_SET_FILTER256(aht, crc) \ 283do { \ 284 (aht)[7 - (((crc) >> 24) >> 5)] |= 1 << (((crc) >> 24) & 0x1f); \ 285} while (/*CONSTCOND*/0) 286 287static int emac_match(device_t, cfdata_t, void *); 288static void emac_attach(device_t, device_t, void *); 289 290static int emac_intr(void *); 291static void emac_shutdown(void *); 292 293static void emac_start(struct ifnet *); 294static int emac_ioctl(struct ifnet *, u_long, void *); 295static int emac_init(struct ifnet *); 296static void emac_stop(struct ifnet *, int); 297static void emac_watchdog(struct ifnet *); 298 299static int emac_add_rxbuf(struct emac_softc *, int); 300static void emac_rxdrain(struct emac_softc *); 301static int emac_set_filter(struct emac_softc *); 302static int emac_txreap(struct emac_softc *); 303 304static void emac_soft_reset(struct emac_softc *); 305static void emac_smart_reset(struct emac_softc *); 306 307static int emac_mii_readreg(device_t, int, int); 308static void emac_mii_writereg(device_t, int, int, int); 309static void emac_mii_statchg(struct ifnet *); 310static uint32_t emac_mii_wait(struct emac_softc *); 311static void emac_mii_tick(void *); 312 313int emac_copy_small = 0; 314 315CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc), 316 emac_match, emac_attach, NULL, NULL); 317 318 319static int 320emac_match(device_t parent, cfdata_t cf, void *aux) 321{ 322 struct opb_attach_args *oaa = aux; 323 324 /* match only on-chip ethernet devices */ 325 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 326 return 1; 327 328 return 0; 329} 330 331static void 332emac_attach(device_t parent, device_t self, void *aux) 333{ 334 struct opb_attach_args *oaa = aux; 335 struct emac_softc *sc = device_private(self); 336 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 337 struct mii_data *mii = &sc->sc_mii; 338 const char * xname = device_xname(self); 339 bus_dma_segment_t seg; 340 int error, i, nseg, opb_freq, opbc, mii_phy = MII_PHY_ANY; 341 const uint8_t *enaddr; 342 prop_dictionary_t dict = device_properties(self); 343 prop_data_t ea; 344 345 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 346 347 sc->sc_dev = self; 348 sc->sc_instance = oaa->opb_instance; 349 sc->sc_st = oaa->opb_bt; 350 sc->sc_dmat = oaa->opb_dmat; 351 352 callout_init(&sc->sc_callout, 0); 353 354 aprint_naive("\n"); 355 aprint_normal(": Ethernet Media Access Controller\n"); 356 357 /* Fetch the Ethernet address. */ 358 ea = prop_dictionary_get(dict, "mac-address"); 359 if (ea == NULL) { 360 aprint_error_dev(self, "unable to get mac-address property\n"); 361 return; 362 } 363 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 364 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 365 enaddr = prop_data_data_nocopy(ea); 366 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 367 368#if defined(EMAC_ZMII_PHY) || defined(EMAC_RGMII_PHY) 369 /* Fetch the MII offset. */ 370 prop_dictionary_get_uint32(dict, "mii-phy", &mii_phy); 371 372#ifdef EMAC_ZMII_PHY 373 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_ZMII) 374 zmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 375 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 376#endif 377#ifdef EMAC_RGMII_PHY 378 if (oaa->opb_flags & OPB_FLAGS_EMAC_RMII_RGMII) 379 rgmii_attach(parent, sc->sc_instance, &sc->sc_rmii_enable, 380 &sc->sc_rmii_disable, &sc->sc_rmii_speed); 381#endif 382#endif 383 384 /* 385 * Allocate the control data structures, and create and load the 386 * DMA map for it. 387 */ 388 if ((error = bus_dmamem_alloc(sc->sc_dmat, 389 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 390 aprint_error_dev(self, 391 "unable to allocate control data, error = %d\n", error); 392 goto fail_0; 393 } 394 395 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 396 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 397 BUS_DMA_COHERENT)) != 0) { 398 aprint_error_dev(self, 399 "unable to map control data, error = %d\n", error); 400 goto fail_1; 401 } 402 403 if ((error = bus_dmamap_create(sc->sc_dmat, 404 sizeof(struct emac_control_data), 1, 405 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 406 aprint_error_dev(self, 407 "unable to create control data DMA map, error = %d\n", 408 error); 409 goto fail_2; 410 } 411 412 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 413 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 414 0)) != 0) { 415 aprint_error_dev(self, 416 "unable to load control data DMA map, error = %d\n", error); 417 goto fail_3; 418 } 419 420 /* 421 * Create the transmit buffer DMA maps. 422 */ 423 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 424 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 425 EMAC_NTXSEGS, MCLBYTES, 0, 0, 426 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 427 aprint_error_dev(self, 428 "unable to create tx DMA map %d, error = %d\n", 429 i, error); 430 goto fail_4; 431 } 432 } 433 434 /* 435 * Create the receive buffer DMA maps. 436 */ 437 for (i = 0; i < EMAC_NRXDESC; i++) { 438 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 439 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 440 aprint_error_dev(self, 441 "unable to create rx DMA map %d, error = %d\n", 442 i, error); 443 goto fail_5; 444 } 445 sc->sc_rxsoft[i].rxs_mbuf = NULL; 446 } 447 448 /* Soft Reset the EMAC. The chip to a known state. */ 449 emac_soft_reset(sc); 450 451 opb_freq = opb_get_frequency(); 452 switch (opb_freq) { 453 case 50000000: opbc = STACR_OPBC_50MHZ; break; 454 case 66666666: opbc = STACR_OPBC_66MHZ; break; 455 case 83333333: opbc = STACR_OPBC_83MHZ; break; 456 case 100000000: opbc = STACR_OPBC_100MHZ; break; 457 458 default: 459 if (opb_freq > 100000000) { 460 opbc = STACR_OPBC_A100MHZ; 461 break; 462 } 463 aprint_error_dev(self, "unsupport OPB frequency %dMHz\n", 464 opb_freq / 1000 / 1000); 465 goto fail_5; 466 } 467 if (oaa->opb_flags & OPB_FLAGS_EMAC_GBE) { 468 sc->sc_mr1 = 469 MR1_RFS_GBE(MR1__FS_16KB) | 470 MR1_TFS_GBE(MR1__FS_16KB) | 471 MR1_TR0_MULTIPLE | 472 MR1_OBCI(opbc); 473 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 474 475 if (oaa->opb_flags & OPB_FLAGS_EMAC_STACV2) { 476 sc->sc_stacr_read = STACR_STAOPC_READ; 477 sc->sc_stacr_write = STACR_STAOPC_WRITE; 478 sc->sc_stacr_bits = STACR_OC; 479 sc->sc_stacr_completed = false; 480 } else { 481 sc->sc_stacr_read = STACR_READ; 482 sc->sc_stacr_write = STACR_WRITE; 483 sc->sc_stacr_completed = true; 484 } 485 } else { 486 /* 487 * Set up Mode Register 1 - set receive and transmit FIFOs to 488 * maximum size, allow transmit of multiple packets (only 489 * channel 0 is used). 490 * 491 * XXX: Allow pause packets?? 492 */ 493 sc->sc_mr1 = 494 MR1_RFS(MR1__FS_4KB) | 495 MR1_TFS(MR1__FS_2KB) | 496 MR1_TR0_MULTIPLE; 497 498 sc->sc_stacr_read = STACR_READ; 499 sc->sc_stacr_write = STACR_WRITE; 500 sc->sc_stacr_bits = STACR_OPBC(opbc); 501 sc->sc_stacr_completed = true; 502 } 503 504 intr_establish(oaa->opb_irq, IST_LEVEL, IPL_NET, emac_intr, sc); 505 mal_intr_establish(sc->sc_instance, sc); 506 507 if (oaa->opb_flags & OPB_FLAGS_EMAC_HT256) 508 sc->sc_htsize = 256; 509 else 510 sc->sc_htsize = 64; 511 512 /* Clear all interrupts */ 513 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL); 514 515 /* 516 * Initialise the media structures. 517 */ 518 mii->mii_ifp = ifp; 519 mii->mii_readreg = emac_mii_readreg; 520 mii->mii_writereg = emac_mii_writereg; 521 mii->mii_statchg = emac_mii_statchg; 522 523 sc->sc_ethercom.ec_mii = mii; 524 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 525 mii_attach(self, mii, 0xffffffff, mii_phy, MII_OFFSET_ANY, 526 MIIF_DOPAUSE); 527 if (LIST_FIRST(&mii->mii_phys) == NULL) { 528 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 529 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 530 } else 531 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 532 533 ifp = &sc->sc_ethercom.ec_if; 534 strcpy(ifp->if_xname, xname); 535 ifp->if_softc = sc; 536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 ifp->if_start = emac_start; 538 ifp->if_ioctl = emac_ioctl; 539 ifp->if_init = emac_init; 540 ifp->if_stop = emac_stop; 541 ifp->if_watchdog = emac_watchdog; 542 IFQ_SET_READY(&ifp->if_snd); 543 544 /* 545 * We can support 802.1Q VLAN-sized frames. 546 */ 547 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 548 549 /* 550 * Attach the interface. 551 */ 552 if_attach(ifp); 553 ether_ifattach(ifp, enaddr); 554 555#ifdef EMAC_EVENT_COUNTERS 556 /* 557 * Attach the event counters. 558 */ 559 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 560 NULL, xname, "txintr"); 561 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 562 NULL, xname, "rxintr"); 563 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 564 NULL, xname, "txde"); 565 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 566 NULL, xname, "rxde"); 567 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 568 NULL, xname, "intr"); 569 570 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 571 NULL, xname, "txreap"); 572 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 573 NULL, xname, "txsstall"); 574 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 575 NULL, xname, "txdstall"); 576 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 577 NULL, xname, "txdrop"); 578 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 579 NULL, xname, "tu"); 580#endif /* EMAC_EVENT_COUNTERS */ 581 582 /* 583 * Make sure the interface is shutdown during reboot. 584 */ 585 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 586 if (sc->sc_sdhook == NULL) 587 aprint_error_dev(self, 588 "WARNING: unable to establish shutdown hook\n"); 589 590 return; 591 592 /* 593 * Free any resources we've allocated during the failed attach 594 * attempt. Do this in reverse order and fall through. 595 */ 596fail_5: 597 for (i = 0; i < EMAC_NRXDESC; i++) { 598 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 599 bus_dmamap_destroy(sc->sc_dmat, 600 sc->sc_rxsoft[i].rxs_dmamap); 601 } 602fail_4: 603 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 604 if (sc->sc_txsoft[i].txs_dmamap != NULL) 605 bus_dmamap_destroy(sc->sc_dmat, 606 sc->sc_txsoft[i].txs_dmamap); 607 } 608 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 609fail_3: 610 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 611fail_2: 612 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 613 sizeof(struct emac_control_data)); 614fail_1: 615 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 616fail_0: 617 return; 618} 619 620/* 621 * EMAC General interrupt handler 622 */ 623static int 624emac_intr(void *arg) 625{ 626 struct emac_softc *sc = arg; 627 uint32_t status; 628 629 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 630 status = EMAC_READ(sc, EMAC_ISR); 631 632 /* Clear the interrupt status bits. */ 633 EMAC_WRITE(sc, EMAC_ISR, status); 634 635 return 1; 636} 637 638static void 639emac_shutdown(void *arg) 640{ 641 struct emac_softc *sc = arg; 642 643 emac_stop(&sc->sc_ethercom.ec_if, 0); 644} 645 646 647/* 648 * ifnet interface functions 649 */ 650 651static void 652emac_start(struct ifnet *ifp) 653{ 654 struct emac_softc *sc = ifp->if_softc; 655 struct mbuf *m0; 656 struct emac_txsoft *txs; 657 bus_dmamap_t dmamap; 658 int error, firsttx, nexttx, lasttx, ofree, seg; 659 660 lasttx = 0; /* XXX gcc */ 661 662 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 663 return; 664 665 /* 666 * Remember the previous number of free descriptors. 667 */ 668 ofree = sc->sc_txfree; 669 670 /* 671 * Loop through the send queue, setting up transmit descriptors 672 * until we drain the queue, or use up all available transmit 673 * descriptors. 674 */ 675 for (;;) { 676 /* Grab a packet off the queue. */ 677 IFQ_POLL(&ifp->if_snd, m0); 678 if (m0 == NULL) 679 break; 680 681 /* 682 * Get a work queue entry. Reclaim used Tx descriptors if 683 * we are running low. 684 */ 685 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 686 emac_txreap(sc); 687 if (sc->sc_txsfree == 0) { 688 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 689 break; 690 } 691 } 692 693 txs = &sc->sc_txsoft[sc->sc_txsnext]; 694 dmamap = txs->txs_dmamap; 695 696 /* 697 * Load the DMA map. If this fails, the packet either 698 * didn't fit in the alloted number of segments, or we 699 * were short on resources. In this case, we'll copy 700 * and try again. 701 */ 702 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 703 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 704 if (error) { 705 if (error == EFBIG) { 706 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 707 aprint_error_ifnet(ifp, 708 "Tx packet consumes too many " 709 "DMA segments, dropping...\n"); 710 IFQ_DEQUEUE(&ifp->if_snd, m0); 711 m_freem(m0); 712 continue; 713 } 714 /* Short on resources, just stop for now. */ 715 break; 716 } 717 718 /* 719 * Ensure we have enough descriptors free to describe 720 * the packet. 721 */ 722 if (dmamap->dm_nsegs > sc->sc_txfree) { 723 /* 724 * Not enough free descriptors to transmit this 725 * packet. We haven't committed anything yet, 726 * so just unload the DMA map, put the packet 727 * back on the queue, and punt. Notify the upper 728 * layer that there are not more slots left. 729 * 730 */ 731 ifp->if_flags |= IFF_OACTIVE; 732 bus_dmamap_unload(sc->sc_dmat, dmamap); 733 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 734 break; 735 } 736 737 IFQ_DEQUEUE(&ifp->if_snd, m0); 738 739 /* 740 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 741 */ 742 743 /* Sync the DMA map. */ 744 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 745 BUS_DMASYNC_PREWRITE); 746 747 /* 748 * Store a pointer to the packet so that we can free it 749 * later. 750 */ 751 txs->txs_mbuf = m0; 752 txs->txs_firstdesc = sc->sc_txnext; 753 txs->txs_ndesc = dmamap->dm_nsegs; 754 755 /* 756 * Initialize the transmit descriptor. 757 */ 758 firsttx = sc->sc_txnext; 759 for (nexttx = sc->sc_txnext, seg = 0; 760 seg < dmamap->dm_nsegs; 761 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 762 struct mal_descriptor *txdesc = 763 &sc->sc_txdescs[nexttx]; 764 765 /* 766 * If this is the first descriptor we're 767 * enqueueing, don't set the TX_READY bit just 768 * yet. That could cause a race condition. 769 * We'll do it below. 770 */ 771 txdesc->md_data = dmamap->dm_segs[seg].ds_addr; 772 txdesc->md_data_len = dmamap->dm_segs[seg].ds_len; 773 txdesc->md_stat_ctrl = 774 (txdesc->md_stat_ctrl & MAL_TX_WRAP) | 775 (nexttx == firsttx ? 0 : MAL_TX_READY) | 776 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 777 lasttx = nexttx; 778 } 779 780 /* Set the LAST bit on the last segment. */ 781 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 782 783 /* 784 * Set up last segment descriptor to send an interrupt after 785 * that descriptor is transmitted, and bypass existing Tx 786 * descriptor reaping method (for now...). 787 */ 788 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 789 790 791 txs->txs_lastdesc = lasttx; 792 793 /* Sync the descriptors we're using. */ 794 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 796 797 /* 798 * The entire packet chain is set up. Give the 799 * first descriptor to the chip now. 800 */ 801 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 802 EMAC_CDTXSYNC(sc, firsttx, 1, 803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 804 /* 805 * Tell the EMAC that a new packet is available. 806 */ 807 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2); 808 809 /* Advance the tx pointer. */ 810 sc->sc_txfree -= txs->txs_ndesc; 811 sc->sc_txnext = nexttx; 812 813 sc->sc_txsfree--; 814 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 815 816 /* 817 * Pass the packet to any BPF listeners. 818 */ 819 bpf_mtap(ifp, m0); 820 } 821 822 if (sc->sc_txfree == 0) 823 /* No more slots left; notify upper layer. */ 824 ifp->if_flags |= IFF_OACTIVE; 825 826 if (sc->sc_txfree != ofree) 827 /* Set a watchdog timer in case the chip flakes out. */ 828 ifp->if_timer = 5; 829} 830 831static int 832emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 833{ 834 struct emac_softc *sc = ifp->if_softc; 835 int s, error; 836 837 s = splnet(); 838 839 switch (cmd) { 840 case SIOCSIFMTU: 841 { 842 struct ifreq *ifr = (struct ifreq *)data; 843 int maxmtu; 844 845 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) 846 maxmtu = EMAC_MAX_MTU; 847 else 848 maxmtu = ETHERMTU; 849 850 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > maxmtu) 851 error = EINVAL; 852 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 853 break; 854 else if (ifp->if_flags & IFF_UP) 855 error = emac_init(ifp); 856 else 857 error = 0; 858 break; 859 } 860 861 default: 862 error = ether_ioctl(ifp, cmd, data); 863 if (error == ENETRESET) { 864 /* 865 * Multicast list has changed; set the hardware filter 866 * accordingly. 867 */ 868 if (ifp->if_flags & IFF_RUNNING) 869 error = emac_set_filter(sc); 870 else 871 error = 0; 872 } 873 } 874 875 /* try to get more packets going */ 876 emac_start(ifp); 877 878 splx(s); 879 return error; 880} 881 882static int 883emac_init(struct ifnet *ifp) 884{ 885 struct emac_softc *sc = ifp->if_softc; 886 struct emac_rxsoft *rxs; 887 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 888 int error, i; 889 890 error = 0; 891 892 /* Cancel any pending I/O. */ 893 emac_stop(ifp, 0); 894 895 /* Reset the chip to a known state. */ 896 emac_soft_reset(sc); 897 898 /* 899 * Initialise the transmit descriptor ring. 900 */ 901 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 902 /* set wrap on last descriptor */ 903 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 904 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 905 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 906 sc->sc_txfree = EMAC_NTXDESC; 907 sc->sc_txnext = 0; 908 909 /* 910 * Initialise the transmit job descriptors. 911 */ 912 for (i = 0; i < EMAC_TXQUEUELEN; i++) 913 sc->sc_txsoft[i].txs_mbuf = NULL; 914 sc->sc_txsfree = EMAC_TXQUEUELEN; 915 sc->sc_txsnext = 0; 916 sc->sc_txsdirty = 0; 917 918 /* 919 * Initialise the receiver descriptor and receive job 920 * descriptor rings. 921 */ 922 for (i = 0; i < EMAC_NRXDESC; i++) { 923 rxs = &sc->sc_rxsoft[i]; 924 if (rxs->rxs_mbuf == NULL) { 925 if ((error = emac_add_rxbuf(sc, i)) != 0) { 926 aprint_error_ifnet(ifp, 927 "unable to allocate or map rx buffer %d," 928 " error = %d\n", 929 i, error); 930 /* 931 * XXX Should attempt to run with fewer receive 932 * XXX buffers instead of just failing. 933 */ 934 emac_rxdrain(sc); 935 goto out; 936 } 937 } else 938 EMAC_INIT_RXDESC(sc, i); 939 } 940 sc->sc_rxptr = 0; 941 942 /* 943 * Set the current media. 944 */ 945 if ((error = ether_mediachange(ifp)) != 0) 946 goto out; 947 948 /* 949 * Load the MAC address. 950 */ 951 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 952 EMAC_WRITE(sc, EMAC_IALR, 953 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 954 955 /* Enable the transmit and receive channel on the MAL. */ 956 error = mal_start(sc->sc_instance, 957 EMAC_CDTXADDR(sc, 0), EMAC_CDRXADDR(sc, 0)); 958 if (error) 959 goto out; 960 961 sc->sc_mr1 &= ~MR1_JPSM; 962 if (ifp->if_mtu > ETHERMTU) 963 /* Enable Jumbo Packet Support Mode */ 964 sc->sc_mr1 |= MR1_JPSM; 965 966 /* Set fifos, media modes. */ 967 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 968 969 /* 970 * Enable Individual and (possibly) Broadcast Address modes, 971 * runt packets, and strip padding. 972 */ 973 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 | 974 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 975 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 976 977 /* 978 * Set multicast filter. 979 */ 980 emac_set_filter(sc); 981 982 /* 983 * Set low- and urgent-priority request thresholds. 984 */ 985 EMAC_WRITE(sc, EMAC_TMR1, 986 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 987 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 988 /* 989 * Set Transmit Request Threshold Register. 990 */ 991 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 992 993 /* 994 * Set high and low receive watermarks. 995 */ 996 EMAC_WRITE(sc, EMAC_RWMR, 997 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 998 999 /* 1000 * Set frame gap. 1001 */ 1002 EMAC_WRITE(sc, EMAC_IPGVR, 8); 1003 1004 /* 1005 * Set interrupt status enable bits for EMAC. 1006 */ 1007 EMAC_WRITE(sc, EMAC_ISER, 1008 ISR_TXPE | /* TX Parity Error */ 1009 ISR_RXPE | /* RX Parity Error */ 1010 ISR_TXUE | /* TX Underrun Event */ 1011 ISR_RXOE | /* RX Overrun Event */ 1012 ISR_OVR | /* Overrun Error */ 1013 ISR_PP | /* Pause Packet */ 1014 ISR_BP | /* Bad Packet */ 1015 ISR_RP | /* Runt Packet */ 1016 ISR_SE | /* Short Event */ 1017 ISR_ALE | /* Alignment Error */ 1018 ISR_BFCS | /* Bad FCS */ 1019 ISR_PTLE | /* Packet Too Long Error */ 1020 ISR_ORE | /* Out of Range Error */ 1021 ISR_IRE | /* In Range Error */ 1022 ISR_SE0 | /* Signal Quality Error 0 (SQE) */ 1023 ISR_TE0 | /* Transmit Error 0 */ 1024 ISR_MOS | /* MMA Operation Succeeded */ 1025 ISR_MOF); /* MMA Operation Failed */ 1026 1027 /* 1028 * Enable the transmit and receive channel on the EMAC. 1029 */ 1030 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1031 1032 /* 1033 * Start the one second MII clock. 1034 */ 1035 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1036 1037 /* 1038 * ... all done! 1039 */ 1040 ifp->if_flags |= IFF_RUNNING; 1041 ifp->if_flags &= ~IFF_OACTIVE; 1042 1043 out: 1044 if (error) { 1045 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1046 ifp->if_timer = 0; 1047 aprint_error_ifnet(ifp, "interface not running\n"); 1048 } 1049 return error; 1050} 1051 1052static void 1053emac_stop(struct ifnet *ifp, int disable) 1054{ 1055 struct emac_softc *sc = ifp->if_softc; 1056 struct emac_txsoft *txs; 1057 int i; 1058 1059 /* Stop the one second clock. */ 1060 callout_stop(&sc->sc_callout); 1061 1062 /* Down the MII */ 1063 mii_down(&sc->sc_mii); 1064 1065 /* Disable interrupts. */ 1066 EMAC_WRITE(sc, EMAC_ISER, 0); 1067 1068 /* Disable the receive and transmit channels. */ 1069 mal_stop(sc->sc_instance); 1070 1071 /* Disable the transmit enable and receive MACs. */ 1072 EMAC_WRITE(sc, EMAC_MR0, 1073 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 1074 1075 /* Release any queued transmit buffers. */ 1076 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 1077 txs = &sc->sc_txsoft[i]; 1078 if (txs->txs_mbuf != NULL) { 1079 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1080 m_freem(txs->txs_mbuf); 1081 txs->txs_mbuf = NULL; 1082 } 1083 } 1084 1085 if (disable) 1086 emac_rxdrain(sc); 1087 1088 /* 1089 * Mark the interface down and cancel the watchdog timer. 1090 */ 1091 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1092 ifp->if_timer = 0; 1093} 1094 1095static void 1096emac_watchdog(struct ifnet *ifp) 1097{ 1098 struct emac_softc *sc = ifp->if_softc; 1099 1100 /* 1101 * Since we're not interrupting every packet, sweep 1102 * up before we report an error. 1103 */ 1104 emac_txreap(sc); 1105 1106 if (sc->sc_txfree != EMAC_NTXDESC) { 1107 aprint_error_ifnet(ifp, 1108 "device timeout (txfree %d txsfree %d txnext %d)\n", 1109 sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext); 1110 ifp->if_oerrors++; 1111 1112 /* Reset the interface. */ 1113 (void)emac_init(ifp); 1114 } else if (ifp->if_flags & IFF_DEBUG) 1115 aprint_error_ifnet(ifp, "recovered from device timeout\n"); 1116 1117 /* try to get more packets going */ 1118 emac_start(ifp); 1119} 1120 1121static int 1122emac_add_rxbuf(struct emac_softc *sc, int idx) 1123{ 1124 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1125 struct mbuf *m; 1126 int error; 1127 1128 MGETHDR(m, M_DONTWAIT, MT_DATA); 1129 if (m == NULL) 1130 return ENOBUFS; 1131 1132 MCLGET(m, M_DONTWAIT); 1133 if ((m->m_flags & M_EXT) == 0) { 1134 m_freem(m); 1135 return ENOBUFS; 1136 } 1137 1138 if (rxs->rxs_mbuf != NULL) 1139 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1140 1141 rxs->rxs_mbuf = m; 1142 1143 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1144 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1145 if (error) { 1146 aprint_error_dev(sc->sc_dev, 1147 "can't load rx DMA map %d, error = %d\n", idx, error); 1148 panic("emac_add_rxbuf"); /* XXX */ 1149 } 1150 1151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1152 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1153 1154 EMAC_INIT_RXDESC(sc, idx); 1155 1156 return 0; 1157} 1158 1159static void 1160emac_rxdrain(struct emac_softc *sc) 1161{ 1162 struct emac_rxsoft *rxs; 1163 int i; 1164 1165 for (i = 0; i < EMAC_NRXDESC; i++) { 1166 rxs = &sc->sc_rxsoft[i]; 1167 if (rxs->rxs_mbuf != NULL) { 1168 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1169 m_freem(rxs->rxs_mbuf); 1170 rxs->rxs_mbuf = NULL; 1171 } 1172 } 1173} 1174 1175static int 1176emac_set_filter(struct emac_softc *sc) 1177{ 1178 struct ether_multistep step; 1179 struct ether_multi *enm; 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1182 int regs, cnt = 0, i; 1183 1184 if (sc->sc_htsize == 256) { 1185 reg = EMAC_GAHT256(0); 1186 regs = 8; 1187 } else { 1188 reg = EMAC_GAHT64(0); 1189 regs = 4; 1190 } 1191 mask = (1ULL << (sc->sc_htsize / regs)) - 1; 1192 1193 rmr = EMAC_READ(sc, EMAC_RMR); 1194 rmr &= ~(RMR_PMME | RMR_MAE); 1195 ifp->if_flags &= ~IFF_ALLMULTI; 1196 1197 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1198 while (enm != NULL) { 1199 if (memcmp(enm->enm_addrlo, 1200 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1201 /* 1202 * We must listen to a range of multicast addresses. 1203 * For now, just accept all multicasts, rather than 1204 * trying to set only those filter bits needed to match 1205 * the range. (At this time, the only use of address 1206 * ranges is for IP multicast routing, for which the 1207 * range is big enough to require all bits set.) 1208 */ 1209 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 1210 gaht[4] = gaht[5] = gaht[6] = gaht[7] = mask; 1211 break; 1212 } 1213 1214 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1215 1216 if (sc->sc_htsize == 256) 1217 EMAC_SET_FILTER256(gaht, crc); 1218 else 1219 EMAC_SET_FILTER(gaht, crc); 1220 1221 ETHER_NEXT_MULTI(step, enm); 1222 cnt++; 1223 } 1224 1225 for (i = 1, tmp = gaht[0]; i < regs; i++) 1226 tmp &= gaht[i]; 1227 if (tmp == mask) { 1228 /* All categories are true. */ 1229 ifp->if_flags |= IFF_ALLMULTI; 1230 rmr |= RMR_PMME; 1231 } else if (cnt != 0) { 1232 /* Some categories are true. */ 1233 for (i = 0; i < regs; i++) 1234 EMAC_WRITE(sc, reg + (i << 2), gaht[i]); 1235 rmr |= RMR_MAE; 1236 } 1237 EMAC_WRITE(sc, EMAC_RMR, rmr); 1238 1239 return 0; 1240} 1241 1242/* 1243 * Reap completed Tx descriptors. 1244 */ 1245static int 1246emac_txreap(struct emac_softc *sc) 1247{ 1248 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1249 struct emac_txsoft *txs; 1250 int handled, i; 1251 uint32_t txstat; 1252 1253 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1254 handled = 0; 1255 1256 ifp->if_flags &= ~IFF_OACTIVE; 1257 1258 /* 1259 * Go through our Tx list and free mbufs for those 1260 * frames that have been transmitted. 1261 */ 1262 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1263 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1264 txs = &sc->sc_txsoft[i]; 1265 1266 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1267 txs->txs_dmamap->dm_nsegs, 1268 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1269 1270 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1271 if (txstat & MAL_TX_READY) 1272 break; 1273 1274 handled = 1; 1275 1276 /* 1277 * Check for errors and collisions. 1278 */ 1279 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1280 ifp->if_oerrors++; 1281 1282#ifdef EMAC_EVENT_COUNTERS 1283 if (txstat & EMAC_TXS_UR) 1284 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1285#endif /* EMAC_EVENT_COUNTERS */ 1286 1287 if (txstat & 1288 (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1289 if (txstat & EMAC_TXS_EC) 1290 ifp->if_collisions += 16; 1291 else if (txstat & EMAC_TXS_MC) 1292 ifp->if_collisions += 2; /* XXX? */ 1293 else if (txstat & EMAC_TXS_SC) 1294 ifp->if_collisions++; 1295 if (txstat & EMAC_TXS_LC) 1296 ifp->if_collisions++; 1297 } else 1298 ifp->if_opackets++; 1299 1300 if (ifp->if_flags & IFF_DEBUG) { 1301 if (txstat & EMAC_TXS_ED) 1302 aprint_error_ifnet(ifp, "excessive deferral\n"); 1303 if (txstat & EMAC_TXS_EC) 1304 aprint_error_ifnet(ifp, 1305 "excessive collisions\n"); 1306 } 1307 1308 sc->sc_txfree += txs->txs_ndesc; 1309 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1310 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1311 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1312 m_freem(txs->txs_mbuf); 1313 txs->txs_mbuf = NULL; 1314 } 1315 1316 /* Update the dirty transmit buffer pointer. */ 1317 sc->sc_txsdirty = i; 1318 1319 /* 1320 * If there are no more pending transmissions, cancel the watchdog 1321 * timer. 1322 */ 1323 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1324 ifp->if_timer = 0; 1325 1326 return handled; 1327} 1328 1329 1330/* 1331 * Reset functions 1332 */ 1333 1334static void 1335emac_soft_reset(struct emac_softc *sc) 1336{ 1337 uint32_t sdr; 1338 int t = 0; 1339 1340 /* 1341 * The PHY must provide a TX Clk in order perform a soft reset the 1342 * EMAC. If none is present, select the internal clock, 1343 * SDR0_MFR[E0CS,E1CS]. After the soft reset, select the external 1344 * clock. 1345 */ 1346 1347 sdr = mfsdr(DCR_SDR0_MFR); 1348 sdr |= SDR0_MFR_ECS(sc->sc_instance); 1349 mtsdr(DCR_SDR0_MFR, sdr); 1350 1351 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1352 1353 sdr = mfsdr(DCR_SDR0_MFR); 1354 sdr &= ~SDR0_MFR_ECS(sc->sc_instance); 1355 mtsdr(DCR_SDR0_MFR, sdr); 1356 1357 delay(5); 1358 1359 /* wait finish */ 1360 while (EMAC_READ(sc, EMAC_MR0) & MR0_SRST) { 1361 if (++t == 1000000 /* 1sec XXXXX */) { 1362 aprint_error_dev(sc->sc_dev, "Soft Reset failed\n"); 1363 return; 1364 } 1365 delay(1); 1366 } 1367} 1368 1369static void 1370emac_smart_reset(struct emac_softc *sc) 1371{ 1372 uint32_t mr0; 1373 int t = 0; 1374 1375 mr0 = EMAC_READ(sc, EMAC_MR0); 1376 if (mr0 & (MR0_TXE | MR0_RXE)) { 1377 mr0 &= ~(MR0_TXE | MR0_RXE); 1378 EMAC_WRITE(sc, EMAC_MR0, mr0); 1379 1380 /* wait idel state */ 1381 while ((EMAC_READ(sc, EMAC_MR0) & (MR0_TXI | MR0_RXI)) != 1382 (MR0_TXI | MR0_RXI)) { 1383 if (++t == 1000000 /* 1sec XXXXX */) { 1384 aprint_error_dev(sc->sc_dev, 1385 "Smart Reset failed\n"); 1386 return; 1387 } 1388 delay(1); 1389 } 1390 } 1391} 1392 1393 1394/* 1395 * MII related functions 1396 */ 1397 1398static int 1399emac_mii_readreg(device_t self, int phy, int reg) 1400{ 1401 struct emac_softc *sc = device_private(self); 1402 uint32_t sta_reg; 1403 1404 if (sc->sc_rmii_enable) 1405 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1406 1407 /* wait for PHY data transfer to complete */ 1408 if (emac_mii_wait(sc)) 1409 goto fail; 1410 1411 sta_reg = 1412 sc->sc_stacr_read | 1413 (reg << STACR_PRA_SHIFT) | 1414 (phy << STACR_PCDA_SHIFT) | 1415 sc->sc_stacr_bits; 1416 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1417 1418 if (emac_mii_wait(sc)) 1419 goto fail; 1420 sta_reg = EMAC_READ(sc, EMAC_STACR); 1421 1422 if (sc->sc_rmii_disable) 1423 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1424 1425 if (sta_reg & STACR_PHYE) 1426 return 0; 1427 return sta_reg >> STACR_PHYD_SHIFT; 1428 1429fail: 1430 if (sc->sc_rmii_disable) 1431 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1432 return 0; 1433} 1434 1435static void 1436emac_mii_writereg(device_t self, int phy, int reg, int val) 1437{ 1438 struct emac_softc *sc = device_private(self); 1439 uint32_t sta_reg; 1440 1441 if (sc->sc_rmii_enable) 1442 sc->sc_rmii_enable(device_parent(self), sc->sc_instance); 1443 1444 /* wait for PHY data transfer to complete */ 1445 if (emac_mii_wait(sc)) 1446 goto out; 1447 1448 sta_reg = 1449 (val << STACR_PHYD_SHIFT) | 1450 sc->sc_stacr_write | 1451 (reg << STACR_PRA_SHIFT) | 1452 (phy << STACR_PCDA_SHIFT) | 1453 sc->sc_stacr_bits; 1454 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1455 1456 if (emac_mii_wait(sc)) 1457 goto out; 1458 if (EMAC_READ(sc, EMAC_STACR) & STACR_PHYE) 1459 aprint_error_dev(sc->sc_dev, "MII PHY Error\n"); 1460 1461out: 1462 if (sc->sc_rmii_disable) 1463 sc->sc_rmii_disable(device_parent(self), sc->sc_instance); 1464} 1465 1466static void 1467emac_mii_statchg(struct ifnet *ifp) 1468{ 1469 struct emac_softc *sc = ifp->if_softc; 1470 struct mii_data *mii = &sc->sc_mii; 1471 1472 /* 1473 * MR1 can only be written immediately after a reset... 1474 */ 1475 emac_smart_reset(sc); 1476 1477 sc->sc_mr1 &= ~(MR1_FDE | MR1_ILE | MR1_EIFC | MR1_MF_MASK | MR1_IST); 1478 if (mii->mii_media_active & IFM_FDX) 1479 sc->sc_mr1 |= (MR1_FDE | MR1_EIFC | MR1_IST); 1480 if (mii->mii_media_active & IFM_FLOW) 1481 sc->sc_mr1 |= MR1_EIFC; 1482 if (mii->mii_media_active & IFM_LOOP) 1483 sc->sc_mr1 |= MR1_ILE; 1484 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1485 case IFM_1000_T: 1486 sc->sc_mr1 |= (MR1_MF_1000MBS | MR1_IST); 1487 break; 1488 1489 case IFM_100_TX: 1490 sc->sc_mr1 |= (MR1_MF_100MBS | MR1_IST); 1491 break; 1492 1493 case IFM_10_T: 1494 sc->sc_mr1 |= MR1_MF_10MBS; 1495 break; 1496 1497 case IFM_NONE: 1498 break; 1499 1500 default: 1501 aprint_error_dev(sc->sc_dev, "unknown sub-type %d\n", 1502 IFM_SUBTYPE(mii->mii_media_active)); 1503 break; 1504 } 1505 if (sc->sc_rmii_speed) 1506 sc->sc_rmii_speed(device_parent(sc->sc_dev), sc->sc_instance, 1507 IFM_SUBTYPE(mii->mii_media_active)); 1508 1509 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 1510 1511 /* Enable TX and RX if already RUNNING */ 1512 if (ifp->if_flags & IFF_RUNNING) 1513 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 1514} 1515 1516static uint32_t 1517emac_mii_wait(struct emac_softc *sc) 1518{ 1519 int i; 1520 uint32_t oc; 1521 1522 /* wait for PHY data transfer to complete */ 1523 i = 0; 1524 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1525 while ((oc == STACR_OC) != sc->sc_stacr_completed) { 1526 delay(7); 1527 if (i++ > 5) { 1528 aprint_error_dev(sc->sc_dev, "MII timed out\n"); 1529 return -1; 1530 } 1531 oc = EMAC_READ(sc, EMAC_STACR) & STACR_OC; 1532 } 1533 return 0; 1534} 1535 1536static void 1537emac_mii_tick(void *arg) 1538{ 1539 struct emac_softc *sc = arg; 1540 int s; 1541 1542 if (!device_is_active(sc->sc_dev)) 1543 return; 1544 1545 s = splnet(); 1546 mii_tick(&sc->sc_mii); 1547 splx(s); 1548 1549 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1550} 1551 1552int 1553emac_txeob_intr(void *arg) 1554{ 1555 struct emac_softc *sc = arg; 1556 int handled = 0; 1557 1558 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1559 handled |= emac_txreap(sc); 1560 1561 /* try to get more packets going */ 1562 emac_start(&sc->sc_ethercom.ec_if); 1563 1564 return handled; 1565} 1566 1567int 1568emac_rxeob_intr(void *arg) 1569{ 1570 struct emac_softc *sc = arg; 1571 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1572 struct emac_rxsoft *rxs; 1573 struct mbuf *m; 1574 uint32_t rxstat; 1575 int i, len; 1576 1577 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1578 1579 for (i = sc->sc_rxptr; ; i = EMAC_NEXTRX(i)) { 1580 rxs = &sc->sc_rxsoft[i]; 1581 1582 EMAC_CDRXSYNC(sc, i, 1583 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1584 1585 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1586 1587 if (rxstat & MAL_RX_EMPTY) { 1588 /* 1589 * We have processed all of the receive buffers. 1590 */ 1591 /* Flush current empty descriptor */ 1592 EMAC_CDRXSYNC(sc, i, 1593 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1594 break; 1595 } 1596 1597 /* 1598 * If an error occurred, update stats, clear the status 1599 * word, and leave the packet buffer in place. It will 1600 * simply be reused the next time the ring comes around. 1601 */ 1602 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1603 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1604 EMAC_RXS_IRE)) { 1605#define PRINTERR(bit, str) \ 1606 if (rxstat & (bit)) \ 1607 aprint_error_ifnet(ifp, \ 1608 "receive error: %s\n", str) 1609 ifp->if_ierrors++; 1610 PRINTERR(EMAC_RXS_OE, "overrun error"); 1611 PRINTERR(EMAC_RXS_BP, "bad packet"); 1612 PRINTERR(EMAC_RXS_RP, "runt packet"); 1613 PRINTERR(EMAC_RXS_SE, "short event"); 1614 PRINTERR(EMAC_RXS_AE, "alignment error"); 1615 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1616 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1617 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1618 PRINTERR(EMAC_RXS_IRE, "in range error"); 1619#undef PRINTERR 1620 EMAC_INIT_RXDESC(sc, i); 1621 continue; 1622 } 1623 1624 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1625 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1626 1627 /* 1628 * No errors; receive the packet. Note, the 405GP emac 1629 * includes the CRC with every packet. 1630 */ 1631 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1632 1633 /* 1634 * If the packet is small enough to fit in a 1635 * single header mbuf, allocate one and copy 1636 * the data into it. This greatly reduces 1637 * memory consumption when we receive lots 1638 * of small packets. 1639 * 1640 * Otherwise, we add a new buffer to the receive 1641 * chain. If this fails, we drop the packet and 1642 * recycle the old buffer. 1643 */ 1644 if (emac_copy_small != 0 && len <= MHLEN) { 1645 MGETHDR(m, M_DONTWAIT, MT_DATA); 1646 if (m == NULL) 1647 goto dropit; 1648 memcpy(mtod(m, void *), 1649 mtod(rxs->rxs_mbuf, void *), len); 1650 EMAC_INIT_RXDESC(sc, i); 1651 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1652 rxs->rxs_dmamap->dm_mapsize, 1653 BUS_DMASYNC_PREREAD); 1654 } else { 1655 m = rxs->rxs_mbuf; 1656 if (emac_add_rxbuf(sc, i) != 0) { 1657 dropit: 1658 ifp->if_ierrors++; 1659 EMAC_INIT_RXDESC(sc, i); 1660 bus_dmamap_sync(sc->sc_dmat, 1661 rxs->rxs_dmamap, 0, 1662 rxs->rxs_dmamap->dm_mapsize, 1663 BUS_DMASYNC_PREREAD); 1664 continue; 1665 } 1666 } 1667 1668 ifp->if_ipackets++; 1669 m_set_rcvif(m, ifp); 1670 m->m_pkthdr.len = m->m_len = len; 1671 1672 /* 1673 * Pass this up to any BPF listeners, but only 1674 * pass it up the stack if it's for us. 1675 */ 1676 bpf_mtap(ifp, m); 1677 1678 /* Pass it on. */ 1679 if_percpuq_enqueue(ifp->if_percpuq, m); 1680 } 1681 1682 /* Update the receive pointer. */ 1683 sc->sc_rxptr = i; 1684 1685 return 1; 1686} 1687 1688int 1689emac_txde_intr(void *arg) 1690{ 1691 struct emac_softc *sc = arg; 1692 1693 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1694 aprint_error_dev(sc->sc_dev, "emac_txde_intr\n"); 1695 return 1; 1696} 1697 1698int 1699emac_rxde_intr(void *arg) 1700{ 1701 struct emac_softc *sc = arg; 1702 int i; 1703 1704 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1705 aprint_error_dev(sc->sc_dev, "emac_rxde_intr\n"); 1706 /* 1707 * XXX! 1708 * This is a bit drastic; we just drop all descriptors that aren't 1709 * "clean". We should probably send any that are up the stack. 1710 */ 1711 for (i = 0; i < EMAC_NRXDESC; i++) { 1712 EMAC_CDRXSYNC(sc, i, 1713 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1714 1715 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) 1716 EMAC_INIT_RXDESC(sc, i); 1717 } 1718 1719 return 1; 1720} 1721