if_emac.c revision 1.12
1/* $NetBSD: if_emac.c,v 1.12 2002/10/01 02:49:56 thorpej Exp $ */ 2 3/* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include "bpfilter.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/mbuf.h> 43#include <sys/kernel.h> 44#include <sys/socket.h> 45#include <sys/ioctl.h> 46 47#include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 48 49#include <net/if.h> 50#include <net/if_dl.h> 51#include <net/if_media.h> 52#include <net/if_ether.h> 53 54#if NBPFILTER > 0 55#include <net/bpf.h> 56#endif 57 58#include <powerpc/ibm4xx/dev/opbvar.h> 59 60#include <powerpc/ibm4xx/ibm405gp.h> 61#include <powerpc/ibm4xx/mal405gp.h> 62#include <powerpc/ibm4xx/dcr405gp.h> 63#include <powerpc/ibm4xx/dev/emacreg.h> 64#include <powerpc/ibm4xx/dev/if_emacreg.h> 65 66#include <dev/mii/miivar.h> 67 68/* 69 * Transmit descriptor list size. There are two Tx channels, each with 70 * up to 256 hardware descriptors available. We currently use one Tx 71 * channel. We tell the upper layers that they can queue a lot of 72 * packets, and we go ahead and manage up to 64 of them at a time. We 73 * allow up to 16 DMA segments per packet. 74 */ 75#define EMAC_NTXSEGS 16 76#define EMAC_TXQUEUELEN 64 77#define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 78#define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 79#define EMAC_NTXDESC 256 80#define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 81#define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 82#define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 83 84/* 85 * Receive descriptor list size. There is one Rx channel with up to 256 86 * hardware descriptors available. We allocate 64 receive descriptors, 87 * each with a 2k buffer (MCLBYTES). 88 */ 89#define EMAC_NRXDESC 64 90#define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 91#define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 92#define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 93 94/* 95 * Transmit/receive descriptors that are DMA'd to the EMAC. 96 */ 97struct emac_control_data { 98 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 99 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 100}; 101 102#define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 103#define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 104#define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 105 106/* 107 * Software state for transmit jobs. 108 */ 109struct emac_txsoft { 110 struct mbuf *txs_mbuf; /* head of mbuf chain */ 111 bus_dmamap_t txs_dmamap; /* our DMA map */ 112 int txs_firstdesc; /* first descriptor in packet */ 113 int txs_lastdesc; /* last descriptor in packet */ 114 int txs_ndesc; /* # of descriptors used */ 115}; 116 117/* 118 * Software state for receive descriptors. 119 */ 120struct emac_rxsoft { 121 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 122 bus_dmamap_t rxs_dmamap; /* our DMA map */ 123}; 124 125/* 126 * Software state per device. 127 */ 128struct emac_softc { 129 struct device sc_dev; /* generic device information */ 130 bus_space_tag_t sc_st; /* bus space tag */ 131 bus_space_handle_t sc_sh; /* bus space handle */ 132 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 133 struct ethercom sc_ethercom; /* ethernet common data */ 134 void *sc_sdhook; /* shutdown hook */ 135 void *sc_powerhook; /* power management hook */ 136 137 struct mii_data sc_mii; /* MII/media information */ 138 struct callout sc_callout; /* tick callout */ 139 140 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 141 142 bus_dmamap_t sc_cddmamap; /* control data dma map */ 143#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 144 145 /* Software state for transmit/receive descriptors. */ 146 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 147 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 148 149 /* Control data structures. */ 150 struct emac_control_data *sc_control_data; 151#define sc_txdescs sc_control_data->ecd_txdesc 152#define sc_rxdescs sc_control_data->ecd_rxdesc 153 154#ifdef EMAC_EVENT_COUNTERS 155 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 156 struct evcnt sc_ev_txintr; /* Tx interrupts */ 157 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 158 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 159 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 160 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 161 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 162 163 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 164 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 165 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 166 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 167 struct evcnt sc_ev_tu; /* Tx underrun */ 168#endif /* EMAC_EVENT_COUNTERS */ 169 170 int sc_txfree; /* number of free Tx descriptors */ 171 int sc_txnext; /* next ready Tx descriptor */ 172 173 int sc_txsfree; /* number of free Tx jobs */ 174 int sc_txsnext; /* next ready Tx job */ 175 int sc_txsdirty; /* dirty Tx jobs */ 176 177 int sc_rxptr; /* next ready RX descriptor/descsoft */ 178}; 179 180#ifdef EMAC_EVENT_COUNTERS 181#define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 182#else 183#define EMAC_EVCNT_INCR(ev) /* nothing */ 184#endif 185 186#define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 187#define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 188 189#define EMAC_CDTXSYNC(sc, x, n, ops) \ 190do { \ 191 int __x, __n; \ 192 \ 193 __x = (x); \ 194 __n = (n); \ 195 \ 196 /* If it will wrap around, sync to the end of the ring. */ \ 197 if ((__x + __n) > EMAC_NTXDESC) { \ 198 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 199 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 200 (EMAC_NTXDESC - __x), (ops)); \ 201 __n -= (EMAC_NTXDESC - __x); \ 202 __x = 0; \ 203 } \ 204 \ 205 /* Now sync whatever is left. */ \ 206 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 207 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 208} while (/*CONSTCOND*/0) 209 210#define EMAC_CDRXSYNC(sc, x, ops) \ 211do { \ 212 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 213 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 214} while (/*CONSTCOND*/0) 215 216#define EMAC_INIT_RXDESC(sc, x) \ 217do { \ 218 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 219 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 220 struct mbuf *__m = __rxs->rxs_mbuf; \ 221 \ 222 /* \ 223 * Note: We scoot the packet forward 2 bytes in the buffer \ 224 * so that the payload after the Ethernet header is aligned \ 225 * to a 4-byte boundary. \ 226 */ \ 227 __m->m_data = __m->m_ext.ext_buf + 2; \ 228 \ 229 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 230 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 231 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 232 /* Set wrap on last descriptor. */ \ 233 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 234 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 235} while (/*CONSTCOND*/0) 236 237#define EMAC_WRITE(sc, reg, val) \ 238 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 239#define EMAC_READ(sc, reg) \ 240 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 241 242static int emac_match(struct device *, struct cfdata *, void *); 243static void emac_attach(struct device *, struct device *, void *); 244 245static int emac_add_rxbuf(struct emac_softc *, int); 246static int emac_init(struct ifnet *); 247static int emac_ioctl(struct ifnet *, u_long, caddr_t); 248static void emac_reset(struct emac_softc *); 249static void emac_rxdrain(struct emac_softc *); 250static int emac_txreap(struct emac_softc *); 251static void emac_shutdown(void *); 252static void emac_start(struct ifnet *); 253static void emac_stop(struct ifnet *, int); 254static void emac_watchdog(struct ifnet *); 255 256static int emac_wol_intr(void *); 257static int emac_serr_intr(void *); 258static int emac_txeob_intr(void *); 259static int emac_rxeob_intr(void *); 260static int emac_txde_intr(void *); 261static int emac_rxde_intr(void *); 262static int emac_intr(void *); 263 264static int emac_mediachange(struct ifnet *); 265static void emac_mediastatus(struct ifnet *, struct ifmediareq *); 266static int emac_mii_readreg(struct device *, int, int); 267static void emac_mii_statchg(struct device *); 268static void emac_mii_tick(void *); 269static uint32_t emac_mii_wait(struct emac_softc *); 270static void emac_mii_writereg(struct device *, int, int, int); 271 272int emac_copy_small = 0; 273 274CFATTACH_DECL(emac, sizeof(struct emac_softc), 275 emac_match, emac_attach, NULL, NULL) 276 277static int 278emac_match(struct device *parent, struct cfdata *cf, void *aux) 279{ 280 struct opb_attach_args *oaa = aux; 281 282 /* match only on-chip ethernet devices */ 283 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 284 return (1); 285 286 return (0); 287} 288 289static void 290emac_attach(struct device *parent, struct device *self, void *aux) 291{ 292 struct opb_attach_args *oaa = aux; 293 struct emac_softc *sc = (struct emac_softc *)self; 294 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 295 struct mii_data *mii = &sc->sc_mii; 296 bus_dma_segment_t seg; 297 int error, i, nseg; 298 299 sc->sc_st = oaa->opb_bt; 300 sc->sc_sh = oaa->opb_addr; 301 sc->sc_dmat = oaa->opb_dmat; 302 303 printf(": 405GP EMAC\n"); 304 305 /* 306 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 307 * size, allow transmit of multiple packets (only channel 0 is used). 308 * 309 * XXX: Allow pause packets?? 310 */ 311 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 312 313 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 314 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 315 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 316 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 317 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 318 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 319 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 320 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 321 oaa->opb_irq, oaa->opb_irq + 6); 322 323 /* 324 * Allocate the control data structures, and create and load the 325 * DMA map for it. 326 */ 327 if ((error = bus_dmamem_alloc(sc->sc_dmat, 328 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 329 printf("%s: unable to allocate control data, error = %d\n", 330 sc->sc_dev.dv_xname, error); 331 goto fail_0; 332 } 333 334 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 335 sizeof(struct emac_control_data), (caddr_t *)&sc->sc_control_data, 336 BUS_DMA_COHERENT)) != 0) { 337 printf("%s: unable to map control data, error = %d\n", 338 sc->sc_dev.dv_xname, error); 339 goto fail_1; 340 } 341 342 if ((error = bus_dmamap_create(sc->sc_dmat, 343 sizeof(struct emac_control_data), 1, 344 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 345 printf("%s: unable to create control data DMA map, " 346 "error = %d\n", sc->sc_dev.dv_xname, error); 347 goto fail_2; 348 } 349 350 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 351 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 352 0)) != 0) { 353 printf("%s: unable to load control data DMA map, error = %d\n", 354 sc->sc_dev.dv_xname, error); 355 goto fail_3; 356 } 357 358 /* 359 * Create the transmit buffer DMA maps. 360 */ 361 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 362 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 363 EMAC_NTXSEGS, MCLBYTES, 0, 0, 364 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 365 printf("%s: unable to create tx DMA map %d, " 366 "error = %d\n", sc->sc_dev.dv_xname, i, error); 367 goto fail_4; 368 } 369 } 370 371 /* 372 * Create the receive buffer DMA maps. 373 */ 374 for (i = 0; i < EMAC_NRXDESC; i++) { 375 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 376 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 377 printf("%s: unable to create rx DMA map %d, " 378 "error = %d\n", sc->sc_dev.dv_xname, i, error); 379 goto fail_5; 380 } 381 sc->sc_rxsoft[i].rxs_mbuf = NULL; 382 } 383 384 /* 385 * Reset the chip to a known state. 386 */ 387 emac_reset(sc); 388 389 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 390 ether_sprintf(board_data.mac_address_local)); 391 392 /* 393 * Initialise the media structures. 394 */ 395 mii->mii_ifp = ifp; 396 mii->mii_readreg = emac_mii_readreg; 397 mii->mii_writereg = emac_mii_writereg; 398 mii->mii_statchg = emac_mii_statchg; 399 400 ifmedia_init(&mii->mii_media, 0, emac_mediachange, 401 emac_mediastatus); 402 mii_attach(&sc->sc_dev, mii, 0xffffffff, 403 MII_PHY_ANY, MII_OFFSET_ANY, 0); 404 if (LIST_FIRST(&mii->mii_phys) == NULL) { 405 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 406 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 407 } else 408 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 409 410 ifp = &sc->sc_ethercom.ec_if; 411 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 412 ifp->if_softc = sc; 413 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 414 ifp->if_ioctl = emac_ioctl; 415 ifp->if_start = emac_start; 416 ifp->if_watchdog = emac_watchdog; 417 ifp->if_init = emac_init; 418 ifp->if_stop = emac_stop; 419 IFQ_SET_READY(&ifp->if_snd); 420 421 /* 422 * We can support 802.1Q VLAN-sized frames. 423 */ 424 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 425 426 /* 427 * Attach the interface. 428 */ 429 if_attach(ifp); 430 ether_ifattach(ifp, board_data.mac_address_local); 431 432#ifdef EMAC_EVENT_COUNTERS 433 /* 434 * Attach the event counters. 435 */ 436 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 437 NULL, sc->sc_dev.dv_xname, "rxintr"); 438 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 439 NULL, sc->sc_dev.dv_xname, "txintr"); 440 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 441 NULL, sc->sc_dev.dv_xname, "rxde"); 442 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 443 NULL, sc->sc_dev.dv_xname, "txde"); 444 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 445 NULL, sc->sc_dev.dv_xname, "wol"); 446 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 447 NULL, sc->sc_dev.dv_xname, "serr"); 448 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 449 NULL, sc->sc_dev.dv_xname, "intr"); 450 451 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 452 NULL, sc->sc_dev.dv_xname, "txreap"); 453 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 454 NULL, sc->sc_dev.dv_xname, "txsstall"); 455 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 456 NULL, sc->sc_dev.dv_xname, "txdstall"); 457 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 458 NULL, sc->sc_dev.dv_xname, "txdrop"); 459 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 460 NULL, sc->sc_dev.dv_xname, "tu"); 461#endif /* EMAC_EVENT_COUNTERS */ 462 463 /* 464 * Make sure the interface is shutdown during reboot. 465 */ 466 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 467 if (sc->sc_sdhook == NULL) 468 printf("%s: WARNING: unable to establish shutdown hook\n", 469 sc->sc_dev.dv_xname); 470 471 return; 472 473 /* 474 * Free any resources we've allocated during the failed attach 475 * attempt. Do this in reverse order and fall through. 476 */ 477fail_5: 478 for (i = 0; i < EMAC_NRXDESC; i++) { 479 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 480 bus_dmamap_destroy(sc->sc_dmat, 481 sc->sc_rxsoft[i].rxs_dmamap); 482 } 483fail_4: 484 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 485 if (sc->sc_txsoft[i].txs_dmamap != NULL) 486 bus_dmamap_destroy(sc->sc_dmat, 487 sc->sc_txsoft[i].txs_dmamap); 488 } 489 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 490fail_3: 491 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 492fail_2: 493 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 494 sizeof(struct emac_control_data)); 495fail_1: 496 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 497fail_0: 498 return; 499} 500 501/* 502 * Device shutdown routine. 503 */ 504static void 505emac_shutdown(void *arg) 506{ 507 struct emac_softc *sc = arg; 508 509 emac_stop(&sc->sc_ethercom.ec_if, 0); 510} 511 512/* ifnet interface function */ 513static void 514emac_start(struct ifnet *ifp) 515{ 516 struct emac_softc *sc = ifp->if_softc; 517 struct mbuf *m0; 518 struct emac_txsoft *txs; 519 bus_dmamap_t dmamap; 520 int error, firsttx, nexttx, lasttx, ofree, seg; 521 522 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 523 return; 524 525 /* 526 * Remember the previous number of free descriptors. 527 */ 528 ofree = sc->sc_txfree; 529 530 /* 531 * Loop through the send queue, setting up transmit descriptors 532 * until we drain the queue, or use up all available transmit 533 * descriptors. 534 */ 535 for (;;) { 536 /* Grab a packet off the queue. */ 537 IFQ_POLL(&ifp->if_snd, m0); 538 if (m0 == NULL) 539 break; 540 541 /* 542 * Get a work queue entry. Reclaim used Tx descriptors if 543 * we are running low. 544 */ 545 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 546 emac_txreap(sc); 547 if (sc->sc_txsfree == 0) { 548 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 549 break; 550 } 551 } 552 553 txs = &sc->sc_txsoft[sc->sc_txsnext]; 554 dmamap = txs->txs_dmamap; 555 556 /* 557 * Load the DMA map. If this fails, the packet either 558 * didn't fit in the alloted number of segments, or we 559 * were short on resources. In this case, we'll copy 560 * and try again. 561 */ 562 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 563 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 564 if (error) { 565 if (error == EFBIG) { 566 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 567 printf("%s: Tx packet consumes too many " 568 "DMA segments, dropping...\n", 569 sc->sc_dev.dv_xname); 570 IFQ_DEQUEUE(&ifp->if_snd, m0); 571 m_freem(m0); 572 continue; 573 } 574 /* Short on resources, just stop for now. */ 575 break; 576 } 577 578 /* 579 * Ensure we have enough descriptors free to describe 580 * the packet. 581 */ 582 if (dmamap->dm_nsegs > sc->sc_txfree) { 583 /* 584 * Not enough free descriptors to transmit this 585 * packet. We haven't committed anything yet, 586 * so just unload the DMA map, put the packet 587 * back on the queue, and punt. Notify the upper 588 * layer that there are not more slots left. 589 * 590 */ 591 ifp->if_flags |= IFF_OACTIVE; 592 bus_dmamap_unload(sc->sc_dmat, dmamap); 593 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 594 break; 595 } 596 597 IFQ_DEQUEUE(&ifp->if_snd, m0); 598 599 /* 600 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 601 */ 602 603 /* Sync the DMA map. */ 604 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 605 BUS_DMASYNC_PREWRITE); 606 607 /* 608 * Store a pointer to the packet so that we can free it 609 * later. 610 */ 611 txs->txs_mbuf = m0; 612 txs->txs_firstdesc = sc->sc_txnext; 613 txs->txs_ndesc = dmamap->dm_nsegs; 614 615 /* 616 * Initialize the transmit descriptor. 617 */ 618 firsttx = sc->sc_txnext; 619 for (nexttx = sc->sc_txnext, seg = 0; 620 seg < dmamap->dm_nsegs; 621 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 622 /* 623 * If this is the first descriptor we're 624 * enqueueing, don't set the TX_READY bit just 625 * yet. That could cause a race condition. 626 * We'll do it below. 627 */ 628 sc->sc_txdescs[nexttx].md_data = 629 dmamap->dm_segs[seg].ds_addr; 630 sc->sc_txdescs[nexttx].md_data_len = 631 dmamap->dm_segs[seg].ds_len; 632 sc->sc_txdescs[nexttx].md_stat_ctrl = 633 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 634 (nexttx == firsttx ? 0 : MAL_TX_READY) | 635 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 636 lasttx = nexttx; 637 } 638 639 /* Set the LAST bit on the last segment. */ 640 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 641 642 txs->txs_lastdesc = lasttx; 643 644 /* Sync the descriptors we're using. */ 645 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 646 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 647 648 /* 649 * The entire packet chain is set up. Give the 650 * first descriptor to the chip now. 651 */ 652 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 653 EMAC_CDTXSYNC(sc, firsttx, 1, 654 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 655 /* 656 * Tell the EMAC that a new packet is available. 657 */ 658 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 659 660 /* Advance the tx pointer. */ 661 sc->sc_txfree -= txs->txs_ndesc; 662 sc->sc_txnext = nexttx; 663 664 sc->sc_txsfree--; 665 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 666 667#if NBPFILTER > 0 668 /* 669 * Pass the packet to any BPF listeners. 670 */ 671 if (ifp->if_bpf) 672 bpf_mtap(ifp->if_bpf, m0); 673#endif /* NBPFILTER > 0 */ 674 } 675 676 if (txs == NULL || sc->sc_txfree == 0) { 677 /* No more slots left; notify upper layer. */ 678 ifp->if_flags |= IFF_OACTIVE; 679 } 680 681 if (sc->sc_txfree != ofree) { 682 /* Set a watchdog timer in case the chip flakes out. */ 683 ifp->if_timer = 5; 684 } 685} 686 687static int 688emac_init(struct ifnet *ifp) 689{ 690 struct emac_softc *sc = ifp->if_softc; 691 struct emac_rxsoft *rxs; 692 unsigned char *enaddr = board_data.mac_address_local; 693 int error, i; 694 695 error = 0; 696 697 /* Cancel any pending I/O. */ 698 emac_stop(ifp, 0); 699 700 /* Reset the chip to a known state. */ 701 emac_reset(sc); 702 703 /* 704 * Initialise the transmit descriptor ring. 705 */ 706 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 707 /* set wrap on last descriptor */ 708 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 709 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 sc->sc_txfree = EMAC_NTXDESC; 712 sc->sc_txnext = 0; 713 714 /* 715 * Initialise the transmit job descriptors. 716 */ 717 for (i = 0; i < EMAC_TXQUEUELEN; i++) 718 sc->sc_txsoft[i].txs_mbuf = NULL; 719 sc->sc_txsfree = EMAC_TXQUEUELEN; 720 sc->sc_txsnext = 0; 721 sc->sc_txsdirty = 0; 722 723 /* 724 * Initialise the receiver descriptor and receive job 725 * descriptor rings. 726 */ 727 for (i = 0; i < EMAC_NRXDESC; i++) { 728 rxs = &sc->sc_rxsoft[i]; 729 if (rxs->rxs_mbuf == NULL) { 730 if ((error = emac_add_rxbuf(sc, i)) != 0) { 731 printf("%s: unable to allocate or map rx " 732 "buffer %d, error = %d\n", 733 sc->sc_dev.dv_xname, i, error); 734 /* 735 * XXX Should attempt to run with fewer receive 736 * XXX buffers instead of just failing. 737 */ 738 emac_rxdrain(sc); 739 goto out; 740 } 741 } else 742 EMAC_INIT_RXDESC(sc, i); 743 } 744 sc->sc_rxptr = 0; 745 746 /* 747 * Set the current media. 748 */ 749 mii_mediachg(&sc->sc_mii); 750 751 /* 752 * Give the transmit and receive rings to the MAL. 753 */ 754 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 755 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 756 757 /* 758 * Load the MAC address. 759 */ 760 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 761 EMAC_WRITE(sc, EMAC_IALR, 762 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 763 764 /* 765 * Set the receive channel buffer size (in units of 16 bytes). 766 */ 767#if MCLBYTES > (4096 - 16) /* XXX! */ 768# error MCLBYTES > max rx channel buffer size 769#endif 770 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 771 772 /* Set fifos, media modes. */ 773 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 774 775 /* 776 * Enable Individual and (possibly) Broadcast Address modes, 777 * runt packets, and strip padding. 778 * 779 * XXX: promiscuous mode (and promiscuous multicast mode) need to be 780 * dealt with here! 781 */ 782 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 783 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 784 785 /* 786 * Set low- and urgent-priority request thresholds. 787 */ 788 EMAC_WRITE(sc, EMAC_TMR1, 789 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 790 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 791 /* 792 * Set Transmit Request Threshold Register. 793 */ 794 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 795 796 /* 797 * Set high and low receive watermarks. 798 */ 799 EMAC_WRITE(sc, EMAC_RWMR, 800 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 801 802 /* 803 * Set frame gap. 804 */ 805 EMAC_WRITE(sc, EMAC_IPGVR, 8); 806 807 /* 808 * Set interrupt status enable bits for EMAC and MAL. 809 */ 810 EMAC_WRITE(sc, EMAC_ISER, 811 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 812 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 813 MAL0_IER_OPB | MAL0_IER_PLB); 814 815 /* 816 * Enable the transmit and receive channel on the MAL. 817 */ 818 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 819 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 820 821 /* 822 * Enable the transmit and receive channel on the EMAC. 823 */ 824 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 825 826 /* 827 * Start the one second MII clock. 828 */ 829 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 830 831 /* 832 * ... all done! 833 */ 834 ifp->if_flags |= IFF_RUNNING; 835 ifp->if_flags &= ~IFF_OACTIVE; 836 837 out: 838 if (error) { 839 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 840 ifp->if_timer = 0; 841 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 842 } 843 return (error); 844} 845 846static int 847emac_add_rxbuf(struct emac_softc *sc, int idx) 848{ 849 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 850 struct mbuf *m; 851 int error; 852 853 MGETHDR(m, M_DONTWAIT, MT_DATA); 854 if (m == NULL) 855 return (ENOBUFS); 856 857 MCLGET(m, M_DONTWAIT); 858 if ((m->m_flags & M_EXT) == 0) { 859 m_freem(m); 860 return (ENOBUFS); 861 } 862 863 if (rxs->rxs_mbuf != NULL) 864 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 865 866 rxs->rxs_mbuf = m; 867 868 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 869 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 870 if (error) { 871 printf("%s: can't load rx DMA map %d, error = %d\n", 872 sc->sc_dev.dv_xname, idx, error); 873 panic("emac_add_rxbuf"); /* XXX */ 874 } 875 876 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 877 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 878 879 EMAC_INIT_RXDESC(sc, idx); 880 881 return (0); 882} 883 884/* ifnet interface function */ 885static void 886emac_watchdog(struct ifnet *ifp) 887{ 888 struct emac_softc *sc = ifp->if_softc; 889 890 /* 891 * Since we're not interrupting every packet, sweep 892 * up before we report an error. 893 */ 894 emac_txreap(sc); 895 896 if (sc->sc_txfree != EMAC_NTXDESC) { 897 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 898 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 899 sc->sc_txnext); 900 ifp->if_oerrors++; 901 902 /* Reset the interface. */ 903 (void)emac_init(ifp); 904 } else if (ifp->if_flags & IFF_DEBUG) 905 printf("%s: recovered from device timeout\n", 906 sc->sc_dev.dv_xname); 907 908 /* try to get more packets going */ 909 emac_start(ifp); 910} 911 912static void 913emac_rxdrain(struct emac_softc *sc) 914{ 915 struct emac_rxsoft *rxs; 916 int i; 917 918 for (i = 0; i < EMAC_NRXDESC; i++) { 919 rxs = &sc->sc_rxsoft[i]; 920 if (rxs->rxs_mbuf != NULL) { 921 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 922 m_freem(rxs->rxs_mbuf); 923 rxs->rxs_mbuf = NULL; 924 } 925 } 926} 927 928/* ifnet interface function */ 929static void 930emac_stop(struct ifnet *ifp, int disable) 931{ 932 struct emac_softc *sc = ifp->if_softc; 933 struct emac_txsoft *txs; 934 int i; 935 936 /* Stop the one second clock. */ 937 callout_stop(&sc->sc_callout); 938 939 /* Down the MII */ 940 mii_down(&sc->sc_mii); 941 942 /* Disable interrupts. */ 943#if 0 /* Can't disable MAL interrupts without a reset... */ 944 EMAC_WRITE(sc, EMAC_ISER, 0); 945#endif 946 mtdcr(DCR_MAL0_IER, 0); 947 948 /* Disable the receive and transmit channels. */ 949 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 950 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 951 952 /* Disable the transmit enable and receive MACs. */ 953 EMAC_WRITE(sc, EMAC_MR0, 954 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 955 956 /* Release any queued transmit buffers. */ 957 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 958 txs = &sc->sc_txsoft[i]; 959 if (txs->txs_mbuf != NULL) { 960 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 961 m_freem(txs->txs_mbuf); 962 txs->txs_mbuf = NULL; 963 } 964 } 965 966 if (disable) 967 emac_rxdrain(sc); 968 969 /* 970 * Mark the interface down and cancel the watchdog timer. 971 */ 972 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 973 ifp->if_timer = 0; 974} 975 976/* ifnet interface function */ 977static int 978emac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 979{ 980 struct emac_softc *sc = ifp->if_softc; 981 struct ifreq *ifr = (struct ifreq *)data; 982 int s, error; 983 984 s = splnet(); 985 986 switch (cmd) { 987 case SIOCSIFMEDIA: 988 case SIOCGIFMEDIA: 989 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 990 break; 991 992 default: 993 error = ether_ioctl(ifp, cmd, data); 994 if (error == ENETRESET) { 995 /* 996 * Multicast list has changed; set the hardware filter 997 * accordingly. 998 */ 999#if 0 1000 error = emac_set_filter(sc); /* XXX not done yet */ 1001#else 1002 error = emac_init(ifp); 1003#endif 1004 } 1005 break; 1006 } 1007 1008 /* try to get more packets going */ 1009 emac_start(ifp); 1010 1011 splx(s); 1012 return (error); 1013} 1014 1015static void 1016emac_reset(struct emac_softc *sc) 1017{ 1018 1019 /* reset the MAL */ 1020 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1021 1022 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1023 delay(5); 1024 1025 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1026 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1027 1028 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1029 1030 /* set the MAL config register */ 1031 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1032 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1033} 1034 1035/* 1036 * EMAC General interrupt handler 1037 */ 1038static int 1039emac_intr(void *arg) 1040{ 1041 struct emac_softc *sc = arg; 1042 uint32_t status; 1043 1044 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1045 status = EMAC_READ(sc, EMAC_ISR); 1046 1047 /* Clear the interrupt status bits. */ 1048 EMAC_WRITE(sc, EMAC_ISR, status); 1049 1050 return (0); 1051} 1052 1053/* 1054 * EMAC Wake-On-LAN interrupt handler 1055 */ 1056static int 1057emac_wol_intr(void *arg) 1058{ 1059 struct emac_softc *sc = arg; 1060 1061 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1062 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1063 return (0); 1064} 1065 1066/* 1067 * MAL System ERRor interrupt handler 1068 */ 1069static int 1070emac_serr_intr(void *arg) 1071{ 1072#ifdef EMAC_EVENT_COUNTERS 1073 struct emac_softc *sc = arg; 1074#endif 1075 u_int32_t esr; 1076 1077 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1078 esr = mfdcr(DCR_MAL0_ESR); 1079 1080 /* Clear the interrupt status bits. */ 1081 mtdcr(DCR_MAL0_ESR, esr); 1082 return (0); 1083} 1084 1085/* 1086 * MAL Transmit End-Of-Buffer interrupt handler. 1087 * NOTE: This shouldn't be called! 1088 */ 1089static int 1090emac_txeob_intr(void *arg) 1091{ 1092#ifdef EMAC_EVENT_COUNTERS 1093 struct emac_softc *sc = arg; 1094#endif 1095 1096 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1097 emac_txreap(arg); 1098 1099 return (0); 1100 1101} 1102 1103/* 1104 * Reap completed Tx descriptors. 1105 */ 1106static int 1107emac_txreap(struct emac_softc *sc) 1108{ 1109 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1110 struct emac_txsoft *txs; 1111 int i; 1112 u_int32_t txstat; 1113 1114 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1115 1116 /* Clear the interrupt */ 1117 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1118 1119 ifp->if_flags &= ~IFF_OACTIVE; 1120 1121 /* 1122 * Go through our Tx list and free mbufs for those 1123 * frames that have been transmitted. 1124 */ 1125 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1126 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1127 txs = &sc->sc_txsoft[i]; 1128 1129 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1130 txs->txs_dmamap->dm_nsegs, 1131 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1132 1133 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1134 if (txstat & MAL_TX_READY) 1135 break; 1136 1137 /* 1138 * Check for errors and collisions. 1139 */ 1140 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1141 ifp->if_oerrors++; 1142 1143#ifdef EMAC_EVENT_COUNTERS 1144 if (txstat & EMAC_TXS_UR) 1145 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1146#endif /* EMAC_EVENT_COUNTERS */ 1147 1148 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1149 if (txstat & EMAC_TXS_EC) 1150 ifp->if_collisions += 16; 1151 else if (txstat & EMAC_TXS_MC) 1152 ifp->if_collisions += 2; /* XXX? */ 1153 else if (txstat & EMAC_TXS_SC) 1154 ifp->if_collisions++; 1155 if (txstat & EMAC_TXS_LC) 1156 ifp->if_collisions++; 1157 } else 1158 ifp->if_opackets++; 1159 1160 if (ifp->if_flags & IFF_DEBUG) { 1161 if (txstat & EMAC_TXS_ED) 1162 printf("%s: excessive deferral\n", 1163 sc->sc_dev.dv_xname); 1164 if (txstat & EMAC_TXS_EC) 1165 printf("%s: excessive collisions\n", 1166 sc->sc_dev.dv_xname); 1167 } 1168 1169 sc->sc_txfree += txs->txs_ndesc; 1170 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1171 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1172 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1173 m_freem(txs->txs_mbuf); 1174 txs->txs_mbuf = NULL; 1175 } 1176 1177 /* Update the dirty transmit buffer pointer. */ 1178 sc->sc_txsdirty = i; 1179 1180 /* 1181 * If there are no more pending transmissions, cancel the watchdog 1182 * timer. 1183 */ 1184 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1185 ifp->if_timer = 0; 1186 1187 return (0); 1188} 1189 1190/* 1191 * MAL Receive End-Of-Buffer interrupt handler 1192 */ 1193static int 1194emac_rxeob_intr(void *arg) 1195{ 1196 struct emac_softc *sc = arg; 1197 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1198 struct emac_rxsoft *rxs; 1199 struct mbuf *m; 1200 u_int32_t rxstat; 1201 int i, len; 1202 1203 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1204 1205 /* Clear the interrupt */ 1206 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1207 1208 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1209 rxs = &sc->sc_rxsoft[i]; 1210 1211 EMAC_CDRXSYNC(sc, i, 1212 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1213 1214 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1215 1216 if (rxstat & MAL_RX_EMPTY) 1217 /* 1218 * We have processed all of the receive buffers. 1219 */ 1220 break; 1221 1222 /* 1223 * If an error occurred, update stats, clear the status 1224 * word, and leave the packet buffer in place. It will 1225 * simply be reused the next time the ring comes around. 1226 */ 1227 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1228 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1229 EMAC_RXS_IRE)) { 1230#define PRINTERR(bit, str) \ 1231 if (rxstat & (bit)) \ 1232 printf("%s: receive error: %s\n", \ 1233 sc->sc_dev.dv_xname, str) 1234 ifp->if_ierrors++; 1235 PRINTERR(EMAC_RXS_OE, "overrun error"); 1236 PRINTERR(EMAC_RXS_BP, "bad packet"); 1237 PRINTERR(EMAC_RXS_RP, "runt packet"); 1238 PRINTERR(EMAC_RXS_SE, "short event"); 1239 PRINTERR(EMAC_RXS_AE, "alignment error"); 1240 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1241 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1242 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1243 PRINTERR(EMAC_RXS_IRE, "in range error"); 1244#undef PRINTERR 1245 EMAC_INIT_RXDESC(sc, i); 1246 continue; 1247 } 1248 1249 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1250 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1251 1252 /* 1253 * No errors; receive the packet. Note, the 405GP emac 1254 * includes the CRC with every packet. 1255 */ 1256 len = sc->sc_rxdescs[i].md_data_len; 1257 1258 /* 1259 * If the packet is small enough to fit in a 1260 * single header mbuf, allocate one and copy 1261 * the data into it. This greatly reduces 1262 * memory consumption when we receive lots 1263 * of small packets. 1264 * 1265 * Otherwise, we add a new buffer to the receive 1266 * chain. If this fails, we drop the packet and 1267 * recycle the old buffer. 1268 */ 1269 if (emac_copy_small != 0 && len <= MHLEN) { 1270 MGETHDR(m, M_DONTWAIT, MT_DATA); 1271 if (m == NULL) 1272 goto dropit; 1273 memcpy(mtod(m, caddr_t), 1274 mtod(rxs->rxs_mbuf, caddr_t), len); 1275 EMAC_INIT_RXDESC(sc, i); 1276 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1277 rxs->rxs_dmamap->dm_mapsize, 1278 BUS_DMASYNC_PREREAD); 1279 } else { 1280 m = rxs->rxs_mbuf; 1281 if (emac_add_rxbuf(sc, i) != 0) { 1282 dropit: 1283 ifp->if_ierrors++; 1284 EMAC_INIT_RXDESC(sc, i); 1285 bus_dmamap_sync(sc->sc_dmat, 1286 rxs->rxs_dmamap, 0, 1287 rxs->rxs_dmamap->dm_mapsize, 1288 BUS_DMASYNC_PREREAD); 1289 continue; 1290 } 1291 } 1292 1293 ifp->if_ipackets++; 1294 m->m_flags |= M_HASFCS; 1295 m->m_pkthdr.rcvif = ifp; 1296 m->m_pkthdr.len = m->m_len = len; 1297 1298#if NBPFILTER > 0 1299 /* 1300 * Pass this up to any BPF listeners, but only 1301 * pass if up the stack if it's for us. 1302 */ 1303 if (ifp->if_bpf) 1304 bpf_mtap(ifp->if_bpf, m); 1305#endif /* NBPFILTER > 0 */ 1306 1307 /* Pass it on. */ 1308 (*ifp->if_input)(ifp, m); 1309 } 1310 1311 /* Update the receive pointer. */ 1312 sc->sc_rxptr = i; 1313 1314 return (0); 1315} 1316 1317/* 1318 * MAL Transmit Descriptor Error interrupt handler 1319 */ 1320static int 1321emac_txde_intr(void *arg) 1322{ 1323 struct emac_softc *sc = arg; 1324 1325 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1326 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1327 return (0); 1328} 1329 1330/* 1331 * MAL Receive Descriptor Error interrupt handler 1332 */ 1333static int 1334emac_rxde_intr(void *arg) 1335{ 1336 int i; 1337 struct emac_softc *sc = arg; 1338 1339 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1340 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1341 /* 1342 * XXX! 1343 * This is a bit drastic; we just drop all descriptors that aren't 1344 * "clean". We should probably send any that are up the stack. 1345 */ 1346 for (i = 0; i < EMAC_NRXDESC; i++) { 1347 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1348 1349 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1350 EMAC_INIT_RXDESC(sc, i); 1351 } 1352 1353 } 1354 1355 /* Reenable the receive channel */ 1356 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1357 1358 /* Clear the interrupt */ 1359 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1360 1361 return (0); 1362} 1363 1364static uint32_t 1365emac_mii_wait(struct emac_softc *sc) 1366{ 1367 int i; 1368 uint32_t reg; 1369 1370 /* wait for PHY data transfer to complete */ 1371 i = 0; 1372 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1373 delay(7); 1374 if (i++ > 5) { 1375 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1376 return (0); 1377 } 1378 } 1379 return (reg); 1380} 1381 1382static int 1383emac_mii_readreg(struct device *self, int phy, int reg) 1384{ 1385 struct emac_softc *sc = (struct emac_softc *)self; 1386 uint32_t sta_reg; 1387 1388 /* wait for PHY data transfer to complete */ 1389 if (emac_mii_wait(sc) == 0) 1390 return (0); 1391 1392 sta_reg = reg << STACR_PRASHIFT; 1393 sta_reg |= STACR_READ; 1394 sta_reg |= phy << STACR_PCDASHIFT; 1395 1396 sta_reg &= ~STACR_OPBC_MASK; 1397 sta_reg |= STACR_OPBC_50MHZ; 1398 1399 1400 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1401 1402 if ((sta_reg = emac_mii_wait(sc)) == 0) 1403 return (0); 1404 sta_reg = EMAC_READ(sc, EMAC_STACR); 1405 if ((sta_reg & STACR_PHYE) != 0) 1406 return (0); 1407 return (sta_reg >> STACR_PHYDSHIFT); 1408} 1409 1410static void 1411emac_mii_writereg(struct device *self, int phy, int reg, int val) 1412{ 1413 struct emac_softc *sc = (struct emac_softc *)self; 1414 uint32_t sta_reg; 1415 1416 /* wait for PHY data transfer to complete */ 1417 if (emac_mii_wait(sc) == 0) 1418 return; 1419 1420 sta_reg = reg << STACR_PRASHIFT; 1421 sta_reg |= STACR_WRITE; 1422 sta_reg |= phy << STACR_PCDASHIFT; 1423 1424 sta_reg &= ~STACR_OPBC_MASK; 1425 sta_reg |= STACR_OPBC_50MHZ; 1426 1427 sta_reg |= val << STACR_PHYDSHIFT; 1428 1429 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1430 1431 if ((sta_reg = emac_mii_wait(sc)) == 0) 1432 return; 1433 if ((sta_reg & STACR_PHYE) != 0) 1434 /* error */ 1435 return; 1436} 1437 1438static void 1439emac_mii_statchg(struct device *self) 1440{ 1441 struct emac_softc *sc = (void *)self; 1442 1443 if (sc->sc_mii.mii_media_active & IFM_FDX) 1444 sc->sc_mr1 |= MR1_FDE; 1445 else 1446 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1447 1448 /* XXX 802.1x flow-control? */ 1449 1450 /* 1451 * MR1 can only be written immediately after a reset... 1452 */ 1453 emac_reset(sc); 1454} 1455 1456static void 1457emac_mii_tick(void *arg) 1458{ 1459 struct emac_softc *sc = arg; 1460 int s; 1461 1462 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1463 return; 1464 1465 s = splnet(); 1466 mii_tick(&sc->sc_mii); 1467 splx(s); 1468 1469 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1470} 1471 1472/* ifmedia interface function */ 1473static void 1474emac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1475{ 1476 struct emac_softc *sc = ifp->if_softc; 1477 1478 mii_pollstat(&sc->sc_mii); 1479 1480 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1481 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1482} 1483 1484/* ifmedia interface function */ 1485static int 1486emac_mediachange(struct ifnet *ifp) 1487{ 1488 struct emac_softc *sc = ifp->if_softc; 1489 1490 if (ifp->if_flags & IFF_UP) 1491 mii_mediachg(&sc->sc_mii); 1492 return (0); 1493} 1494