1/*	$NetBSD: cpu.h,v 1.58 2024/01/20 00:15:32 thorpej Exp $	*/
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1982, 1990, 1993
6 *	The Regents of the University of California.  All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 *    may be used to endorse or promote products derived from this software
22 *    without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: Utah $Hdr: cpu.h 1.16 91/03/25$
37 *
38 *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
39 */
40
41#ifndef _MACHINE_CPU_H_
42#define _MACHINE_CPU_H_
43
44#if defined(_KERNEL_OPT)
45#include "opt_lockdebug.h"
46#endif
47
48/*
49 * Get common m68k definitions.
50 */
51#include <m68k/cpu.h>
52
53#if defined(_KERNEL)
54/* locore.s functions */
55void	doboot(void) __attribute__((__noreturn__));
56int	nmihand(void *);
57
58extern int iscolor;
59#endif /* _KERNEL */
60
61#define NEXT_RAMBASE  (0x4000000) /* really depends on slot, but... */
62#define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */
63
64#if 0
65/* @@@ this needs to be fixed to work on 030's */
66#define	NEXT_SLOT_ID		0x0
67#ifdef	M68030
68#define	NEXT_SLOT_ID_BMAP	0x0
69#endif	/* M68030 */
70#endif
71#ifdef	M68040
72#ifdef DISABLE_NEXT_BMAP_CHIP		/* @@@ For turbo testing */
73#define	NEXT_SLOT_ID_BMAP	0x0
74#else
75#define	NEXT_SLOT_ID_BMAP	0x00100000
76#endif
77#define NEXT_SLOT_ID		0x0
78#endif	/* M68040 */
79
80/****************************************************************/
81
82/* Eventually, I'd like to move these defines off into
83 * configure somewhere
84 * Darrin B Jewell <jewell@mit.edu>  Thu Feb  5 03:50:58 1998
85 */
86/* ROM */
87#define NEXT_P_EPROM		(NEXT_SLOT_ID+0x00000000)
88#define NEXT_P_EPROM_BMAP	(NEXT_SLOT_ID+0x01000000)
89#define NEXT_P_EPROM_SIZE	(128 * 1024)
90
91/* device space */
92#define NEXT_P_DEV_SPACE	(NEXT_SLOT_ID+0x02000000)
93#define NEXT_P_DEV_BMAP		(NEXT_SLOT_ID+0x02100000)
94#define NEXT_DEV_SPACE_SIZE	0x0001c000
95
96/* DMA control/status (writes MUST be 32-bit) */
97#define NEXT_P_SCSI_CSR		(NEXT_SLOT_ID+0x02000010)
98#define NEXT_P_SOUNDOUT_CSR	(NEXT_SLOT_ID+0x02000040)
99#define NEXT_P_DISK_CSR		(NEXT_SLOT_ID+0x02000050)
100#define NEXT_P_SOUNDIN_CSR	(NEXT_SLOT_ID+0x02000080)
101#define NEXT_P_PRINTER_CSR	(NEXT_SLOT_ID+0x02000090)
102#define NEXT_P_SCC_CSR		(NEXT_SLOT_ID+0x020000c0)
103#define NEXT_P_DSP_CSR		(NEXT_SLOT_ID+0x020000d0)
104#define NEXT_P_ENETX_CSR	(NEXT_SLOT_ID+0x02000110)
105#define NEXT_P_ENETR_CSR	(NEXT_SLOT_ID+0x02000150)
106#define NEXT_P_VIDEO_CSR	(NEXT_SLOT_ID+0x02000180)
107#define NEXT_P_M2R_CSR		(NEXT_SLOT_ID+0x020001d0)
108#define NEXT_P_R2M_CSR		(NEXT_SLOT_ID+0x020001c0)
109
110/* DMA scratch pad (writes MUST be 32-bit) */
111#define NEXT_P_VIDEO_SPAD	(NEXT_SLOT_ID+0x02004180)
112#define NEXT_P_EVENT_SPAD	(NEXT_SLOT_ID+0x0200418c)
113#define NEXT_P_M2M_SPAD		(NEXT_SLOT_ID+0x020041e0)
114
115/* device registers */
116#define NEXT_P_ENET		(NEXT_SLOT_ID_BMAP+0x02006000)
117#define NEXT_P_DSP		(NEXT_SLOT_ID_BMAP+0x02008000)
118#define NEXT_P_MON		(NEXT_SLOT_ID+0x0200e000)
119#define NEXT_P_PRINTER		(NEXT_SLOT_ID+0x0200f000)
120#define NEXT_P_DISK		(NEXT_SLOT_ID_BMAP+0x02012000)
121#define NEXT_P_SCSI		(NEXT_SLOT_ID_BMAP+0x02014000)
122#define NEXT_P_FLOPPY		(NEXT_SLOT_ID_BMAP+0x02014100)
123#define NEXT_P_TIMER		(NEXT_SLOT_ID_BMAP+0x02016000)
124#define NEXT_P_TIMER_CSR	(NEXT_SLOT_ID_BMAP+0x02016004)
125#define NEXT_P_SCC		(NEXT_SLOT_ID_BMAP+0x02018000)
126#define NEXT_P_SCC_CLK		(NEXT_SLOT_ID_BMAP+0x02018004)
127#define NEXT_P_EVENTC		(NEXT_SLOT_ID_BMAP+0x0201a000)
128#define NEXT_P_BMAP		(NEXT_SLOT_ID+0x020c0000)
129/* All COLOR_FB registers are 1 byte wide */
130#define NEXT_P_C16_DAC_0	(NEXT_SLOT_ID_BMAP+0x02018100)	/* COLOR_FB - RAMDAC */
131#define NEXT_P_C16_DAC_1	(NEXT_SLOT_ID_BMAP+0x02018101)
132#define NEXT_P_C16_DAC_2	(NEXT_SLOT_ID_BMAP+0x02018102)
133#define NEXT_P_C16_DAC_3	(NEXT_SLOT_ID_BMAP+0x02018103)
134#define NEXT_P_C16_CMD_REG	(NEXT_SLOT_ID_BMAP+0x02018180)	/* COLOR_FB - CSR */
135
136/* system control registers */
137#define NEXT_P_MEMTIMING	(NEXT_SLOT_ID_BMAP+0x02006010)
138#define NEXT_P_INTRSTAT		(NEXT_SLOT_ID+0x02007000)
139#define NEXT_P_INTRSTAT_CON	0x02007000
140/* #define NEXT_P_INTRSTAT_0	(NEXT_SLOT_ID+0x02008000) */
141#define NEXT_P_INTRMASK		(NEXT_SLOT_ID+0x02007800)
142#define NEXT_P_INTRMASK_CON	0x02007800
143/* #define NEXT_P_INTRMASK_0	(NEXT_SLOT_ID+0x0200a000) */
144#define NEXT_P_SCR1		(NEXT_SLOT_ID+0x0200c000)
145#define NEXT_P_SCR1_CON	0x0200c000
146#define NEXT_P_SID		0x0200c800		/* NOT slot-relative */
147#define NEXT_P_SCR2		(NEXT_SLOT_ID+0x0200d000)
148#define NEXT_P_SCR2_CON	0x0200d000
149#define NEXT_P_RMTINT		(NEXT_SLOT_ID+0x0200d800)
150#define NEXT_P_BRIGHTNESS	(NEXT_SLOT_ID_BMAP+0x02010000)
151#define NEXT_P_DRAM_TIMING	(NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */
152#define NEXT_P_VRAM_TIMING	(NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */
153
154/* memory */
155#define NEXT_P_MAINMEM		(NEXT_SLOT_ID+0x04000000)
156#define NEXT_P_MEMSIZE		0x04000000
157#define NEXT_P_VIDEOMEM		(NEXT_SLOT_ID+0x0b000000)
158#define NEXT_P_VIDEOSIZE	0x0003a800
159#if 0
160#define NEXT_P_C16_VIDEOMEM	(NEXT_SLOT_ID+0x06000000)	/* COLOR_FB */
161#endif
162#define NEXT_P_C16_VIDEOMEM	(0x2c000000)
163#define NEXT_P_C16_VIDEOSIZE	0x001D4000		/* COLOR_FB */
164#define NEXT_P_WF4VIDEO		(NEXT_SLOT_ID+0x0c000000)	/* w A+B-AB function */
165#define NEXT_P_WF3VIDEO		(NEXT_SLOT_ID+0x0d000000)	/* w (1-A)B function */
166#define NEXT_P_WF2VIDEO		(NEXT_SLOT_ID+0x0e000000)	/* w ceil(A+B) function */
167#define NEXT_P_WF1VIDEO		(NEXT_SLOT_ID+0x0f000000)	/* w AB function */
168#define NEXT_P_WF4MEM		(NEXT_SLOT_ID+0x10000000)	/* w A+B-AB function */
169#define NEXT_P_WF3MEM		(NEXT_SLOT_ID+0x14000000)	/* w (1-A)B function */
170#define NEXT_P_WF2MEM		(NEXT_SLOT_ID+0x18000000)	/* w ceil(A+B) function */
171#define NEXT_P_WF1MEM		(NEXT_SLOT_ID+0x1c000000)	/* w AB function */
172#define NEXT_NMWF		4			/* # of memory write funcs */
173
174/*
175 * Interrupt structure.
176 * BASE and BITS define the origin and length of the bit field in the
177 * interrupt status/mask register for the particular interrupt level.
178 * The first component of the interrupt device name indicates the bit
179 * position in the interrupt status and mask registers; the second is the
180 * interrupt level; the third is the bit index relative to the start of the
181 * bit field.
182 */
183#define	NEXT_I(l,i,b)	(((b) << 8) | ((l) << 4) | (i))
184#define	NEXT_I_INDEX(i)	((i) & 0xf)
185#define	NEXT_I_IPL(i)	(((i) >> 4) & 7)
186#define	NEXT_I_BIT(i)	( 1 << (((i) >> 8) & 0x1f))
187
188#define	NEXT_I_IPL7_BASE	0
189#define	NEXT_I_IPL7_BITS	2
190#define	NEXT_I_NMI		NEXT_I(7,0,31)
191#define	NEXT_I_PFAIL		NEXT_I(7,1,30)
192
193#define	NEXT_I_IPL6_BASE	2
194#define	NEXT_I_IPL6_BITS	12
195#define	NEXT_I_TIMER		NEXT_I(6,0,29)
196#define	NEXT_I_ENETX_DMA	NEXT_I(6,1,28)
197#define	NEXT_I_ENETR_DMA	NEXT_I(6,2,27)
198#define	NEXT_I_SCSI_DMA		NEXT_I(6,3,26)
199#define	NEXT_I_DISK_DMA		NEXT_I(6,4,25)
200#define	NEXT_I_PRINTER_DMA	NEXT_I(6,5,24)
201#define	NEXT_I_SOUND_OUT_DMA	NEXT_I(6,6,23)
202#define	NEXT_I_SOUND_IN_DMA	NEXT_I(6,7,22)
203#define	NEXT_I_SCC_DMA		NEXT_I(6,8,21)
204#define	NEXT_I_DSP_DMA		NEXT_I(6,9,20)
205#define	NEXT_I_M2R_DMA		NEXT_I(6,10,19)
206#define	NEXT_I_R2M_DMA		NEXT_I(6,11,18)
207
208#define	NEXT_I_IPL5_BASE	14
209#define	NEXT_I_IPL5_BITS	3
210#define	NEXT_I_SCC		NEXT_I(5,0,17)
211#define	NEXT_I_REMOTE		NEXT_I(5,1,16)
212#define	NEXT_I_BUS		NEXT_I(5,2,15)
213
214#define	NEXT_I_IPL4_BASE	17
215#define	NEXT_I_IPL4_BITS	1
216#define	NEXT_I_DSP_4		NEXT_I(4,0,14)
217
218#define	NEXT_I_IPL3_BASE	18
219#define	NEXT_I_IPL3_BITS	12
220#define	NEXT_I_DISK		NEXT_I(3,0,13)
221#define	NEXT_I_C16_VIDEO	NEXT_I(3,0,13)	/* COLOR_FB - Steals old ESDI interrupt */
222#define	NEXT_I_SCSI		NEXT_I(3,1,12)
223#define	NEXT_I_PRINTER		NEXT_I(3,2,11)
224#define	NEXT_I_ENETX		NEXT_I(3,3,10)
225#define	NEXT_I_ENETR		NEXT_I(3,4,9)
226#define	NEXT_I_SOUND_OVRUN	NEXT_I(3,5,8)
227#define	NEXT_I_PHONE		NEXT_I(3,6,7)
228#define	NEXT_I_DSP_3		NEXT_I(3,7,6)
229#define	NEXT_I_VIDEO		NEXT_I(3,8,5)
230#define	NEXT_I_MONITOR		NEXT_I(3,9,4)
231#define	NEXT_I_KYBD_MOUSE	NEXT_I(3,10,3)
232#define	NEXT_I_POWER		NEXT_I(3,11,2)
233
234#define	NEXT_I_IPL2_BASE	30
235#define	NEXT_I_IPL2_BITS	1
236#define	NEXT_I_SOFTINT1		NEXT_I(2,0,1)
237
238#define	NEXT_I_IPL1_BASE	31
239#define	NEXT_I_IPL1_BITS	1
240#define	NEXT_I_SOFTINT0		NEXT_I(1,0,0)
241
242/****************************************************************/
243
244/* physical memory sections */
245#if 0
246#define	ROMBASE		(0x00000000)
247#endif
248
249#define	INTIOBASE	(0x02000000)
250#define	INTIOTOP	(0x02120000)
251#define MONOBASE	(0x0b000000)
252#define MONOTOP		(0x0b03a800)
253#define COLORBASE	(0x2c000000)
254#define COLORTOP	(0x2c1d4000)
255#define TURBOFBBASE	(0x0c000000)
256#define TURBOMONOTOP	(0x0c03a800)
257#define TURBOCOLORTOP	(0x0c1d4000)
258
259#define NEXT_INTR_BITS \
260"\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0"
261
262/*
263 * Internal IO space:
264 *
265 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
266 *
267 * Internal IO space is mapped in the kernel from ``intiobase'' to
268 * ``intiolimit'' (defined in locore.s).  Since it is always mapped,
269 * conversion between physical and kernel virtual addresses is easy.
270 */
271#define	IIOV(pa)	((int)(pa)-INTIOBASE+intiobase)
272#define	IIOP(va)	((int)(va)-intiobase+INTIOBASE)
273#define	IIOMAPSIZE	btoc(INTIOTOP-INTIOBASE)	/* 2mb */
274
275#endif	/* _MACHINE_CPU_H_ */
276