adrsmap.h revision 1.5
1/* $NetBSD: adrsmap.h,v 1.5 2000/10/12 03:07:02 onoe Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY 39 * 40 * @(#)adrsmap.h 8.1 (Berkeley) 6/11/93 41 */ 42 43/* 44 * adrsmap.h 45 * 46 * Define all hardware address map. 47 */ 48 49#ifndef __MACHINE_ADRSMAP__ 50#define __MACHINE_ADRSMAP__ 51 52/*---------------------------------------------------------------------- 53 * news3400 54 *----------------------------------------------------------------------*/ 55/* 56 * timer 57 */ 58#define RTC_PORT 0xbff407f8 59#define DATA_PORT 0xbff407f9 60 61#ifdef notdef 62#define EN_ITIMER 0xb8000004 /*XXX:???*/ 63#endif 64 65#define INTEN0 0xbfc80000 66#define INTEN0_PERR 0x80 67#define INTEN0_ABORT 0x40 68#define INTEN0_BERR 0x20 69#define INTEN0_TIMINT 0x10 70#define INTEN0_KBDINT 0x08 71#define INTEN0_MSINT 0x04 72#define INTEN0_CFLT 0x02 73#define INTEN0_CBSY 0x01 74 75#define INTEN1 0xbfc80001 76#define INTEN1_BEEP 0x80 77#define INTEN1_SCC 0x40 78#define INTEN1_LANCE 0x20 79#define INTEN1_DMA 0x10 80#define INTEN1_SLOT1 0x08 81#define INTEN1_SLOT3 0x04 82#define INTEN1_EXT1 0x02 83#define INTEN1_EXT3 0x01 84 85#define INTST0 0xbfc80002 86#define INTST0_PERR 0x80 87#define INTST0_ABORT 0x40 88#define INTST0_BERR 0x00 /* N/A */ 89#define INTST0_TIMINT 0x10 90#define INTST0_KBDINT 0x08 91#define INTST0_MSINT 0x04 92#define INTST0_CFLT 0x02 93#define INTST0_CBSY 0x01 94#define INTST0_PERR_BIT 7 95#define INTST0_ABORT_BIT 6 96#define INTST0_BERR_BIT 5 /* N/A */ 97#define INTST0_TIMINT_BIT 4 98#define INTST0_KBDINT_BIT 3 99#define INTST0_MSINT_BIT 2 100#define INTST0_CFLT_BIT 1 101#define INTST0_CBSY_BIT 0 102 103#define INTST1 0xbfc80003 104#define INTST1_BEEP 0x80 105#define INTST1_SCC 0x40 106#define INTST1_LANCE 0x20 107#define INTST1_DMA 0x10 108#define INTST1_SLOT1 0x08 109#define INTST1_SLOT3 0x04 110#define INTST1_EXT1 0x02 111#define INTST1_EXT3 0x01 112#define INTST1_BEEP_BIT 7 113#define INTST1_SCC_BIT 6 114#define INTST1_LANCE_BIT 5 115#define INTST1_DMA_BIT 4 116#define INTST1_SLOT1_BIT 3 117#define INTST1_SLOT3_BIT 2 118#define INTST1_EXT1_BIT 1 119#define INTST1_EXT3_BIT 0 120 121#define INTCLR0 0xbfc80004 122#define INTCLR0_PERR 0x80 123#define INTCLR0_ABORT 0x40 124#define INTCLR0_BERR 0x20 125#define INTCLR0_TIMINT 0x10 126#define INTCLR0_KBDINT 0x00 /* N/A */ 127#define INTCLR0_MSINT 0x00 /* N/A */ 128#define INTCLR0_CFLT 0x02 129#define INTCLR0_CBSY 0x01 130 131#define INTCLR1 0xbfc80005 132#define INTCLR1_BEEP 0x80 133#define INTCLR1_SCC 0x00 /* N/A */ 134#define INTCLR1_LANCE 0x00 /* N/A */ 135#define INTCLR1_DMA 0x00 /* N/A */ 136#define INTCLR1_SLOT1 0x00 /* N/A */ 137#define INTCLR1_SLOT3 0x00 /* N/A */ 138#define INTCLR1_EXT1 0x00 /* N/A */ 139#define INTCLR1_EXT3 0x00 /* N/A */ 140 141#define ITIMER 0xbfc80006 142#define IOCLOCK 4915200 143 144#define DIP_SWITCH 0xbfe40000 145#define IDROM 0xbfe80000 146 147#define DEBUG_PORT 0xbfcc0003 148#define DP_READ 0x00 149#define DP_WRITE 0xf0 150#define DP_LED0 0x01 151#define DP_LED1 0x02 152#define DP_LED2 0x04 153#define DP_LED3 0x08 154 155 156#define LANCE_PORT 0xbff80000 157#define LANCE_MEMORY 0xbffc0000 158#define ETHER_ID IDROM_PORT 159 160#define LANCE_PORT1 0xb8c30000 /* expansion lance #1 */ 161#define LANCE_MEMORY1 0xb8c20000 162#define ETHER_ID1 0xb8c38000 163 164#define LANCE_PORT2 0xb8c70000 /* expansion lance #2 */ 165#define LANCE_MEMORY2 0xb8c60000 166#define ETHER_ID2 0xb8c78000 167 168#define IDROM_PORT 0xbfe80000 169 170#define SCCPORT0B 0xbfec0000 171#define SCCPORT0A 0xbfec0002 172#define SCCPORT1B 0xb8c40100 173#define SCCPORT1A 0xb8c40102 174#define SCCPORT2B 0xb8c40104 175#define SCCPORT2A 0xb8c40106 176#define SCCPORT3B 0xb8c40110 177#define SCCPORT3A 0xb8c40112 178#define SCCPORT4B 0xb8c40114 179#define SCCPORT4A 0xb8c40116 180 181#define SCC_STATUS0 0xbfcc0002 182#define SCC_STATUS1 0xb8c40108 183#define SCC_STATUS2 0xb8c40118 184 185#define SCCVECT (0x1fcc0007 | MIPS_KSEG1_START) 186#define SCC_RECV 2 187#define SCC_XMIT 0 188#define SCC_CTRL 3 189#define SCC_STAT 1 190#define SCC_INT_MASK 0x6 191 192/*XXX: SHOULD BE FIX*/ 193#define KEYB_DATA 0xbfd00000 /* keyboard data port */ 194#define KEYB_STAT 0xbfd00001 /* keyboard status port */ 195#define KEYB_INTE INTEN0 /* keyboard interrupt enable */ 196#define KEYB_RESET 0xbfd00002 /* keyboard reset port*/ 197#define KEYB_INIT1 0xbfd00003 /* keyboard speed */ 198#define KEYB_INIT2 KEYB_INIT1 /* keyboard clock */ 199#define KEYB_BUZZ 0xbfd40001 /* keyboard buzzer (length) */ 200#define KEYB_BUZZF 0xbfd40000 /* keyboard buzzer frequency */ 201#define MOUSE_DATA 0xbfd00004 /* mouse data port */ 202#define MOUSE_STAT 0xbfd00005 /* mouse status port */ 203#define MOUSE_INTE INTEN0 /* mouse interrupt enable */ 204#define MOUSE_RESET 0xbfd00006 /* mouse reset port */ 205#define MOUSE_INIT1 0xbfd00007 /* mouse speed */ 206#define MOUSE_INIT2 MOUSE_INIT1 /* mouse clock */ 207 208#define RX_MSINTE 0x04 /* Mouse Interrupt Enable */ 209#define RX_KBINTE 0x08 /* Keyboard Intr. Enable */ 210#define RX_MSINT 0x04 /* Mouse Interrupted */ 211#define RX_KBINT 0x08 /* Keyboard Interrupted */ 212#define RX_MSBUF 0x01 /* Mouse data buffer Full */ 213#define RX_KBBUF 0x01 /* Keyboard data Full */ 214#define RX_MSRDY 0x02 /* Mouse data ready */ 215#define RX_KBRDY 0x02 /* Keyboard data ready */ 216/*XXX: SHOULD BE FIX*/ 217 218#define ABEINT_BADDR 0xbfdc0038 219 220#define NEWS5000_DIP_SWITCH 0xbf3d0000 221#define NEWS5000_IDROM 0xbf3c0000 222 223#define NEWS5000_TIMER0 0xbf800000 224#define NEWS5000_FREERUN 0xbf840000 225#define NEWS5000_NVRAM 0xbf880000 226#define NEWS5000_NVRAM_SIZE 0x07f8 227#define NEWS5000_RTC_PORT 0xbf881fe0 228 229#define NEWS5000_INTCLR0 0xbf4e0000 230#define NEWS5000_INTCLR1 0xbf4e0004 231#define NEWS5000_INTCLR2 0xbf4e0008 232#define NEWS5000_INTCLR3 0xbf4e000c 233#define NEWS5000_INTCLR4 0xbf4e0010 234#define NEWS5000_INTCLR5 0xbf4e0014 235 236#define NEWS5000_INTEN0 0xbfa00000 237#define NEWS5000_INTEN1 0xbfa00004 238#define NEWS5000_INTEN2 0xbfa00008 239#define NEWS5000_INTEN3 0xbfa0000c 240#define NEWS5000_INTEN4 0xbfa00010 241#define NEWS5000_INTEN5 0xbfa00014 242 243#define NEWS5000_INTST0 0xbfa00020 244#define NEWS5000_INTST1 0xbfa00024 245#define NEWS5000_INTST2 0xbfa00028 246#define NEWS5000_INTST3 0xbfa0002c 247#define NEWS5000_INTST4 0xbfa00030 248#define NEWS5000_INTST5 0xbfa00034 249 250/* 251 * level0 intr (INTMASK0/INTSTAT0) 252 */ 253#define NEWS5000_INT0_DMAC 0x01 254#define NEWS5000_INT0_SONIC 0x02 255#define NEWS5000_INT0_FDC 0x10 256 257/* 258 * level1 intr (INTMASK1/INTSTAT1) 259 */ 260#define NEWS5000_INT1_KBD 0x01 261#define NEWS5000_INT1_SCC 0x02 262#define NEWS5000_INT1_AUDIO0 0x04 263#define NEWS5000_INT1_AUDIO1 0x08 264#define NEWS5000_INT1_PARALLEL 0x20 265#define NEWS5000_INT1_FB 0x80 266 267/* 268 * level2 intr (INTMASK2/INTSTAT2) 269 */ 270#define NEWS5000_INT2_TIMER0 0x01 271#define NEWS5000_INT2_TIMER1 0x02 272 273/* 274 * level4 intr (INTMASK4/INTSTAT4) 275 */ 276#define NEWS5000_INT4_APBUS 0x01 277 278#define NEWS5000_WBFLUSH 0xbf520004 279 280#define NEWS5000_LED_POWER 0xbf3f0000 281#define NEWS5000_LED_DISK 0xbf3f0004 282#define NEWS5000_LED_FLOPPY 0xbf3f0008 283#define NEWS5000_LED_SEC 0xbf3f000c 284#define NEWS5000_LED_NET 0xbf3f0010 285#define NEWS5000_LED_CD 0xbf3f0014 286 287#define NEWS5000_APBUS_INTMSK 0xb4c0000c /* interrupt mask */ 288#define NEWS5000_APBUS_INT_DMAADDR 0x0100 289#define NEWS5000_APBUS_INT_RDTIMEO 0x0004 290#define NEWS5000_APBUS_INT_WRTIMEO 0x0001 291#define NEWS5000_APBUS_INTST 0xb4c00014 /* interrupt status */ 292#define NEWS5000_APBUS_BER_A 0xb4c0001c /* Bus error address */ 293#define NEWS5000_APBUS_CTRL 0xb4c00034 /* configuration control */ 294#define NEWS5000_APBUS_DER_A 0xb400005c /* DMA error address */ 295#define NEWS5000_APBUS_DER_S 0xb4c0006c /* DMA error slot */ 296#define NEWS5000_APBUS_DMA 0xb4c00084 /* unmapped DMA coherency */ 297 298#define NEWS5000_SCCPORT0A 0xbe950000 299 300#endif /* !__MACHINE_ADRSMAP__ */ 301