1/*	$NetBSD: dmac3reg.h,v 1.2 2008/04/09 15:40:30 tsutsui Exp $	*/
2
3/*-
4 * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 *    derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29struct dmac3reg {
30	volatile uint32_t csr;
31	volatile uint32_t intr;
32	volatile uint32_t len;
33	volatile uint32_t addr;
34	volatile uint32_t conf;
35};
36
37#define DMAC3_CSR_DBURST	0x0020
38#define DMAC3_CSR_MBURST	0x0010
39#define DMAC3_CSR_APAD		0x0008
40#define DMAC3_CSR_RESET		0x0004
41#define DMAC3_CSR_RECV		0x0002
42#define DMAC3_CSR_SEND		0x0000
43#define DMAC3_CSR_ENABLE	0x0001
44
45#define DMAC3_INTR_PERR		0x8000
46#define DMAC3_INTR_DRQI		0x4000
47#define DMAC3_INTR_DRQIE	0x2000
48#define DMAC3_INTR_DREQ		0x1000
49#define DMAC3_INTR_EOPI		0x0400
50#define DMAC3_INTR_EOPIE	0x0200
51#define DMAC3_INTR_EOP		0x0100
52#define DMAC3_INTR_TCI		0x0040
53#define DMAC3_INTR_TCIE		0x0020
54#define DMAC3_INTR_INTEN	0x0002
55#define DMAC3_INTR_INT		0x0001
56
57#define DMAC3_CONF_IPER		0x8000
58#define DMAC3_CONF_MPER		0x4000
59#define DMAC3_CONF_PCEN		0x2000
60#define DMAC3_CONF_DERR		0x1000
61#define DMAC3_CONF_DCEN		0x0800
62#define DMAC3_CONF_ODDP		0x0200
63#define DMAC3_CONF_WIDTH	0x00ff
64#define DMAC3_CONF_SLOWACCESS	0x0020
65#define DMAC3_CONF_FASTACCESS	0x0001
66
67
68#define DMAC3_PAGEMAP	0xb4c20000
69#define DMAC3_MAPSIZE	0x20000
70
71struct dma_pte {
72	uint32_t pad1;
73	uint32_t valid:1,
74	      coherent:1,	/* ? */
75	      pad2:10,		/* ? */
76	      pfnum:20;
77};
78