1/*	$NetBSD: zs.c,v 1.46 2024/01/18 05:12:29 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 *
38 * Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej@NetBSD.org>
39 */
40
41#include <sys/cdefs.h>
42__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.46 2024/01/18 05:12:29 thorpej Exp $");
43
44#include "opt_mvmeconf.h"
45
46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/conf.h>
49#include <sys/device.h>
50#include <sys/file.h>
51#include <sys/ioctl.h>
52#include <sys/kernel.h>
53#include <sys/proc.h>
54#include <sys/tty.h>
55#include <sys/time.h>
56#include <sys/syslog.h>
57#include <sys/cpu.h>
58#include <sys/bus.h>
59#include <sys/intr.h>
60
61#include <dev/cons.h>
62#include <dev/ic/z8530reg.h>
63#include <machine/z8530var.h>
64
65#include <mvme68k/dev/zsvar.h>
66
67#include "ioconf.h"
68
69/*
70 * Some warts needed by z8530tty.c -
71 * The default parity REALLY needs to be the same as the PROM uses,
72 * or you can not see messages done with printf during boot-up...
73 */
74int zs_def_cflag = (CREAD | CS8 | HUPCL);
75
76/* Flags from zscnprobe() */
77static int zs_hwflags[NZSC][2];
78
79/* Default speed for each channel */
80static int zs_defspeed[NZSC][2] = {
81	{ 9600, 	/* port 1 */
82	  9600 },	/* port 2 */
83	{ 9600, 	/* port 3 */
84	  9600 },	/* port 4 */
85};
86
87static struct zs_chanstate zs_conschan_store;
88static struct zs_chanstate *zs_conschan;
89
90uint8_t zs_init_reg[16] = {
91	0,	/* 0: CMD (reset, etc.) */
92	0,	/* 1: No interrupts yet. */
93	0x18 + ZSHARD_PRI,	/* IVECT */
94	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
95	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
96	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
97	0,	/* 6: TXSYNC/SYNCLO */
98	0,	/* 7: RXSYNC/SYNCHI */
99	0,	/* 8: alias for data port */
100	ZSWR9_MASTER_IE,
101	0,	/*10: Misc. TX/RX control bits */
102	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
103	0,			/*12: BAUDLO (default=9600) */
104	0,			/*13: BAUDHI (default=9600) */
105	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
106	ZSWR15_BREAK_IE,
107};
108
109
110/****************************************************************
111 * Autoconfig
112 ****************************************************************/
113
114/* Definition of the driver for autoconfig. */
115static int	zsc_print(void *, const char *name);
116int	zs_getc(void *);
117void	zs_putc(void *, int);
118
119#if 0
120static int zs_get_speed(struct zs_chanstate *);
121#endif
122
123cons_decl(zsc_pcc);
124
125
126/*
127 * Configure children of an SCC.
128 */
129void
130zs_config(struct zsc_softc *zsc, struct zsdevice *zs, int vector, int pclk)
131{
132	struct zsc_attach_args zsc_args;
133	volatile struct zschan *zc;
134	struct zs_chanstate *cs;
135	int zsc_unit, channel, s;
136
137	zsc_unit = device_unit(zsc->zsc_dev);
138	printf(": Zilog 8530 SCC at vector 0x%x\n", vector);
139
140	/*
141	 * Initialize software state for each channel.
142	 */
143	for (channel = 0; channel < 2; channel++) {
144		zsc_args.channel = channel;
145		zsc_args.hwflags = zs_hwflags[zsc_unit][channel];
146		cs = &zsc->zsc_cs_store[channel];
147		zsc->zsc_cs[channel] = cs;
148
149		/*
150		 * If we're the console, copy the channel state, and
151		 * adjust the console channel pointer.
152		 */
153		if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
154			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
155			zs_conschan = cs;
156		} else {
157			zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
158			cs->cs_reg_csr  = zc->zc_csr;
159			cs->cs_reg_data = zc->zc_data;
160			memcpy(cs->cs_creg, zs_init_reg, 16);
161			memcpy(cs->cs_preg, zs_init_reg, 16);
162			cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
163		}
164
165		zs_lock_init(cs);
166		cs->cs_brg_clk = pclk / 16;
167		cs->cs_creg[2] = cs->cs_preg[2] = vector;
168		zs_set_speed(cs, cs->cs_defspeed);
169		cs->cs_creg[12] = cs->cs_preg[12];
170		cs->cs_creg[13] = cs->cs_preg[13];
171		cs->cs_defcflag = zs_def_cflag;
172
173		/* Make these correspond to cs_defcflag (-crtscts) */
174		cs->cs_rr0_dcd = ZSRR0_DCD;
175		cs->cs_rr0_cts = 0;
176		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
177		cs->cs_wr5_rts = 0;
178
179		cs->cs_channel = channel;
180		cs->cs_private = NULL;
181		cs->cs_ops = &zsops_null;
182
183		/*
184		 * Clear the master interrupt enable.
185		 * The INTENA is common to both channels,
186		 * so just do it on the A channel.
187		 * Write the interrupt vector while we're at it.
188		 */
189		if (channel == 0) {
190			zs_write_reg(cs, 9, 0);
191			zs_write_reg(cs, 2, vector);
192		}
193
194		/*
195		 * Look for a child driver for this channel.
196		 * The child attach will setup the hardware.
197		 */
198		if (!config_found(zsc->zsc_dev, (void *)&zsc_args,
199		    zsc_print, CFARGS_NONE)) {
200			/* No sub-driver.  Just reset it. */
201			uint8_t reset = (channel == 0) ?
202				ZSWR9_A_RESET : ZSWR9_B_RESET;
203			s = splzs();
204			zs_write_reg(cs,  9, reset);
205			splx(s);
206		}
207	}
208
209	/*
210	 * Allocate a software interrupt cookie.
211	 */
212	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
213	    (void (*)(void *)) zsc_intr_soft, zsc);
214#ifdef DEBUG
215	assert(zsc->zsc_softintr_cookie);
216#endif
217}
218
219static int
220zsc_print(void *aux, const char *name)
221{
222	struct zsc_attach_args *args = aux;
223
224	if (name != NULL)
225		aprint_normal("%s: ", name);
226
227	if (args->channel != -1)
228		aprint_normal(" channel %d", args->channel);
229
230	return UNCONF;
231}
232
233#if defined(MVME162) || defined(MVME172)
234/*
235 * Our ZS chips each have their own interrupt vector.
236 */
237int
238zshard_unshared(void *arg)
239{
240	struct zsc_softc *zsc = arg;
241	int rval;
242
243	rval = zsc_intr_hard(zsc);
244
245	if (rval) {
246		if ((zsc->zsc_cs[0]->cs_softreq) ||
247		    (zsc->zsc_cs[1]->cs_softreq))
248			softint_schedule(zsc->zsc_softintr_cookie);
249		zsc->zsc_evcnt.ev_count++;
250	}
251
252	return rval;
253}
254#endif
255
256#ifdef MVME147
257/*
258 * Our ZS chips all share a common, PCC-vectored interrupt,
259 * so we have to look at all of them on each interrupt.
260 */
261int
262zshard_shared(void *arg)
263{
264	struct zsc_softc *zsc;
265	int unit, rval;
266
267	rval = 0;
268	for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
269		zsc = device_lookup_private(&zsc_cd, unit);
270		if (zsc != NULL && zsc_intr_hard(zsc)) {
271			if ((zsc->zsc_cs[0]->cs_softreq) ||
272			    (zsc->zsc_cs[1]->cs_softreq))
273				softint_schedule(zsc->zsc_softintr_cookie);
274			zsc->zsc_evcnt.ev_count++;
275			rval++;
276		}
277	}
278	return rval;
279}
280#endif
281
282
283#if 0
284/*
285 * Compute the current baud rate given a ZSCC channel.
286 */
287static int
288zs_get_speed(struct zs_chanstate *cs)
289{
290	int tconst;
291
292	tconst = zs_read_reg(cs, 12);
293	tconst |= zs_read_reg(cs, 13) << 8;
294	return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
295}
296#endif
297
298/*
299 * MD functions for setting the baud rate and control modes.
300 */
301int
302zs_set_speed(struct zs_chanstate *cs, int bps)
303{
304	int tconst, real_bps;
305
306	if (bps == 0)
307		return 0;
308
309#ifdef	DIAGNOSTIC
310	if (cs->cs_brg_clk == 0)
311		panic("zs_set_speed");
312#endif
313
314	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
315	if (tconst < 0)
316		return EINVAL;
317
318	/* Convert back to make sure we can do it. */
319	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
320
321	/* Allow 2% tolerance WRT the required bps */
322	if (((abs(real_bps - bps) * 1000) / bps) > 20)
323		return EINVAL;
324
325	cs->cs_preg[12] = tconst;
326	cs->cs_preg[13] = tconst >> 8;
327
328	/* Caller will stuff the pending registers. */
329	return 0;
330}
331
332int
333zs_set_modes(struct zs_chanstate *cs, int cflag)
334{
335	int s;
336
337	/*
338	 * Output hardware flow control on the chip is horrendous:
339	 * if carrier detect drops, the receiver is disabled, and if
340	 * CTS drops, the transmitter is stopped IN MID CHARACTER!
341	 * Therefore, NEVER set the HFC bit, and instead use the
342	 * status interrupt to detect CTS changes.
343	 */
344	s = splzs();
345	cs->cs_rr0_pps = 0;
346	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
347		cs->cs_rr0_dcd = 0;
348		if ((cflag & MDMBUF) == 0)
349			cs->cs_rr0_pps = ZSRR0_DCD;
350	} else
351		cs->cs_rr0_dcd = ZSRR0_DCD;
352	if ((cflag & CRTSCTS) != 0) {
353		cs->cs_wr5_dtr = ZSWR5_DTR;
354		cs->cs_wr5_rts = ZSWR5_RTS;
355		cs->cs_rr0_cts = ZSRR0_CTS;
356	} else if ((cflag & MDMBUF) != 0) {
357		cs->cs_wr5_dtr = 0;
358		cs->cs_wr5_rts = ZSWR5_DTR;
359		cs->cs_rr0_cts = ZSRR0_DCD;
360	} else {
361		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
362		cs->cs_wr5_rts = 0;
363		cs->cs_rr0_cts = 0;
364	}
365	splx(s);
366
367	/* Caller will stuff the pending registers. */
368	return 0;
369}
370
371
372/*
373 * Read or write the chip with suitable delays.
374 */
375
376uint8_t
377zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
378{
379	uint8_t val;
380
381	*cs->cs_reg_csr = reg;
382	ZS_DELAY();
383	val = *cs->cs_reg_csr;
384	ZS_DELAY();
385	return val;
386}
387
388void
389zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
390{
391
392	*cs->cs_reg_csr = reg;
393	ZS_DELAY();
394	*cs->cs_reg_csr = val;
395	ZS_DELAY();
396}
397
398uint8_t
399zs_read_csr(struct zs_chanstate *cs)
400{
401	uint8_t val;
402
403	val = *cs->cs_reg_csr;
404	ZS_DELAY();
405	return val;
406}
407
408void
409zs_write_csr(struct zs_chanstate *cs, uint8_t val)
410{
411
412	*cs->cs_reg_csr = val;
413	ZS_DELAY();
414}
415
416uint8_t
417zs_read_data(struct zs_chanstate *cs)
418{
419	uint8_t val;
420
421	val = *cs->cs_reg_data;
422	ZS_DELAY();
423	return val;
424}
425
426void
427zs_write_data(struct zs_chanstate *cs, uint8_t val)
428{
429
430	*cs->cs_reg_data = val;
431	ZS_DELAY();
432}
433
434/****************************************************************
435 * Console support functions (MVME specific!)
436 ****************************************************************/
437
438/*
439 * Polled input char.
440 */
441int
442zs_getc(void *arg)
443{
444	struct zs_chanstate *cs = arg;
445	int s, c, rr0, stat;
446
447	s = splhigh();
448 top:
449	/* Wait for a character to arrive. */
450	do {
451		rr0 = *cs->cs_reg_csr;
452		ZS_DELAY();
453	} while ((rr0 & ZSRR0_RX_READY) == 0);
454
455	/* Read error register. */
456	stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE);
457	if (stat) {
458		zs_write_csr(cs, ZSM_RESET_ERR);
459		goto top;
460	}
461
462	/* Read character. */
463	c = *cs->cs_reg_data;
464	ZS_DELAY();
465	splx(s);
466
467	return c;
468}
469
470/*
471 * Polled output char.
472 */
473void
474zs_putc(void *arg, int c)
475{
476	struct zs_chanstate *cs = arg;
477	int s, rr0;
478
479	s = splhigh();
480	/* Wait for transmitter to become ready. */
481	do {
482		rr0 = *cs->cs_reg_csr;
483		ZS_DELAY();
484	} while ((rr0 & ZSRR0_TX_READY) == 0);
485
486	*cs->cs_reg_data = c;
487	ZS_DELAY();
488	splx(s);
489}
490
491/*
492 * Common parts of console init.
493 */
494void
495zs_cnconfig(int zsc_unit, int channel, struct zsdevice *zs, int pclk)
496{
497	struct zs_chanstate *cs;
498	struct zschan *zc;
499
500	zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
501
502	/*
503	 * Pointer to channel state.  Later, the console channel
504	 * state is copied into the softc, and the console channel
505	 * pointer adjusted to point to the new copy.
506	 */
507	zs_conschan = cs = &zs_conschan_store;
508	zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE;
509
510	/* Setup temporary chanstate. */
511	cs->cs_brg_clk = pclk / 16;
512	cs->cs_reg_csr  = zc->zc_csr;
513	cs->cs_reg_data = zc->zc_data;
514
515	/* Initialize the pending registers. */
516	memcpy(cs->cs_preg, zs_init_reg, 16);
517	cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS);
518
519#if 0
520	/* XXX: Preserve BAUD rate from boot loader. */
521	/* XXX: Also, why reset the chip here? -gwr */
522	cs->cs_defspeed = zs_get_speed(cs);
523#else
524	cs->cs_defspeed = 9600;	/* XXX */
525#endif
526	zs_set_speed(cs, cs->cs_defspeed);
527	cs->cs_creg[12] = cs->cs_preg[12];
528	cs->cs_creg[13] = cs->cs_preg[13];
529
530	/* Clear the master interrupt enable. */
531	zs_write_reg(cs, 9, 0);
532
533	/* Reset the whole SCC chip. */
534	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
535
536	/* Copy "pending" to "current" and H/W. */
537	zs_loadchannelregs(cs);
538}
539
540/*
541 * Polled console input putchar.
542 */
543int
544zsc_pcccngetc(dev_t dev)
545{
546	struct zs_chanstate *cs = zs_conschan;
547	int c;
548
549	c = zs_getc(cs);
550	return c;
551}
552
553/*
554 * Polled console output putchar.
555 */
556void
557zsc_pcccnputc(dev_t dev, int c)
558{
559	struct zs_chanstate *cs = zs_conschan;
560
561	zs_putc(cs, c);
562}
563
564/*
565 * Handle user request to enter kernel debugger.
566 */
567void
568zs_abort(struct zs_chanstate *cs)
569{
570	int rr0;
571
572	/* Wait for end of break to avoid PROM abort. */
573	/* XXX - Limit the wait? */
574	do {
575		rr0 = *cs->cs_reg_csr;
576		ZS_DELAY();
577	} while (rr0 & ZSRR0_BREAK);
578
579	mvme68k_abort("SERIAL LINE ABORT");
580}
581