1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * PCI constants File: sb1250_pci.h 5 * 6 * This module contains constants and macros to describe 7 * the PCI interface on the SB1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49#ifndef _SB1250_PCI_H 50#define _SB1250_PCI_H 51 52#include "sb1250_defs.h" 53 54#define K_PCI_VENDOR_SIBYTE 0x166D 55#define K_PCI_DEVICE_SB1250 0x0001 56 57/* 58 * PCI Interface Type 0 configuration header 59 */ 60 61#define R_PCI_TYPE0_DEVICEID 0x0000 62#define R_PCI_TYPE0_CMDSTATUS 0x0004 63#define R_PCI_TYPE0_CLASSREV 0x0008 64#define R_PCI_TYPE0_DEVHDR 0x000C 65#define R_PCI_TYPE0_BAR0 0x0010 /* translated via mapping table */ 66#define R_PCI_TYPE0_BAR1 0x0014 /* reserved */ 67#define R_PCI_TYPE0_BAR2 0x0018 /* mbox 0 */ 68#define R_PCI_TYPE0_BAR3 0x001C /* mbox 1 */ 69#define R_PCI_TYPE0_BAR4 0x0020 /* low memory */ 70#define R_PCI_TYPE0_BAR5 0x0024 /* high memory */ 71#define R_PCI_TYPE0_CARDBUSCIS 0x0028 72#define R_PCI_TYPE0_SUBSYSID 0x002C 73#define R_PCI_TYPE0_ROMBASE 0x0030 74#define R_PCI_TYPE0_CAPPTR 0x0034 /* not used */ 75#define R_PCI_TYPE0_RESERVED1 0x0038 76#define R_PCI_TYPE0_INTGRANT 0x003C /* interrupt pin and grant latency */ 77#define R_PCI_TYPE0_TIMEOUT 0x0040 /* FControl, Timeout */ 78#define R_PCI_TYPE0_FCONTROL 0x0040 /* FControl, Timeout */ 79#define R_PCI_TYPE0_MAPBASE 0x0044 /* 0x44 through 0x80 - map table */ 80#define PCI_TYPE0_MAPENTRIES 32 /* 64 bytes, 32 entries */ 81#define R_PCI_TYPE0_ERRORADDR 0x0084 82#define R_PCI_TYPE0_ADDSTATUS 0x0088 83#define R_PCI_TYPE0_SUBSYSSET 0x008C /* only accessible from ZBBus */ 84#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 85#define R_PCI_TYPE0_READHOST 0x0094 /* Read Host register */ 86#define R_PCI_TYPE0_ADXTEND 0x0098 /* Adaptive Extend register */ 87#endif /* 1250 PASS2 || 112x PASS1 */ 88 89/* 90 * PCI Device ID register 91 */ 92 93#define S_PCI_DEVICEID_VENDOR 0 94#define M_PCI_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_PCI_DEVICEID_VENDOR) 95#define V_PCI_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_VENDOR) 96#define G_PCI_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_PCI_DEVICEID_VENDOR,M_PCI_DEVICEID_VENDOR) 97 98#define S_PCI_DEVICEID_DEVICEID 16 99#define M_PCI_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_PCI_DEVICEID_DEVICEID) 100#define V_PCI_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_DEVICEID) 101#define G_PCI_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_PCI_DEVICEID_DEVICEID,M_PCI_DEVICEID_DEVICEID) 102 103 104/* 105 * PCI Command Register (Table 8-4) 106 */ 107 108#define M_PCI_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) 109#define M_PCI_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) 110#define M_PCI_CMD_MASTER_EN _SB_MAKEMASK1_32(2) 111#define M_PCI_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) 112#define M_PCI_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) 113#define M_PCI_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) 114#define M_PCI_CMD_PARERRRESP _SB_MAKEMASK1_32(6) 115#define M_PCI_CMD_STEPCTRL _SB_MAKEMASK1_32(7) 116#define M_PCI_CMD_SERR_EN _SB_MAKEMASK1_32(8) 117#define M_PCI_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) 118 119/* 120 * PCI class and revision registers 121 */ 122 123#define S_PCI_CLASSREV_REV 0 124#define M_PCI_CLASSREV_REV _SB_MAKEMASK_32(8,S_PCI_CLASSREV_REV) 125#define V_PCI_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_REV) 126#define G_PCI_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_PCI_CLASSREV_REV,M_PCI_CLASSREV_REV) 127 128#define S_PCI_CLASSREV_CLASS 8 129#define M_PCI_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_PCI_CLASSREV_CLASS) 130#define V_PCI_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_CLASS) 131#define G_PCI_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS) 132 133#define K_PCI_REV 0x01 134#define K_PCI_CLASS 0x060000 135 136/* 137 * Device Header (offset 0x0C) 138 */ 139 140#define S_PCI_DEVHDR_CLINESZ 0 141#define M_PCI_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ) 142#define V_PCI_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ) 143#define G_PCI_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ) 144 145#define S_PCI_DEVHDR_LATTMR 8 146#define M_PCI_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTMR) 147#define V_PCI_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTMR) 148#define G_PCI_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTMR,M_PCI_DEVHDR_LATTMR) 149 150#define S_PCI_DEVHDR_HDRTYPE 16 151#define M_PCI_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE) 152#define V_PCI_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE) 153#define G_PCI_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE) 154 155#define K_PCI_DEVHDR_HDRTYPE_TYPE0 0 156 157#define S_PCI_DEVHDR_BIST 24 158#define M_PCI_DEVHDR_BIST _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST) 159#define V_PCI_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST) 160#define G_PCI_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST) 161 162/* 163 * PCI Status Register (Table 8-5). Note that these constants 164 * assume you've read the command and status register 165 * together (32-bit read at offset 0x04) 166 */ 167 168#define M_PCI_STATUS_CAPLIST _SB_MAKEMASK1_32(20) 169#define M_PCI_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) 170#define M_PCI_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) 171#define M_PCI_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) 172#define M_PCI_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) 173 174#define S_PCI_STATUS_DEVSELTIMING 25 175#define M_PCI_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_PCI_STATUS_DEVSELTIMING) 176#define V_PCI_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_PCI_STATUS_DEVSELTIMING) 177#define G_PCI_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING) 178 179#define M_PCI_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) 180#define M_PCI_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) 181#define M_PCI_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) 182#define M_PCI_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) 183#define M_PCI_STATUS_DETPARERR _SB_MAKEMASK1_32(31) 184 185/* 186 * Device Header Register (Table 8-6, Table 8-7) 187 */ 188 189#define S_PCI_DEVHDR_CLINESZ 0 190#define M_PCI_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ) 191#define V_PCI_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ) 192#define G_PCI_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ) 193 194#define S_PCI_DEVHDR_LATTIME 8 195#define M_PCI_DEVHDR_LATTIME _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTIME) 196#define V_PCI_DEVHDR_LATTIME(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTIME) 197#define G_PCI_DEVHDR_LATTIME(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTIME,M_PCI_DEVHDR_LATTIME) 198 199#define S_PCI_DEVHDR_HDRTYPE 16 200#define M_PCI_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE) 201#define V_PCI_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE) 202#define G_PCI_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE) 203 204#define S_PCI_DEVHDR_BIST 24 205#define M_PCI_DEVHDR_BIST _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST) 206#define V_PCI_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST) 207#define G_PCI_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST) 208 209/* 210 * Timeout and feature control Register (Table 8-8) (Table 8-9) 211 * Note that these constants assume you've read the timeout/fcontrol register 212 * together (32-bit read at offset 0x40) 213 */ 214 215#define S_PCI_TIMEOUT_TRDY 0 216#define M_PCI_TIMEOUT_TRDY _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_TRDY) 217#define V_PCI_TIMEOUT_TRDY(x) _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_TRDY) 218#define G_PCI_TIMEOUT_TRDY(x) _SB_GETVALUE_32(x,S_PCI_TIMEOUT_TRDY,M_PCI_TIMEOUT_TRDY) 219 220#define S_PCI_TIMEOUT_RETRY 8 221#define M_PCI_TIMEOUT_RETRY _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_RETRY) 222#define V_PCI_TIMEOUT_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_RETRY) 223#define G_PCI_TIMEOUT_RETRY(x) _SB_GETVALUE_32(x,S_PCI_TIMEOUT_RETRY,M_PCI_TIMEOUT_RETRY) 224 225#define M_PCI_FCONTROL_BAR4_EN _SB_MAKEMASK1_32(16) 226#define M_PCI_FCONTROL_BAR5_EN _SB_MAKEMASK1_32(17) 227#define M_PCI_FCONTROL_PTP_EN _SB_MAKEMASK1_32(18) 228#define M_PCI_FCONTROL_ADAPT_RETRY_EN _SB_MAKEMASK1_32(19) 229 230#define S_PCI_FCONTROL_MIN_TAR_RETRY 20 231#define M_PCI_FCONTROL_MIN_TAR_RETRY _SB_MAKEMASK_32(3,S_PCI_FCONTROL_MIN_TAR_RETRY) 232#define V_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY) 233#define G_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY,M_PCI_FCONTROL_MIN_TAR_RETRY) 234 235#define S_PCI_FCONTROL_NOM_TAR_RETRY 23 236#define M_PCI_FCONTROL_NOM_TAR_RETRY _SB_MAKEMASK_32(4,S_PCI_FCONTROL_NOM_TAR_RETRY) 237#define V_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY) 238#define G_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY,M_PCI_FCONTROL_NOM_TAR_RETRY) 239 240#define S_PCI_FCONTROL_MAX_TAR_RETRY 27 241#define M_PCI_FCONTROL_MAX_TAR_RETRY _SB_MAKEMASK_32(5,S_PCI_FCONTROL_MAX_TAR_RETRY) 242#define V_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY) 243#define G_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY,M_PCI_FCONTROL_MAX_TAR_RETRY) 244 245/* 246 * BAR0 Map Table Entry (Offsets 0x40-0x80) (Table 8-10) 247 */ 248 249#define M_PCI_BAR0MAP_ENABLE _SB_MAKEMASK1_32(0) 250#define M_PCI_BAR0MAP_SENDLDT _SB_MAKEMASK1_32(1) 251#define S_PCI_BAR0MAP_ADDR 12 252#define M_PCI_BAR0MAP_ADDR _SB_MAKEMASK_32(20,S_PCI_BAR0MAP_ADDR) 253 254/* 255 * Additional Status Register (Table 8-11) 256 */ 257 258#define M_PCI_ASTATUS_HOTPLUG_EN _SB_MAKEMASK1_32(0) 259#define M_PCI_ASTATUS_SERR_DET _SB_MAKEMASK1_32(1) 260#define M_PCI_ASTATUS_TRDYERR _SB_MAKEMASK1_32(2) 261#define M_PCI_ASTATUS_RETRTYERR _SB_MAKEMASK1_32(3) 262#define M_PCI_ASTATUS_TRDYINTMASK _SB_MAKEMASK1_32(4) 263#define M_PCI_ASTATUS_RETRYINTMASK _SB_MAKEMASK1_32(5) 264#define M_PCI_ASTATUS_SIGNALINTA _SB_MAKEMASK1_32(6) 265 266#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 267/* 268 * Read Host Register 269 */ 270 271#define M_PCI_READHOST_RDHOST _SB_MAKEMASK1_32(0) 272 273/* 274 * Adaptive Extend Register 275 */ 276 277#define S_PCI_ADXTEND_NOM_TAR_RETRY 1 278#define M_PCI_ADXTEND_NOM_TAR_RETRY _SB_MAKEMASK_32(3,S_PCI_ADXTEND_NOM_TAR_RETRY) 279#define V_PCI_ADXTEND_NOM_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY) 280#define G_PCI_ADXTEND_NOM_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY,M_PCI_ADXTEND_NOM_TAR_RETRY) 281 282#define S_PCI_ADXTEND_MAX_TAR_RETRY 4 283#define M_PCI_ADXTEND_MAX_TAR_RETRY _SB_MAKEMASK_32(2,S_PCI_ADXTEND_MAX_TAR_RETRY) 284#define V_PCI_ADXTEND_MAX_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY) 285#define G_PCI_ADXTEND_MAX_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY,M_PCI_ADXTEND_MAX_TAR_RETRY) 286 287#define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP _SB_MAKEMASK1_32(6) 288#define M_PCI_ADXTEND_DIS_MEMRD_BE _SB_MAKEMASK1_32(6) 289#endif /* 1250 PASS2 || 112x PASS1 */ 290 291 292#endif 293 294 295