1/* $NetBSD: rmixlvar.h,v 1.6 2011/07/01 19:01:31 dyoung Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _MIPS_RMI_RMIXLVAR_H_ 39#define _MIPS_RMI_RMIXLVAR_H_ 40 41#include <mips/cpu.h> 42#include <mips/locore.h> 43#include <mips/rmi/rmixl_firmware.h> 44 45#include <sys/bus.h> 46 47#include <dev/pci/pcivar.h> 48 49extern void rmixl_pcr_init_core(void); 50 51static inline bool 52cpu_rmixl(const struct pridtab *ct) 53{ 54 if (ct->cpu_cid == MIPS_PRID_CID_RMI) 55 return true; 56 return false; 57} 58 59static inline bool 60cpu_rmixlr(const struct pridtab *ct) 61{ 62 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 63 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLR) 64 return true; 65 return false; 66} 67 68static inline bool 69cpu_rmixls(const struct pridtab *ct) 70{ 71 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 72 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLS) 73 return true; 74 return false; 75} 76 77static inline bool 78cpu_rmixlp(const struct pridtab *ct) 79{ 80 u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 81 if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLP) 82 return true; 83 return false; 84} 85 86static inline int 87cpu_rmixl_chip_type(const struct pridtab *ct) 88{ 89 return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE; 90} 91 92typedef enum { 93 PSB_TYPE_UNKNOWN=0, 94 PSB_TYPE_RMI, 95 PSB_TYPE_DELL, 96} rmixlfw_psb_type_t; 97 98static inline const char * 99rmixlfw_psb_type_name(rmixlfw_psb_type_t type) 100{ 101 switch(type) { 102 case PSB_TYPE_UNKNOWN: 103 return "unknown"; 104 case PSB_TYPE_RMI: 105 return "RMI"; 106 case PSB_TYPE_DELL: 107 return "DELL"; 108 default: 109 return "undefined"; 110 } 111} 112 113struct rmixl_config { 114 uint64_t rc_io_pbase; 115 uint64_t rc_flash_pbase; /* FLASH_BAR */ 116 uint64_t rc_flash_mask; /* FLASH_BAR */ 117 bus_addr_t rc_pci_cfg_pbase; 118 bus_size_t rc_pci_cfg_size; 119 bus_addr_t rc_pci_ecfg_pbase; 120 bus_size_t rc_pci_ecfg_size; 121 bus_addr_t rc_pci_mem_pbase; 122 bus_size_t rc_pci_mem_size; 123 bus_addr_t rc_pci_io_pbase; 124 bus_size_t rc_pci_io_size; 125 struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */ 126 struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */ 127 struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */ 128 struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */ 129 struct mips_bus_space rc_pci_ecfg_memt; /* PCI ECFG */ 130 struct mips_bus_space rc_pci_memt; /* PCI MEM */ 131 struct mips_bus_space rc_pci_iot; /* PCI IO */ 132 struct mips_bus_dma_tag rc_dma_tag; 133 bus_dma_tag_t rc_64bit_dmat; 134 bus_dma_tag_t rc_32bit_dmat; 135 bus_dma_tag_t rc_29bit_dmat; 136 struct extent *rc_phys_ex; /* Note: MB units */ 137 struct extent *rc_obio_eb_ex; 138 struct extent *rc_obio_el_ex; 139 struct extent *rc_iobus_ex; 140 struct extent *rc_pci_cfg_ex; 141 struct extent *rc_pci_ecfg_ex; 142 struct extent *rc_pci_mem_ex; 143 struct extent *rc_pci_io_ex; 144 int rc_mallocsafe; 145 rmixlfw_info_t rc_psb_info; 146 rmixlfw_psb_type_t rc_psb_type; 147 volatile struct rmixlfw_cpu_wakeup_info 148 *rc_cpu_wakeup_info; 149 const void *rc_cpu_wakeup_end; 150}; 151 152extern struct rmixl_config rmixl_configuration; 153 154extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *); 155extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *); 156extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *); 157extern void rmixl_pci_cfg_bus_mem_init(bus_space_tag_t, void *); 158extern void rmixl_pci_ecfg_bus_mem_init(bus_space_tag_t, void *); 159extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *); 160extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *); 161 162extern void rmixl_addr_error_init(void); 163extern int rmixl_addr_error_check(void); 164 165extern uint64_t rmixl_mfcr(u_int); 166extern void rmixl_mtcr(uint64_t, u_int); 167extern void rmixl_eirr_ack(uint64_t, uint64_t, uint64_t); 168 169 170/* 171 * rmixl_cache_err_dis: 172 * - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors 173 * - clear the cache error log 174 * - return previous value from RMIXL_PCR_L1D_CONFIG0 175 */ 176static inline uint64_t 177rmixl_cache_err_dis(void) 178{ 179 uint64_t r; 180 181 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 182 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e); 183 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 184 return r; 185} 186 187/* 188 * rmixl_cache_err_restore: 189 * - clear the cache error log, cache error overflow log, 190 * and cache interrupt registers 191 * - restore previous value to RMIXL_PCR_L1D_CONFIG0 192 */ 193static inline void 194rmixl_cache_err_restore(uint64_t r) 195{ 196 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0); 197 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0); 198 rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0); 199 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 200} 201 202static inline uint64_t 203rmixl_cache_err_check(void) 204{ 205 return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG); 206} 207 208static inline int 209rmixl_probe_4(volatile uint32_t *va) 210{ 211 uint32_t r; 212 int err; 213 int s; 214 215 s = splhigh(); 216 r = rmixl_cache_err_dis(); 217 (void)*va; /* probe */ 218 err = rmixl_cache_err_check(); 219 rmixl_cache_err_restore(r); 220 splx(s); 221 222 return (err == 0); 223} 224 225#endif /* _MIPS_RMI_RMIXLVAR_H_ */ 226