ingenic_regs.h revision 1.21
1/* $NetBSD: ingenic_regs.h,v 1.21 2015/08/07 17:37:54 macallan Exp $ */ 2 3/*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef INGENIC_REGS_H 30#define INGENIC_REGS_H 31 32/* for wbflush() */ 33#include <mips/locore.h> 34 35/* UARTs, mostly 16550 compatible with 32bit spaced registers */ 36#define JZ_UART0 0x10030000 37#define JZ_UART1 0x10031000 38#define JZ_UART2 0x10032000 39#define JZ_UART3 0x10033000 40#define JZ_UART4 0x10034000 41 42/* LCD controller base addresses, registers are in jzfb_regs.h */ 43#define JZ_LCDC0_BASE 0x13050000 44#define JZ_LCDC1_BASE 0x130a0000 45 46/* watchdog */ 47#define JZ_WDOG_TDR 0x10002000 /* compare */ 48#define JZ_WDOG_TCER 0x10002004 49 #define TCER_ENABLE 0x01 /* enable counter */ 50#define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */ 51#define JZ_WDOG_TCSR 0x1000200c 52 #define TCSR_PCK_EN 0x01 /* PCLK */ 53 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 54 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 55 #define TCSR_PRESCALE_M 0x38 56 #define TCSR_DIV_1 0x00 57 #define TCSR_DIV_4 0x08 58 #define TCSR_DIV_16 0x10 59 #define TCSR_DIV_64 0x18 60 #define TCSR_DIV_256 0x20 61 #define TCSR_DIV_1024 0x28 62 63/* timers and PWMs */ 64#define JZ_TC_TER 0x10002010 /* TC enable reg, ro */ 65#define JZ_TC_TESR 0x10002014 /* TC enable set reg. */ 66 #define TESR_TCST0 0x0001 /* enable counter 0 */ 67 #define TESR_TCST1 0x0002 /* enable counter 1 */ 68 #define TESR_TCST2 0x0004 /* enable counter 2 */ 69 #define TESR_TCST3 0x0008 /* enable counter 3 */ 70 #define TESR_TCST4 0x0010 /* enable counter 4 */ 71 #define TESR_TCST5 0x0020 /* enable counter 5 */ 72 #define TESR_TCST6 0x0040 /* enable counter 6 */ 73 #define TESR_TCST7 0x0080 /* enable counter 7 */ 74 #define TESR_OST 0x8000 /* enable OST */ 75#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */ 76#define JZ_TC_TFR 0x10002020 77 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 78 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 79 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 80 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 81 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 82 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 83 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 84 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 85 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 86#define JZ_TC_TFSR 0x10002024 /* timer flag set */ 87#define JZ_TC_TFCR 0x10002028 /* timer flag clear */ 88#define JZ_TC_TMR 0x10002030 /* timer flag mask */ 89#define JZ_TC_TMSR 0x10002034 /* timer flag mask set */ 90#define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/ 91 92#define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */ 93#define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */ 94#define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */ 95 96#define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10)) 97/* same bits as in JZ_WDOG_TCSR */ 98 99/* operating system timer */ 100#define JZ_OST_DATA 0x100020e0 /* compare */ 101#define JZ_OST_CNT_LO 0x100020e4 102#define JZ_OST_CNT_HI 0x100020e8 103#define JZ_OST_CTRL 0x100020ec 104 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 105 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 106 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 107 #define OSTC_PRESCALE_M 0x0038 108 #define OSTC_DIV_1 0x0000 109 #define OSTC_DIV_4 0x0008 110 #define OSTC_DIV_16 0x0010 111 #define OSTC_DIV_64 0x0018 112 #define OSTC_DIV_256 0x0020 113 #define OSTC_DIV_1024 0x0028 114 #define OSTC_SHUTDOWN 0x0200 115 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 116#define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */ 117 118static inline void 119writereg(uint32_t reg, uint32_t val) 120{ 121 *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 122 wbflush(); 123} 124 125static inline uint32_t 126readreg(uint32_t reg) 127{ 128 wbflush(); 129 return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg); 130} 131 132/* extra CP0 registers */ 133static inline uint32_t 134MFC0(uint32_t r, uint32_t s) 135{ 136 uint32_t ret = 0x12345678; 137 138 __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s)); 139 return ret; 140} 141 142#define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s)) 143 144#define CP0_CORE_CTRL 12 /* select 2 */ 145 #define CC_SW_RST0 1 /* reset core 0 */ 146 #define CC_SW_RST1 2 /* reset core 1 */ 147 #define CC_RPC0 0x100 /* dedicated reset entry core 0 */ 148 #define CC_RPC1 0x200 /* -- || -- core 1 */ 149 #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */ 150 #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */ 151 152/* cores status, 12 select 3 */ 153#define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */ 154#define CS_MIRQ1_P 0x00002 /* || core 1 */ 155#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */ 156#define CS_IRQ1_P 0x00200 /* || core 1 */ 157#define CS_SLEEP0 0x10000 /* core 0 sleeping */ 158#define CS_SLEEP1 0x20000 /* core 1 sleeping */ 159 160/* cores reset entry & IRQ masks - 12 select 4 */ 161#define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */ 162#define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */ 163#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */ 164#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */ 165#define REIM_ENTRY_M 0xffff0000 /* reset exception entry if RPCn=1 */ 166 167#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ 168 169/* power management */ 170#define JZ_CPCCR 0x10000000 /* Clock Control Register */ 171 #define JZ_PDIV_M 0x000f0000 /* PCLK divider mask */ 172 #define JZ_PDIV_S 16 /* PCLK divider shift */ 173 #define JZ_CDIV_M 0x0000000f /* CPU clock divider mask */ 174 #define JZ_CDIV_S 0 /* CPU clock divider shift */ 175#define JZ_CPMPCR 0x00000014 /* MPLL */ 176 #define JZ_PLLM_S 19 /* PLL multiplier shift */ 177 #define JZ_PLLM_M 0xfff80000 /* PLL multiplier mask */ 178 #define JZ_PLLN_S 13 /* PLL divider shift */ 179 #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */ 180 #define JZ_PLLP_S 9 /* PLL postdivider shift */ 181 #define JZ_PLLP_M 0x00001700 /* PLL postdivider mask */ 182 #define JZ_PLLON 0x00000010 /* PLL is on and stable */ 183 #define JZ_PLLBP 0x00000002 /* PLL bypass */ 184 #define JZ_PLLEN 0x00000001 /* PLL enable */ 185#define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ 186 #define CLK_NEMC (1 << 0) 187 #define CLK_BCH (1 << 1) 188 #define CLK_OTG0 (1 << 2) 189 #define CLK_MSC0 (1 << 3) 190 #define CLK_SSI0 (1 << 4) 191 #define CLK_SMB0 (1 << 5) 192 #define CLK_SMB1 (1 << 6) 193 #define CLK_SCC (1 << 7) 194 #define CLK_AIC (1 << 8) 195 #define CLK_TSSI0 (1 << 9) 196 #define CLK_OWI (1 << 10) 197 #define CLK_MSC1 (1 << 11) 198 #define CLK_MSC2 (1 << 12) 199 #define CLK_KBC (1 << 13) 200 #define CLK_SADC (1 << 14) 201 #define CLK_UART0 (1 << 15) 202 #define CLK_UART1 (1 << 16) 203 #define CLK_UART2 (1 << 17) 204 #define CLK_UART3 (1 << 18) 205 #define CLK_SSI1 (1 << 19) 206 #define CLK_SSI2 (1 << 20) 207 #define CLK_PDMA (1 << 21) 208 #define CLK_GPS (1 << 22) 209 #define CLK_MAC (1 << 23) 210 #define CLK_UHC (1 << 24) 211 #define CLK_SMB2 (1 << 25) 212 #define CLK_CIM (1 << 26) 213 #define CLK_TVE (1 << 27) 214 #define CLK_LCD (1 << 28) 215 #define CLK_IPU (1 << 29) 216 #define CLK_DDR0 (1 << 30) 217 #define CLK_DDR1 (1 << 31) 218 219#define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ 220 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 221 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 222 #define OPCR_L2CM_M 0x0c000000 223 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 224 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 225 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 226 #define OPCR_SPENDN0 0x00000080 /* 0 - OTG port forced down */ 227 #define OPCR_SPENDN1 0x00000040 /* 0 - UHC port forced down */ 228 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 229 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 230 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 231 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 232 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 233 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 234#define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ 235 #define CLK_SMB3 (1 << 0) 236 #define CLK_TSSI1 (1 << 1) 237 #define CLK_VPU (1 << 2) 238 #define CLK_PCM (1 << 3) 239 #define CLK_GPU (1 << 4) 240 #define CLK_COMPRESS (1 << 5) 241 #define CLK_AIC1 (1 << 6) 242 #define CLK_GPVLC (1 << 7) 243 #define CLK_OTG1 (1 << 8) 244 #define CLK_HDMI (1 << 9) 245 #define CLK_UART4 (1 << 10) 246 #define CLK_AHB_MON (1 << 11) 247 #define CLK_SMB4 (1 << 12) 248 #define CLK_DES (1 << 13) 249 #define CLK_X2D (1 << 14) 250 #define CLK_P1 (1 << 15) 251 252#define JZ_USBPCR 0x1000003c 253 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 254 #define PCR_AVLD_REG 0x40000000 255 #define PCR_IDPULLUP_MASK 0x30000000 256 #define PCR_INCR_MASK 0x08000000 257 #define PCR_TCRISETUNE 0x04000000 258 #define PCR_COMMONONN 0x02000000 259 #define PCR_VBUSVLDEXT 0x01000000 260 #define PCR_VBUSVLDEXTSEL 0x00800000 261 #define PCR_POR 0x00400000 262 #define PCR_SIDDQ 0x00200000 263 #define PCR_OTG_DISABLE 0x00100000 264 #define PCR_COMPDISTN_M 0x000e0000 265 #define PCR_OTGTUNE 0x0001c000 266 #define PCR_SQRXTUNE 0x00003800 267 #define PCR_TXFSLSTUNE 0x00000780 268 #define PCR_TXPREEMPHTUNE 0x00000040 269 #define PCR_TXHSXVTUNE 0x00000030 270 #define PCR_TXVREFTUNE 0x0000000f 271#define JZ_USBRDT 0x10000040 /* Reset Detect Timer Register */ 272#define JZ_USBVBFIL 0x10000044 273#define JZ_USBPCR1 0x10000048 274 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 275 #define PCR_REFCLK_CORE 0x0c000000 276 #define PCR_REFCLK_XO25 0x04000000 277 #define PCR_REFCLK_CO 0x00000000 278 #define PCR_CLK_M 0x03000000 /* clock */ 279 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 280 #define PCR_CLK_48 0x02000000 /* 48MHz */ 281 #define PCR_CLK_24 0x01000000 /* 24MHz */ 282 #define PCR_CLK_12 0x00000000 /* 12MHz */ 283 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 284 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 285 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 286 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 287 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 288 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 289 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 290 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 291 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 292 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 293 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 294 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 295 #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */ 296 297#define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */ 298 #define UHCCDR_SCLK_A 0x00000000 299 #define UHCCDR_MPLL 0x40000000 300 #define UHCCDR_EPLL 0x80000000 301 #define UHCCDR_OTG_PHY 0xc0000000 302 #define UHCCDR_CE 0x20000000 303 #define UHCCDR_BUSY 0x10000000 304 #define UHCCDR_STOP 0x08000000 305 #define UHCCDR_DIV_M 0x000000ff 306#define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */ 307#define JZ_SPCR1 0x100000bc 308#define JZ_SRBC 0x100000c4 /* Soft Reset & Bus Control */ 309 310/* clock divider registers */ 311#define JZ_MSC0CDR 0x10000068 312 #define MSCCDR_SCLK_A 0x40000000 313 #define MSCCDR_MPLL 0x80000000 314 #define MSCCDR_CE 0x20000000 315 #define MSCCDR_BUSY 0x10000000 316 #define MSCCDR_STOP 0x08000000 317 #define MSCCDR_PHASE 0x00008000 /* 0 - 90deg phase, 1 - 180 */ 318 #define MSCCDR_DIV_M 0x000000ff /* src / ((div + 1) * 2) */ 319 #define UHCCDR_DIV_M 0x000000ff 320#define JZ_MSC1CDR 0x100000a4 321#define JZ_MSC2CDR 0x100000a8 322 323/* 324 * random number generator 325 * 326 * Its function currently isn't documented by Ingenic. 327 * However, testing suggests that it works as expected. 328 */ 329#define JZ_ERNG 0x100000d8 330#define JZ_RNG 0x100000dc 331 332/* interrupt controller */ 333#define JZ_ICSR0 0x10001000 /* raw IRQ line status */ 334#define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */ 335#define JZ_ICMSR0 0x10001008 /* sets bits in mask register */ 336#define JZ_ICMCR0 0x1000100c /* clears bits in mask register */ 337#define JZ_ICPR0 0x10001010 /* line status after masking */ 338 339#define JZ_ICSR1 0x10001020 /* raw IRQ line status */ 340#define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */ 341#define JZ_ICMSR1 0x10001028 /* sets bits in mask register */ 342#define JZ_ICMCR1 0x1000102c /* clears bits in maks register */ 343#define JZ_ICPR1 0x10001030 /* line status after masking */ 344 345#define JZ_DSR0 0x10001034 /* source for PDMA */ 346#define JZ_DMR0 0x10001038 /* mask for PDMA */ 347#define JZ_DPR0 0x1000103c /* pending for PDMA */ 348 349#define JZ_DSR1 0x10001040 /* source for PDMA */ 350#define JZ_DMR1 0x10001044 /* mask for PDMA */ 351#define JZ_DPR1 0x10001048 /* pending for PDMA */ 352 353/* memory controller */ 354#define JZ_DMMAP0 0x13010024 355#define JZ_DMMAP1 0x13010028 356 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 357 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 358 * constant */ 359/* USB controllers */ 360#define JZ_EHCI_BASE 0x13490000 361#define JZ_OHCI_BASE 0x134a0000 362#define JZ_DWC2_BASE 0x13500000 363 364/* Ethernet */ 365#define JZ_DME_BASE 0x16000000 366#define JZ_DME_IO 0 367#define JZ_DME_DATA 2 368 369/* GPIO */ 370#define JZ_GPIO_A_BASE 0x10010000 371#define JZ_GPIO_B_BASE 0x10010100 372#define JZ_GPIO_C_BASE 0x10010200 373#define JZ_GPIO_D_BASE 0x10010300 374#define JZ_GPIO_E_BASE 0x10010400 375#define JZ_GPIO_F_BASE 0x10010500 376 377/* GPIO registers per port */ 378#define JZ_GPIO_PIN 0x00000000 /* pin level register */ 379/* 0 - normal gpio, 1 - interrupt */ 380#define JZ_GPIO_INT 0x00000010 /* interrupt register */ 381#define JZ_GPIO_INTS 0x00000014 /* interrupt set register */ 382#define JZ_GPIO_INTC 0x00000018 /* interrupt clear register */ 383/* 384 * INT == 1: 1 disables interrupt 385 * INT == 0: device select, see below 386 */ 387#define JZ_GPIO_MASK 0x00000020 /* port mask register */ 388#define JZ_GPIO_MASKS 0x00000024 /* port mask set register */ 389#define JZ_GPIO_MASKC 0x00000028 /* port mask clear register */ 390/* 391 * INT == 1: 0 - level triggered, 1 - edge triggered 392 * INT == 0: 0 - device select, see below 393 */ 394#define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */ 395#define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */ 396#define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */ 397/* 398 * INT == 1: 399 * PAT1 == 0: 0 - trigger on low, 1 - trigger on high 400 * PAT1 == 1: 0 - trigger on falling edge, 1 - trigger on rising edge 401 * INT == 0: 402 * MASK == 0: 403 * PAT1 == 0: 0 - device 0, 1 - device 1 404 * PAT1 == 1: 0 - device 2, 1 - device 3 405 * MASK == 1: 406 * PAT1 == 0: set gpio output 407 * PAT1 == 1: pin is input 408 */ 409#define JZ_GPIO_PAT0 0x00000040 /* pattern 0 register */ 410#define JZ_GPIO_PAT0S 0x00000044 /* pattern 0 set register */ 411#define JZ_GPIO_PAT0C 0x00000048 /* pattern 0 clear register */ 412/* 1 - interrupt happened */ 413#define JZ_GPIO_FLAG 0x00000050 /* flag register */ 414#define JZ_GPIO_FLAGC 0x00000058 /* flag clear register */ 415/* 1 - disable pull up/down resistors */ 416#define JZ_GPIO_DPULL 0x00000070 /* pull disable register */ 417#define JZ_GPIO_DPULLS 0x00000074 /* pull disable set register */ 418#define JZ_GPIO_DPULLC 0x00000078 /* pull disable clear register */ 419/* the following are uncommented in the manual */ 420#define JZ_GPIO_DRVL 0x00000080 /* drive low register */ 421#define JZ_GPIO_DRVLS 0x00000084 /* drive low set register */ 422#define JZ_GPIO_DRVLC 0x00000088 /* drive low clear register */ 423#define JZ_GPIO_DIR 0x00000090 /* direction register */ 424#define JZ_GPIO_DIRS 0x00000094 /* direction register */ 425#define JZ_GPIO_DIRC 0x00000098 /* direction register */ 426#define JZ_GPIO_DRVH 0x000000a0 /* drive high register */ 427#define JZ_GPIO_DRVHS 0x000000a4 /* drive high set register */ 428#define JZ_GPIO_DRVHC 0x000000a8 /* drive high clear register */ 429 430static inline void 431gpio_as_output(uint32_t g, int pin) 432{ 433 uint32_t mask = 1 << pin; 434 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 435 436 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 437 writereg(reg + JZ_GPIO_MASKS, mask); 438 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */ 439} 440 441static inline void 442gpio_set(uint32_t g, int pin, int level) 443{ 444 uint32_t mask = 1 << pin; 445 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 446 447 reg += (level == 0) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S; 448 writereg(reg, mask); 449} 450 451static inline void 452gpio_as_dev0(uint32_t g, int pin) 453{ 454 uint32_t mask = 1 << pin; 455 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 456 457 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 458 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 459 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */ 460 writereg(reg + JZ_GPIO_PAT0C, mask); 461} 462 463static inline void 464gpio_as_dev1(uint32_t g, int pin) 465{ 466 uint32_t mask = 1 << pin; 467 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 468 469 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 470 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 471 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */ 472 writereg(reg + JZ_GPIO_PAT0S, mask); 473} 474 475static inline void 476gpio_as_dev2(uint32_t g, int pin) 477{ 478 uint32_t mask = 1 << pin; 479 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 480 481 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 482 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 483 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */ 484 writereg(reg + JZ_GPIO_PAT0C, mask); 485} 486 487static inline void 488gpio_as_dev3(uint32_t g, int pin) 489{ 490 uint32_t mask = 1 << pin; 491 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 492 493 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 494 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 495 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */ 496 writereg(reg + JZ_GPIO_PAT0S, mask); 497} 498 499static inline void 500gpio_as_intr_level(uint32_t g, int pin) 501{ 502 uint32_t mask = 1 << pin; 503 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 504 505 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 506 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 507 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 508 writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */ 509 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 510 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 511} 512 513static inline void 514gpio_as_intr_level_low(uint32_t g, int pin) 515{ 516 uint32_t mask = 1 << pin; 517 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 518 519 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 520 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 521 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 522 writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */ 523 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 524 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 525} 526 527static inline void 528gpio_as_input(uint32_t g, int pin) 529{ 530 uint32_t mask = 1 << pin; 531 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 532 533 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 534 writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */ 535 writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */ 536 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */ 537} 538 539/* I2C / SMBus */ 540#define JZ_SMB0_BASE 0x10050000 541#define JZ_SMB1_BASE 0x10051000 542#define JZ_SMB2_BASE 0x10052000 543#define JZ_SMB3_BASE 0x10053000 544#define JZ_SMB4_BASE 0x10054000 545 546/* SMBus register offsets, per port */ 547#define JZ_SMBCON 0x00 /* SMB control */ 548 #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ 549 #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ 550 #define JZ_REST 0x20 /* 1 - allow RESTART */ 551 #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ 552 #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ 553 #define JZ_SPD_M 0x06 /* bus speed control */ 554 #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ 555 #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ 556 #define JZ_MD 0x01 /* enable master */ 557#define JZ_SMBTAR 0x04 /* SMB target address */ 558 #define JZ_SMATP 0x1000 /* enable 10bit master addr */ 559 #define JZ_SPECIAL 0x0800 /* 1 - special command */ 560 #define JZ_START 0x0400 /* 1 - send START */ 561 #define JZ_SMBTAR_M 0x03ff /* target address */ 562#define JZ_SMBSAR 0x08 /* SMB slave address */ 563#define JZ_SMBDC 0x10 /* SMB data buffer and command */ 564 #define JZ_CMD 0x100 /* 1 - read, 0 - write */ 565 #define JZ_DATA 0x0ff 566#define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ 567#define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ 568#define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ 569#define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ 570#define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ 571 #define JZ_ISTT 0x400 /* START or RESTART occured */ 572 #define JZ_ISTP 0x200 /* STOP occured */ 573 #define JZ_TXABT 0x40 /* ABORT occured */ 574 #define JZ_TXEMP 0x10 /* TX FIFO is low */ 575 #define JZ_TXOF 0x08 /* TX FIFO is high */ 576 #define JZ_RXFL 0x04 /* RX FIFO is at JZ_SMBRXTL*/ 577 #define JZ_RXOF 0x02 /* RX FIFO is high */ 578 #define JZ_RXUF 0x01 /* RX FIFO underflow */ 579#define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ 580#define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ 581#define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ 582#define JZ_SMBCINT 0x40 /* Clear Interrupts */ 583 #define JZ_CLEARALL 0x01 584#define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ 585#define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ 586#define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ 587#define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ 588#define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ 589#define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ 590#define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ 591#define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ 592#define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ 593#define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ 594#define JZ_SMBENB 0x6C /* SMB Enable */ 595 #define JZ_ENABLE 0x01 596#define JZ_SMBST 0x70 /* SMB Status register */ 597 #define JZ_SLVACT 0x40 /* slave is active */ 598 #define JZ_MSTACT 0x20 /* master is active */ 599 #define JZ_RFF 0x10 /* RX FIFO is full */ 600 #define JZ_RFNE 0x08 /* RX FIFO not empty */ 601 #define JZ_TFE 0x04 /* TX FIFO is empty */ 602 #define JZ_TFNF 0x02 /* TX FIFO is not full */ 603 #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ 604#define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ 605#define JZ_SMBDMACR 0x88 /* DMA Control Register */ 606#define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ 607#define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ 608#define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ 609#define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ 610#define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ 611#define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ 612 #define JZ_HDENB 0x100 /* enable hold time */ 613 614/* SD/MMC hosts */ 615#define JZ_MSC0_BASE 0x13450000 616#define JZ_MSC1_BASE 0x13460000 617#define JZ_MSC2_BASE 0x13470000 618 619#define JZ_MSC_CTRL 0x00 620 #define JZ_SEND_CCSD 0x8000 621 #define JZ_SEND_AS_CCSD 0x4000 622 #define JZ_EXIT_MULTIPLE 0x0080 623 #define JZ_EXIT_TRANSFER 0x0040 624 #define JZ_START_READWAIT 0x0020 625 #define JZ_STOP_READWAIT 0x0010 626 #define JZ_RESET 0x0008 627 #define JZ_START_OP 0x0004 628 #define JZ_CLOCK_CTRL_M 0x0003 629 #define JZ_CLOCK_START 0x0002 630 #define JZ_CLOCK_STOP 0x0001 631#define JZ_MSC_STAT 0x04 632 #define JZ_AUTO_CMD12_DONE 0x80000000 633 #define JZ_AUTO_CMD23_DONE 0x40000000 634 #define JZ_SVS 0x20000000 635 #define JZ_PIN_LEVEL_M 0x1f000000 636 #define JZ_BCE 0x00100000 /* boot CRC error */ 637 #define JZ_BDE 0x00080000 /* boot data end */ 638 #define JZ_BAE 0x00040000 /* boot acknowledge error */ 639 #define JZ_BAR 0x00020000 /* boot ack. received */ 640 #define JZ_DMAEND 0x00010000 641 #define JZ_IS_RESETTING 0x00008000 642 #define JZ_SDIO_INT_ACTIVE 0x00004000 643 #define JZ_PRG_DONE 0x00002000 644 #define JZ_DATA_TRAN_DONE 0x00001000 645 #define JZ_END_CMD_RES 0x00000800 646 #define JZ_DATA_FIFO_AFULL 0x00000400 647 #define JZ_IS_READWAIT 0x00000200 648 #define JZ_CLK_EN 0x00000100 649 #define JZ_DATA_FIFO_FULL 0x00000080 650 #define JZ_DATA_FIFO_EMPTY 0x00000040 651 #define JZ_CRC_RES_ERR 0x00000020 652 #define JZ_CRC_READ_ERR 0x00000010 653 #define JZ_CRC_WRITE_ERR_M 0x0000000c 654 #define JZ_CRC_WRITE_OK 0x00000000 655 #define JZ_CRC_CARD_ERR 0x00000004 656 #define JZ_CRC_NO_STATUS 0x00000008 657 #define JZ_TIME_OUT_RES 0x00000002 658 #define JZ_TIME_OUT_READ 0x00000001 659#define JZ_MSC_CLKRT 0x08 660 #define JZ_DEV_CLK 0x0 661 #define JZ_DEV_CLK_2 0x1 /* DEV_CLK / 2 */ 662 #define JZ_DEV_CLK_4 0x2 /* DEV_CLK / 4 */ 663 #define JZ_DEV_CLK_8 0x3 /* DEV_CLK / 8 */ 664 #define JZ_DEV_CLK_16 0x4 /* DEV_CLK / 16 */ 665 #define JZ_DEV_CLK_32 0x5 /* DEV_CLK / 32 */ 666 #define JZ_DEV_CLK_64 0x6 /* DEV_CLK / 64 */ 667 #define JZ_DEV_CLK_128 0x7 /* DEV_CLK / 128 */ 668#define JZ_MSC_CMDAT 0x0c 669 #define JZ_CCS_EXPECTED 0x80000000 670 #define JZ_READ_CEATA 0x40000000 671 #define JZ_DIS_BOOT 0x08000000 672 #define JZ_ENA_BOOT 0x04000000 673 #define JZ_EXP_BOOT_ACK 0x02000000 674 #define JZ_BOOT_MODE 0x01000000 675 #define JZ_AUTO_CMD23 0x00040000 676 #define JZ_SDIO_PRDT 0x00020000 677 #define JZ_AUTO_CMD12 0x00010000 678 #define JZ_RTRG_M 0x0000c000 /* receive FIFO trigger */ 679 #define JZ_RTRG_16 0x00000000 /* >= 16 */ 680 #define JZ_RTRG_32 0x00004000 /* >= 32 */ 681 #define JZ_RTRG_64 0x00008000 /* >= 64 */ 682 #define JZ_RTRG_96 0x0000c000 /* >= 96 */ 683 #define JZ_TTRG_M 0x00003000 /* transmit FIFO trigger */ 684 #define JZ_TTRG_16 0x00000000 /* >= 16 */ 685 #define JZ_TTRG_32 0x00001000 /* >= 32 */ 686 #define JZ_TTRG_64 0x00002000 /* >= 64 */ 687 #define JZ_TTRG_96 0x00003000 /* >= 96 */ 688 #define JZ_IO_ABORT 0x00000800 689 #define JZ_BUS_WIDTH_M 0x00000600 690 #define JZ_BUS_1BIT 0x00000000 691 #define JZ_BUS_4BIT 0x00000200 692 #define JZ_BUS_8BIT 0x00000300 693 #define JZ_INIT 0x00000080 /* send 80 clk init before cmd */ 694 #define JZ_BUSY 0x00000040 695 #define JZ_STREAM 0x00000020 696 #define JZ_WRITE 0x00000010 /* read otherwise */ 697 #define JZ_DATA_EN 0x00000008 698 #define JZ_RESPONSE_M 0x00000007 /* response format */ 699 #define JZ_RES_NONE 0x00000000 700 #define JZ_RES_R1 0x00000001 /* R1 and R1b */ 701 #define JZ_RES_R2 0x00000002 702 #define JZ_RES_R3 0x00000003 703 #define JZ_RES_R4 0x00000004 704 #define JZ_RES_R5 0x00000005 705 #define JZ_RES_R6 0x00000006 706 #define JZ_RES_R7 0x00000007 707#define JZ_MSC_RESTO 0x10 /* 16bit response timeout in MSC_CLK */ 708#define JZ_MSC_RDTO RW 0x14 /* 32bit read timeout in MSC_CLK */ 709#define JZ_MSC_BLKLEN 0x18 /* 16bit block length */ 710#define JZ_MSC_NOB 0x1c /* 16bit block counter */ 711#define JZ_MSC_SNOB 0x20 /* 16bit successful block counter */ 712#define JZ_MSC_IMASK 0x24 /* interrupt mask */ 713 #define JZ_INT_AUTO_CMD23_DONE 0x40000000 714 #define JZ_INT_SVS 0x20000000 715 #define JZ_INT_PIN_LEVEL_M 0x1f000000 716 #define JZ_INT_BCE 0x00100000 717 #define JZ_INT_BDE 0x00080000 718 #define JZ_INT_BAE 0x00040000 719 #define JZ_INT_BAR 0x00020000 720 #define JZ_INT_DMAEND 0x00010000 721 #define JZ_INT_AUTO_CMD12_DONE 0x00008000 722 #define JZ_INT_DATA_FIFO_FULL 0x00004000 723 #define JZ_INT_DATA_FIFO_EMPTY 0x00002000 724 #define JZ_INT_CRC_RES_ERR 0x00001000 725 #define JZ_INT_CRC_READ_ERR 0x00000800 726 #define JZ_INT_CRC_WRITE_ERR 0x00000400 727 #define JZ_INT_TIMEOUT_RES 0x00000200 728 #define JZ_INT_TIMEOUT_READ 0x00000100 729 #define JZ_INT_SDIO 0x00000080 730 #define JZ_INT_TXFIFO_WR_REQ 0x00000040 731 #define JZ_INT_RXFIFO_RD_REQ 0x00000020 732 #define JZ_INT_EMD_CMD_RES 0x00000004 733 #define JZ_INT_PRG_DONE 0x00000002 734 #define JZ_INT_DATA_TRAN_DONE 0x00000001 735#define JZ_MSC_IFLG 0x28 /* interrupt flags */ 736#define JZ_MSC_CMD 0x2c /* 6bit CMD index */ 737#define JZ_MSC_ARG 0x30 /* 32bit argument */ 738#define JZ_MSC_RES 0x34 /* 8x16bit response data FIFO */ 739#define JZ_MSC_RXFIFO 0x38 740#define JZ_MSC_TXFIFO 0x3c 741#define JZ_MSC_LPM 0x40 742 #define JZ_DRV_SEL_M 0xc0000000 743 #define JZ_FALLING_EDGE 0x00000000 744 #define JZ_RISING_1NS 0x40000000 /* 1ns delay */ 745 #define JZ_RISING_4 0x80000000 /* 1/4 MSC_CLK delay */ 746 #define JZ_SMP_SEL 0x20000000 /* 1 - rising edge */ 747 #define JZ_LPM 0x00000001 /* low power mode */ 748#define JZ_MSC_DMAC 0x44 749 #define JZ_MODE_SEL 0x80 /* 1 - specify transfer length */ 750 #define JZ_AOFST_M 0x60 /* address offset in bytes */ 751 #define JZ_ALIGNEN 0x10 /* allow non-32bit-aligned transfers */ 752 #define JZ_INCR_M 0x0c /* burst type */ 753 #define JZ_INCR_16 0x00 754 #define JZ_INCR_32 0x04 755 #define JZ_INCR_64 0x08 756 #define JZ_DMASEL 0x02 /* 1 - SoC DMAC, 0 - MSC built-in */ 757 #define JZ_DMAEN 0x01 /* enable DMA */ 758#define JZ_MSC_DMANDA 0x48 /* next descriptor paddr */ 759#define JZ_MSC_DMADA 0x4c /* current descriptor */ 760#define JZ_MSC_DMALEN 0x50 /* transfer tength */ 761#define JZ_MSC_DMACMD 0x54 762 #define JZ_DMA_IDI_M 0xff000000 763 #define JZ_DMA_ID_M 0x00ff0000 764 #define JZ_DMA_AOFST_M 0x00000600 765 #define JZ_DMA_ALIGN 0x00000100 766 #define JZ_DMA_ENDI 0x00000002 767 #define JZ_DMA_LINK 0x00000001 768#define JZ_MSC_CTRL2 0x58 769 #define JZ_PIP 0x1f000000 /* 1 - intr trigger on high */ 770 #define JZ_RST_EN 0x00800000 771 #define JZ_STPRM 0x00000010 772 #define JZ_SVC 0x00000008 773 #define JZ_SMS_M 0x00000007 774 #define JZ_SMS_DEF 0x00000000 /* default speed */ 775 #define JZ_SMS_HIGH 0x00000001 /* high speed */ 776 #define JZ_SMS_SDR12 0x00000002 777 #define JZ_SMS_SDR25 0x00000003 778 #define JZ_SMS_SDR50 0x00000004 779#define JZ_MSC_RTCNT 0x5c /* RT FIFO count */ 780 781#endif /* INGENIC_REGS_H */ 782