ingenic_regs.h revision 1.15
1/* $NetBSD: ingenic_regs.h,v 1.15 2015/04/23 01:20:20 macallan Exp $ */ 2 3/*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef INGENIC_REGS_H 30#define INGENIC_REGS_H 31 32/* for wbflush() */ 33#include <mips/locore.h> 34 35/* UARTs, mostly 16550 compatible with 32bit spaced registers */ 36#define JZ_UART0 0x10030000 37#define JZ_UART1 0x10031000 38#define JZ_UART2 0x10032000 39#define JZ_UART3 0x10033000 40#define JZ_UART4 0x10034000 41 42/* LCD controller base addresses, registers are in jzfb_regs.h */ 43#define JZ_LCDC0_BASE 0x13050000 44#define JZ_LCDC1_BASE 0x130a0000 45 46/* watchdog */ 47#define JZ_WDOG_TDR 0x10002000 /* compare */ 48#define JZ_WDOG_TCER 0x10002004 49 #define TCER_ENABLE 0x01 /* enable counter */ 50#define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */ 51#define JZ_WDOG_TCSR 0x1000200c 52 #define TCSR_PCK_EN 0x01 /* PCLK */ 53 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 54 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 55 #define TCSR_PRESCALE_M 0x38 56 #define TCSR_DIV_1 0x00 57 #define TCSR_DIV_4 0x08 58 #define TCSR_DIV_16 0x10 59 #define TCSR_DIV_64 0x18 60 #define TCSR_DIV_256 0x20 61 #define TCSR_DIV_1024 0x28 62 63/* timers and PWMs */ 64#define JZ_TC_TER 0x10002010 /* TC enable reg, ro */ 65#define JZ_TC_TESR 0x10002014 /* TC enable set reg. */ 66 #define TESR_TCST0 0x0001 /* enable counter 0 */ 67 #define TESR_TCST1 0x0002 /* enable counter 1 */ 68 #define TESR_TCST2 0x0004 /* enable counter 2 */ 69 #define TESR_TCST3 0x0008 /* enable counter 3 */ 70 #define TESR_TCST4 0x0010 /* enable counter 4 */ 71 #define TESR_TCST5 0x0020 /* enable counter 5 */ 72 #define TESR_TCST6 0x0040 /* enable counter 6 */ 73 #define TESR_TCST7 0x0080 /* enable counter 7 */ 74 #define TESR_OST 0x8000 /* enable OST */ 75#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */ 76#define JZ_TC_TFR 0x10002020 77 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 78 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 79 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 80 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 81 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 82 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 83 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 84 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 85 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 86#define JZ_TC_TFSR 0x10002024 /* timer flag set */ 87#define JZ_TC_TFCR 0x10002028 /* timer flag clear */ 88#define JZ_TC_TMR 0x10002030 /* timer flag mask */ 89#define JZ_TC_TMSR 0x10002034 /* timer flag mask set */ 90#define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/ 91 92#define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */ 93#define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */ 94#define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */ 95 96#define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10)) 97/* same bits as in JZ_WDOG_TCSR */ 98 99/* operating system timer */ 100#define JZ_OST_DATA 0x100020e0 /* compare */ 101#define JZ_OST_CNT_LO 0x100020e4 102#define JZ_OST_CNT_HI 0x100020e8 103#define JZ_OST_CTRL 0x100020ec 104 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 105 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 106 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 107 #define OSTC_PRESCALE_M 0x0038 108 #define OSTC_DIV_1 0x0000 109 #define OSTC_DIV_4 0x0008 110 #define OSTC_DIV_16 0x0010 111 #define OSTC_DIV_64 0x0018 112 #define OSTC_DIV_256 0x0020 113 #define OSTC_DIV_1024 0x0028 114 #define OSTC_SHUTDOWN 0x0200 115 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 116#define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */ 117 118static inline void 119writereg(uint32_t reg, uint32_t val) 120{ 121 *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 122 wbflush(); 123} 124 125static inline uint32_t 126readreg(uint32_t reg) 127{ 128 wbflush(); 129 return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg); 130} 131 132/* extra CP0 registers */ 133static inline uint32_t 134MFC0(uint32_t r, uint32_t s) 135{ 136 uint32_t ret = 0x12345678; 137 138 __asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s)); 139 return ret; 140} 141 142#define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s)) 143 144#define CP0_CORE_CTRL 12 /* select 2 */ 145 #define CC_SW_RST0 1 /* reset core 0 */ 146 #define CC_SW_RST1 2 /* reset core 1 */ 147 #define CC_RPC0 0x100 /* dedicater reset entry core 0 */ 148 #define CC_RPC1 0x200 /* -- || -- core 1 */ 149 #define CC_SLEEP0M 0x10000 /* mask sleep core 0 */ 150 #define CC_SLEEP1M 0x20000 /* mask sleep core 1 */ 151 152/* cores status, 12 select 3 */ 153#define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */ 154#define CS_MIRQ1_P 0x00002 /* || core 1 */ 155#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */ 156#define CS_IRQ1_P 0x00200 /* || core 1 */ 157#define CS_SLEEP0 0x10000 /* core 0 sleeping */ 158#define CS_SLEEP1 0x20000 /* core 1 sleeping */ 159 160/* cores reset entry & IRQ masks - 12 select 4 */ 161#define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */ 162#define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */ 163#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */ 164#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */ 165#define REIM_ENTRY_M 0xffff0000 /* reset exception entry if RPCn=1 */ 166 167#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */ 168 169/* power management */ 170#define JZ_CPCCR 0x10000000 /* Clock Control Register */ 171 #define JZ_PDIV_M 0x000f0000 /* PCLK divider mask */ 172 #define JZ_PDIV_S 16 /* PCLK divider shift */ 173#define JZ_CPMPCR 0x00000014 /* MPLL */ 174 #define JZ_PLLM_S 19 /* PLL multiplier shift */ 175 #define JZ_PLLM_M 0xfff80000 /* PLL multiplier mask */ 176 #define JZ_PLLN_S 13 /* PLL divider shift */ 177 #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */ 178 #define JZ_PLLP_S 9 /* PLL postdivider shift */ 179 #define JZ_PLLP_M 0x00001700 /* PLL postdivider mask */ 180 #define JZ_PLLON 0x00000010 /* PLL is on and stable */ 181 #define JZ_PLLBP 0x00000002 /* PLL bypass */ 182 #define JZ_PLLEN 0x00000001 /* PLL enable */ 183#define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ 184 #define CLK_NEMC (1 << 0) 185 #define CLK_BCH (1 << 1) 186 #define CLK_OTG0 (1 << 2) 187 #define CLK_MSC0 (1 << 3) 188 #define CLK_SSI0 (1 << 4) 189 #define CLK_SMB0 (1 << 5) 190 #define CLK_SMB1 (1 << 6) 191 #define CLK_SCC (1 << 7) 192 #define CLK_AIC (1 << 8) 193 #define CLK_TSSI0 (1 << 9) 194 #define CLK_OWI (1 << 10) 195 #define CLK_MSC1 (1 << 11) 196 #define CLK_MSC2 (1 << 12) 197 #define CLK_KBC (1 << 13) 198 #define CLK_SADC (1 << 14) 199 #define CLK_UART0 (1 << 15) 200 #define CLK_UART1 (1 << 16) 201 #define CLK_UART2 (1 << 17) 202 #define CLK_UART3 (1 << 18) 203 #define CLK_SSI1 (1 << 19) 204 #define CLK_SSI2 (1 << 20) 205 #define CLK_PDMA (1 << 21) 206 #define CLK_GPS (1 << 22) 207 #define CLK_MAC (1 << 23) 208 #define CLK_UHC (1 << 24) 209 #define CLK_SMB2 (1 << 25) 210 #define CLK_CIM (1 << 26) 211 #define CLK_TVE (1 << 27) 212 #define CLK_LCD (1 << 28) 213 #define CLK_IPU (1 << 29) 214 #define CLK_DDR0 (1 << 30) 215 #define CLK_DDR1 (1 << 31) 216 217#define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ 218 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 219 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 220 #define OPCR_L2CM_M 0x0c000000 221 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 222 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 223 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 224 #define OPCR_SPENDN0 0x00000080 /* OTG port forced down */ 225 #define OPCR_SPENDN1 0x00000040 /* UHC port forced down */ 226 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 227 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 228 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 229 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 230 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 231 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 232#define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ 233 #define CLK_SMB3 (1 << 0) 234 #define CLK_TSSI1 (1 << 1) 235 #define CLK_VPU (1 << 2) 236 #define CLK_PCM (1 << 3) 237 #define CLK_GPU (1 << 4) 238 #define CLK_COMPRESS (1 << 5) 239 #define CLK_AIC1 (1 << 6) 240 #define CLK_GPVLC (1 << 7) 241 #define CLK_OTG1 (1 << 8) 242 #define CLK_HDMI (1 << 9) 243 #define CLK_UART4 (1 << 10) 244 #define CLK_AHB_MON (1 << 11) 245 #define CLK_SMB4 (1 << 12) 246 #define CLK_DES (1 << 13) 247 #define CLK_X2D (1 << 14) 248 #define CLK_P1 (1 << 15) 249 250#define JZ_USBPCR 0x1000003c 251 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 252 #define PCR_AVLD_REG 0x40000000 253 #define PCR_IDPULLUP_MASK 0x30000000 254 #define PCR_INCR_MASK 0x08000000 255 #define PCR_TCRISETUNE 0x04000000 256 #define PCR_COMMONONN 0x02000000 257 #define PCR_VBUSVLDEXT 0x01000000 258 #define PCR_VBUSVLDEXTSEL 0x00800000 259 #define PCR_POR 0x00400000 260 #define PCR_SIDDQ 0x00200000 261 #define PCR_OTG_DISABLE 0x00100000 262 #define PCR_COMPDISTN_M 0x000e0000 263 #define PCR_OTGTUNE 0x0001c000 264 #define PCR_SQRXTUNE 0x00003800 265 #define PCR_TXFSLSTUNE 0x00000780 266 #define PCR_TXPREEMPHTUNE 0x00000040 267 #define PCR_TXHSXVTUNE 0x00000030 268 #define PCR_TXVREFTUNE 0x0000000f 269#define JZ_USBRDT 0x10000040 /* Reset Detect Timer Register */ 270#define JZ_USBPCR1 0x10000048 271 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 272 #define PCR_REFCLK_CORE 0x0c000000 273 #define PCR_REFCLK_XO25 0x04000000 274 #define PCR_REFCLK_CO 0x00000000 275 #define PCR_CLK_M 0x03000000 /* clock */ 276 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 277 #define PCR_CLK_48 0x02000000 /* 48MHz */ 278 #define PCR_CLK_24 0x01000000 /* 24MHz */ 279 #define PCR_CLK_12 0x00000000 /* 12MHz */ 280 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 281 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 282 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 283 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 284 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 285 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 286 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 287 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 288 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 289 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 290 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 291 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 292 #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */ 293 294#define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */ 295#define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */ 296#define JZ_SPCR1 0x100000bc 297#define JZ_SRBC 0x100000c4 /* Soft Reset & Bus Control */ 298 299/* interrupt controller */ 300#define JZ_ICSR0 0x10001000 /* raw IRQ line status */ 301#define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */ 302#define JZ_ICMSR0 0x10001008 /* sets bits in mask register */ 303#define JZ_ICMCR0 0x1000100c /* clears bits in mask register */ 304#define JZ_ICPR0 0x10001010 /* line status after masking */ 305 306#define JZ_ICSR1 0x10001020 /* raw IRQ line status */ 307#define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */ 308#define JZ_ICMSR1 0x10001028 /* sets bits in mask register */ 309#define JZ_ICMCR1 0x1000102c /* clears bits in maks register */ 310#define JZ_ICPR1 0x10001030 /* line status after masking */ 311 312#define JZ_DSR0 0x10001034 /* source for PDMA */ 313#define JZ_DMR0 0x10001038 /* mask for PDMA */ 314#define JZ_DPR0 0x1000103c /* pending for PDMA */ 315 316#define JZ_DSR1 0x10001040 /* source for PDMA */ 317#define JZ_DMR1 0x10001044 /* mask for PDMA */ 318#define JZ_DPR1 0x10001048 /* pending for PDMA */ 319 320/* memory controller */ 321#define JZ_DMMAP0 0x13010024 322#define JZ_DMMAP1 0x13010028 323 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 324 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 325 * constant */ 326/* USB controllers */ 327#define JZ_EHCI_BASE 0x13490000 328#define JZ_OHCI_BASE 0x134a0000 329#define JZ_DWC2_BASE 0x13500000 330 331/* Ethernet */ 332#define JZ_DME_BASE 0x16000000 333#define JZ_DME_IO 0 334#define JZ_DME_DATA 2 335 336/* GPIO */ 337#define JZ_GPIO_A_BASE 0x10010000 338#define JZ_GPIO_B_BASE 0x10010100 339#define JZ_GPIO_C_BASE 0x10010200 340#define JZ_GPIO_D_BASE 0x10010300 341#define JZ_GPIO_E_BASE 0x10010400 342#define JZ_GPIO_F_BASE 0x10010500 343 344/* GPIO registers per port */ 345#define JZ_GPIO_PIN 0x00000000 /* pin level register */ 346/* 0 - normal gpio, 1 - interrupt */ 347#define JZ_GPIO_INT 0x00000010 /* interrupt register */ 348#define JZ_GPIO_INTS 0x00000014 /* interrupt set register */ 349#define JZ_GPIO_INTC 0x00000018 /* interrupt clear register */ 350/* 351 * INT == 1: 1 disables interrupt 352 * INT == 0: device select, see below 353 */ 354#define JZ_GPIO_MASK 0x00000020 /* port mask register */ 355#define JZ_GPIO_MASKS 0x00000024 /* port mask set register */ 356#define JZ_GPIO_MASKC 0x00000028 /* port mask clear register */ 357/* 358 * INT == 1: 0 - level triggered, 1 - edge triggered 359 * INT == 0: 0 - device select, see below 360 */ 361#define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */ 362#define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */ 363#define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */ 364/* 365 * INT == 1: 366 * PAT1 == 0: 0 - trigger on low, 1 - trigger on high 367 * PAT1 == 1: 0 - trigger on falling edge, 1 - trigger on rising edge 368 * INT == 0: 369 * MASK == 0: 370 * PAT1 == 0: 0 - device 0, 1 - device 1 371 * PAT1 == 1: 0 - device 2, 1 - device 3 372 * MASK == 1: 373 * PAT1 == 0: set gpio output 374 * PAT1 == 1: pin is input 375 */ 376#define JZ_GPIO_PAT0 0x00000040 /* pattern 0 register */ 377#define JZ_GPIO_PAT0S 0x00000044 /* pattern 0 set register */ 378#define JZ_GPIO_PAT0C 0x00000048 /* pattern 0 clear register */ 379/* 1 - interrupt happened */ 380#define JZ_GPIO_FLAG 0x00000050 /* flag register */ 381#define JZ_GPIO_FLAGC 0x00000058 /* flag clear register */ 382/* 1 - disable pull up/down resistors */ 383#define JZ_GPIO_DPULL 0x00000070 /* pull disable register */ 384#define JZ_GPIO_DPULLS 0x00000074 /* pull disable set register */ 385#define JZ_GPIO_DPULLC 0x00000078 /* pull disable clear register */ 386/* the following are uncommented in the manual */ 387#define JZ_GPIO_DRVL 0x00000080 /* drive low register */ 388#define JZ_GPIO_DRVLS 0x00000084 /* drive low set register */ 389#define JZ_GPIO_DRVLC 0x00000088 /* drive low clear register */ 390#define JZ_GPIO_DIR 0x00000090 /* direction register */ 391#define JZ_GPIO_DIRS 0x00000094 /* direction register */ 392#define JZ_GPIO_DIRC 0x00000098 /* direction register */ 393#define JZ_GPIO_DRVH 0x000000a0 /* drive high register */ 394#define JZ_GPIO_DRVHS 0x000000a4 /* drive high set register */ 395#define JZ_GPIO_DRVHC 0x000000a8 /* drive high clear register */ 396 397static inline void 398gpio_as_output(uint32_t g, int pin) 399{ 400 uint32_t mask = 1 << pin; 401 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 402 403 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 404 writereg(reg + JZ_GPIO_MASKS, mask); 405 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */ 406} 407 408static inline void 409gpio_set(uint32_t g, int pin, int level) 410{ 411 uint32_t mask = 1 << pin; 412 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 413 414 reg += (level == 0) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S; 415 writereg(reg, mask); 416} 417 418static inline void 419gpio_as_dev0(uint32_t g, int pin) 420{ 421 uint32_t mask = 1 << pin; 422 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 423 424 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 425 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 426 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */ 427 writereg(reg + JZ_GPIO_PAT0C, mask); 428} 429 430static inline void 431gpio_as_dev1(uint32_t g, int pin) 432{ 433 uint32_t mask = 1 << pin; 434 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 435 436 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 437 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 438 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */ 439 writereg(reg + JZ_GPIO_PAT0S, mask); 440} 441 442static inline void 443gpio_as_dev2(uint32_t g, int pin) 444{ 445 uint32_t mask = 1 << pin; 446 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 447 448 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 449 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 450 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */ 451 writereg(reg + JZ_GPIO_PAT0C, mask); 452} 453 454static inline void 455gpio_as_dev3(uint32_t g, int pin) 456{ 457 uint32_t mask = 1 << pin; 458 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 459 460 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 461 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 462 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */ 463 writereg(reg + JZ_GPIO_PAT0S, mask); 464} 465 466static inline void 467gpio_as_intr_level(uint32_t g, int pin) 468{ 469 uint32_t mask = 1 << pin; 470 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 471 472 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 473 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 474 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 475 writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */ 476 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 477 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 478} 479 480/* I2C / SMBus */ 481#define JZ_SMB0_BASE 0x10050000 482#define JZ_SMB1_BASE 0x10051000 483#define JZ_SMB2_BASE 0x10052000 484#define JZ_SMB3_BASE 0x10053000 485#define JZ_SMB4_BASE 0x10054000 486 487/* SMBus register offsets, per port */ 488#define JZ_SMBCON 0x00 /* SMB control */ 489 #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ 490 #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ 491 #define JZ_REST 0x20 /* 1 - allow RESTART */ 492 #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ 493 #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ 494 #define JZ_SPD_M 0x06 /* bus speed control */ 495 #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ 496 #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ 497 #define JZ_MD 0x01 /* enable master */ 498#define JZ_SMBTAR 0x04 /* SMB target address */ 499 #define JZ_SMATP 0x1000 /* enable 10bit master addr */ 500 #define JZ_SPECIAL 0x0800 /* 1 - special command */ 501 #define JZ_START 0x0400 /* 1 - send START */ 502 #define JZ_SMBTAR_M 0x03ff /* target address */ 503#define JZ_SMBSAR 0x08 /* SMB slave address */ 504#define JZ_SMBDC 0x10 /* SMB data buffer and command */ 505 #define JZ_CMD 0x100 /* 1 - read, 0 - write */ 506 #define JZ_DATA 0x0ff 507#define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ 508#define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ 509#define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ 510#define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ 511#define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ 512 #define JZ_ISTT 0x400 /* START or RESTART occured */ 513 #define JZ_ISTP 0x200 /* STOP occured */ 514 #define JZ_TXABT 0x40 /* ABORT occured */ 515 #define JZ_TXEMP 0x10 /* TX FIFO is low */ 516 #define JZ_TXOF 0x08 /* TX FIFO is high */ 517 #define JZ_RXFL 0x04 /* RX FIFO is at JZ_SMBRXTL*/ 518 #define JZ_RXOF 0x02 /* RX FIFO is high */ 519 #define JZ_RXUF 0x01 /* RX FIFO underflow */ 520#define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ 521#define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ 522#define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ 523#define JZ_SMBCINT 0x40 /* Clear Interrupts */ 524 #define JZ_CLEARALL 0x01 525#define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ 526#define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ 527#define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ 528#define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ 529#define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ 530#define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ 531#define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ 532#define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ 533#define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ 534#define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ 535#define JZ_SMBENB 0x6C /* SMB Enable */ 536 #define JZ_ENABLE 0x01 537#define JZ_SMBST 0x70 /* SMB Status register */ 538 #define JZ_SLVACT 0x40 /* slave is active */ 539 #define JZ_MSTACT 0x20 /* master is active */ 540 #define JZ_RFF 0x10 /* RX FIFO is full */ 541 #define JZ_RFNE 0x08 /* RX FIFO not empty */ 542 #define JZ_TFE 0x04 /* TX FIFO is empty */ 543 #define JZ_TFNF 0x02 /* TX FIFO is not full */ 544 #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ 545#define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ 546#define JZ_SMBDMACR 0x88 /* DMA Control Register */ 547#define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ 548#define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ 549#define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ 550#define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ 551#define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ 552#define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ 553 #define JZ_HDENB 0x100 /* enable hold time */ 554 555/* SD/MMC hosts */ 556#define JZ_MSC0_BASE 0x13450000 557#define JZ_MSC1_BASE 0x13460000 558#define JZ_MSC2_BASE 0x13470000 559 560#endif /* INGENIC_REGS_H */ 561