ingenic_regs.h revision 1.1 
1/*	$NetBSD: ingenic_regs.h,v 1.1 2014/11/22 15:17:01 macallan Exp $ */
2
3/*-
4 * Copyright (c) 2014 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <mips/locore.h>
30
31#ifndef INGENIC_REGS_H
32#define INGENIC_REGS_H
33
34/* UARTs, mostly 16550 compatible with 32bit spaced registers */
35#define JZ_UART0 0x10030000
36#define JZ_UART1 0x10031000
37#define JZ_UART2 0x10032000
38#define JZ_UART3 0x10033000
39#define JZ_UART4 0x10034000
40
41/* watchdog */
42#define JZ_WDOG_TDR	0x10002000	/* compare */
43#define JZ_WDOG_TCER	0x10002004
44	#define TCER_ENABLE	0x01	/* enable counter */
45#define JZ_WDOG_TCNT	0x10002008	/* 16bit up count */
46#define JZ_WDOG_TCSR	0x1000200c
47	#define TCSR_PCK_EN	0x01	/* PCLK */
48	#define TCSR_RTC_EN	0x02	/* RTCCLK - 32.768kHz */
49	#define TCSR_EXT_EN	0x04	/* EXTCLK - 12MHz? */
50	#define TCSR_PRESCALE_M	0x38
51	#define TCSR_DIV_1	0x00
52	#define TCSR_DIV_4	0x08
53	#define TCSR_DIV_16	0x10
54	#define TCSR_DIV_64	0x18
55	#define TCSR_DIV_256	0x20
56	#define TCSR_DIV_1024	0x28
57
58/* timers and PWMs */
59#define JZ_TC_TER	0x10002010	/* TC enable reg, ro */
60#define JZ_TC_TESR	0x10002014	/* TC enable set reg. */
61	#define TESR_TCST0	0x0001	/* enable counter 0 */
62	#define TESR_TCST1	0x0002	/* enable counter 1 */
63	#define TESR_TCST2	0x0004	/* enable counter 2 */
64	#define TESR_TCST3	0x0008	/* enable counter 3 */
65	#define TESR_TCST4	0x0010	/* enable counter 4 */
66	#define TESR_TCST5	0x0014	/* enable counter 5 */
67	#define TESR_TCST6	0x0018	/* enable counter 6 */
68	#define TESR_TCST7	0x001c	/* enable counter 7 */
69	#define TESR_OST	0x8000	/* enable OST */
70#define JZ_TC_TECR	0x10002018	/* TC enable clear reg. */
71
72/* operating system timer */
73#define JZ_OST_DATA	0x100020e0	/* compare */
74#define JZ_OST_CNT_LO	0x100020e4
75#define JZ_OST_CNT_HI	0x100020e8
76#define JZ_OST_CTRL	0x100020ec
77	#define OSTC_PCK_EN	0x0001	/* use PCLK */
78	#define OSTC_RTC_EN	0x0002	/* use RTCCLK */
79	#define OSTC_EXT_EN	0x0004	/* use EXTCLK */
80	#define OSTC_PRESCALE_M	0x0038
81	#define OSTC_DIV_1	0x0000
82	#define OSTC_DIV_4	0x0008
83	#define OSTC_DIV_16	0x0010
84	#define OSTC_DIV_64	0x0018
85	#define OSTC_DIV_256	0x0020
86	#define OSTC_DIV_1024	0x0028
87	#define OSTC_SHUTDOWN	0x0200
88	#define OSTC_MODE	0x8000	/* 0 - reset to 0 when = OST_DATA */
89#define JZ_OST_CNT_U32	0x100020fc	/* copy of CNT_HI when reading CNT_LO */
90
91static inline void
92writereg(uint32_t reg, uint32_t val)
93{
94	*(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
95	wbflush();
96}
97
98static inline uint32_t
99readreg(uint32_t reg)
100{
101	wbflush();
102	return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
103}
104
105#endif /* INGENIC_REGS_H */