1/*	$NetBSD: mainbus.c,v 1.10 2021/09/06 14:03:18 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2007
5 *      Internet Initiative Japan, Inc.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.10 2021/09/06 14:03:18 jmcneill Exp $");
31
32#define	_MIPS_BUS_DMA_PRIVATE
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/device.h>
37#include <sys/bus.h>
38
39#include <mips/cavium/include/mainbusvar.h>
40#include <mips/cavium/octeonvar.h>
41
42#include <dev/fdt/fdtvar.h>
43
44static int	mainbus_match(device_t, struct cfdata *, void *);
45static void	mainbus_attach(device_t, device_t, void *);
46static void	mainbus_attach_static(device_t);
47static void	mainbus_attach_devicetree(device_t);
48static int	mainbus_submatch(device_t, cfdata_t, const int *, void *);
49static int	mainbus_print(void *, const char *);
50
51static void	simplebus_bus_io_init(bus_space_tag_t, void *);
52
53CFATTACH_DECL_NEW(mainbus, sizeof(device_t), mainbus_match, mainbus_attach,
54    NULL, NULL);
55
56static struct mips_bus_space simplebus_bus_tag;
57
58static struct mips_bus_dma_tag simplebus_dma_tag = {
59	._cookie = NULL,
60	._wbase = 0,
61	._bounce_alloc_lo = 0,
62	._bounce_alloc_hi = 0,
63	._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
64	._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
65	._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
66};
67
68static int
69mainbus_match(device_t parent, struct cfdata *match, void *aux)
70{
71	static int once = 0;
72
73	if (once != 0)
74		return 0;
75	once = 1;
76
77	return 1;
78}
79
80static void
81mainbus_attach(device_t parent, device_t self, void *aux)
82{
83	aprint_normal("\n");
84
85	if (fdtbus_get_data() != NULL) {
86		mainbus_attach_devicetree(self);
87	} else {
88		mainbus_attach_static(self);
89	}
90}
91
92static void
93mainbus_attach_static(device_t self)
94{
95	struct mainbus_attach_args aa;
96	int i;
97
98	for (i = 0; i < (int)mainbus_ndevs; i++) {
99		aa.aa_name = mainbus_devs[i];
100		config_found(self, &aa, mainbus_print,
101		    CFARGS(.submatch = mainbus_submatch,
102			   .iattr = "mainbus"));
103	}
104}
105
106extern struct octeon_config octeon_configuration;
107extern void octpow_bootstrap(struct octeon_config *);
108extern void octfpa_bootstrap(struct octeon_config *);
109
110static void
111mainbus_attach_devicetree(device_t self)
112{
113	const struct fdt_console *cons = fdtbus_get_console();
114	struct mainbus_attach_args aa;
115	struct fdt_attach_args faa;
116	u_int uart_freq;
117
118	aa.aa_name = "cpunode";
119	config_found(self, &aa, mainbus_print,
120	    CFARGS(.submatch = mainbus_submatch,
121		   .iattr = "mainbus"));
122
123	aa.aa_name = "iobus";
124	config_found(self, &aa, mainbus_print,
125	    CFARGS(.submatch = mainbus_submatch,
126		   .iattr = "mainbus"));
127
128	simplebus_bus_io_init(&simplebus_bus_tag, NULL);
129
130	faa.faa_bst = &simplebus_bus_tag;
131	faa.faa_dmat = &simplebus_dma_tag;
132	faa.faa_name = "";
133
134	if (cons != NULL) {
135		faa.faa_phandle = fdtbus_get_stdout_phandle();
136
137		if (of_getprop_uint32(faa.faa_phandle, "clock-frequency",
138		    &uart_freq) != 0) {
139			uart_freq = octeon_ioclock_speed();
140		}
141
142		if (uart_freq > 0)
143			delay(640000000 / uart_freq);
144
145		cons->consinit(&faa, uart_freq);
146	}
147
148	faa.faa_phandle = OF_peer(0);
149	config_found(self, &faa, NULL,
150	    CFARGS(.iattr = "fdt"));
151}
152
153static int
154mainbus_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux)
155{
156	struct mainbus_attach_args *aa = aux;
157
158	if (strcmp(cf->cf_name, aa->aa_name) != 0)
159		return 0;
160
161	return config_match(parent, cf, aux);
162}
163
164static int
165mainbus_print(void *aux, const char *pnp)
166{
167	struct mainbus_attach_args *aa = aux;
168
169	if (pnp != 0)
170		return QUIET;
171
172	if (pnp)
173		aprint_normal("%s at %s", aa->aa_name, pnp);
174
175	return UNCONF;
176}
177
178/* ---- bus_space(9) */
179#define	CHIP			simplebus
180#define	CHIP_IO
181#define	CHIP_ACCESS_SIZE	8
182
183#define	CHIP_W1_BUS_START(v)	0x0000000000000000ULL
184#define	CHIP_W1_BUS_END(v)	0x7fffffffffffffffULL
185#define	CHIP_W1_SYS_START(v)	0x8000000000000000ULL
186#define	CHIP_W1_SYS_END(v)	0xffffffffffffffffULL
187
188#include <mips/mips/bus_space_alignstride_chipdep.c>
189
190bus_space_tag_t
191fdtbus_bus_tag_create(int phandle, uint32_t flags)
192{
193	return &simplebus_bus_tag;
194}
195