1/* $NetBSD: octeon_uartreg.h,v 1.2 2019/04/11 11:40:58 kamil Exp $ */ 2 3/* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * UART Registers 31 */ 32 33#ifndef _OCTEON_UARTREG_H_ 34#define _OCTEON_UARTREG_H_ 35 36/* ---- register addresses */ 37 38#define MIO_UART0_RBR 0x0001180000000800ULL 39#define MIO_UART0_IER 0x0001180000000808ULL 40#define MIO_UART0_IIR 0x0001180000000810ULL 41#define MIO_UART0_LCR 0x0001180000000818ULL 42#define MIO_UART0_MCR 0x0001180000000820ULL 43#define MIO_UART0_LSR 0x0001180000000828ULL 44#define MIO_UART0_MSR 0x0001180000000830ULL 45#define MIO_UART0_SCR 0x0001180000000838ULL 46#define MIO_UART0_THR 0x0001180000000840ULL 47#define MIO_UART0_FCR 0x0001180000000850ULL 48#define MIO_UART0_DLL 0x0001180000000880ULL 49#define MIO_UART0_DLH 0x0001180000000888ULL 50#define MIO_UART0_FAR 0x0001180000000920ULL 51#define MIO_UART0_TFR 0x0001180000000928ULL 52#define MIO_UART0_RFW 0x0001180000000930ULL 53#define MIO_UART0_USR 0x0001180000000938ULL 54#define MIO_UART0_TFL 0x0001180000000a00ULL 55#define MIO_UART0_RFL 0x0001180000000a08ULL 56#define MIO_UART0_SRR 0x0001180000000a10ULL 57#define MIO_UART0_SRTS 0x0001180000000a18ULL 58#define MIO_UART0_SBCR 0x0001180000000a20ULL 59#define MIO_UART0_SFE 0x0001180000000a30ULL 60#define MIO_UART0_SRT 0x0001180000000a38ULL 61#define MIO_UART0_STT 0x0001180000000b00ULL 62#define MIO_UART0_HTX 0x0001180000000b08ULL 63#define MIO_UART1_RBR 0x0001180000000c00ULL 64#define MIO_UART1_IER 0x0001180000000c08ULL 65#define MIO_UART1_IIR 0x0001180000000c10ULL 66#define MIO_UART1_LCR 0x0001180000000c18ULL 67#define MIO_UART1_MCR 0x0001180000000c20ULL 68#define MIO_UART1_LSR 0x0001180000000c28ULL 69#define MIO_UART1_MSR 0x0001180000000c30ULL 70#define MIO_UART1_SCR 0x0001180000000c38ULL 71#define MIO_UART1_THR 0x0001180000000c40ULL 72#define MIO_UART1_FCR 0x0001180000000c50ULL 73#define MIO_UART1_DLL 0x0001180000000c80ULL 74#define MIO_UART1_DLH 0x0001180000000c88ULL 75#define MIO_UART1_FAR 0x0001180000000d20ULL 76#define MIO_UART1_TFR 0x0001180000000d28ULL 77#define MIO_UART1_RFW 0x0001180000000d30ULL 78#define MIO_UART1_USR 0x0001180000000d38ULL 79#define MIO_UART1_TFL 0x0001180000000e00ULL 80#define MIO_UART1_RFL 0x0001180000000e08ULL 81#define MIO_UART1_SRR 0x0001180000000e10ULL 82#define MIO_UART1_SRTS 0x0001180000000e18ULL 83#define MIO_UART1_SBCR 0x0001180000000e20ULL 84#define MIO_UART1_SFE 0x0001180000000e30ULL 85#define MIO_UART1_SRT 0x0001180000000e38ULL 86#define MIO_UART1_STT 0x0001180000000f00ULL 87#define MIO_UART1_HTX 0x0001180000000f08ULL 88 89/* ---- snprintb */ 90 91/* XXX */ 92 93/* ---- bus_space */ 94 95#define MIO_UART0_BASE 0x0001180000000800ULL 96#define MIO_UART1_BASE 0x0001180000000c00ULL 97 98#define MIO_UART_RBR_OFFSET 0x0000 99#define MIO_UART_IER_OFFSET 0x0008 100#define MIO_UART_IIR_OFFSET 0x0010 101#define MIO_UART_LCR_OFFSET 0x0018 102#define MIO_UART_MCR_OFFSET 0x0020 103#define MIO_UART_LSR_OFFSET 0x0028 104#define MIO_UART_MSR_OFFSET 0x0030 105#define MIO_UART_SCR_OFFSET 0x0038 106#define MIO_UART_THR_OFFSET 0x0040 107#define MIO_UART_FCR_OFFSET 0x0050 108#define MIO_UART_DLL_OFFSET 0x0080 109#define MIO_UART_DLH_OFFSET 0x0088 110#define MIO_UART_FAR_OFFSET 0x0120 111#define MIO_UART_TFR_OFFSET 0x0128 112#define MIO_UART_RFW_OFFSET 0x0130 113#define MIO_UART_USR_OFFSET 0x0138 114#define MIO_UART_TFL_OFFSET 0x0200 115#define MIO_UART_RFL_OFFSET 0x0208 116#define MIO_UART_SRR_OFFSET 0x0210 117#define MIO_UART_SRTS_OFFSET 0x0218 118#define MIO_UART_SBCR_OFFSET 0x0220 119#define MIO_UART_SFE_OFFSET 0x0230 120#define MIO_UART_SRT_OFFSET 0x0238 121#define MIO_UART_STT_OFFSET 0x0300 122#define MIO_UART_HTX_OFFSET 0x0308 123 124#endif /* _OCTEON_UARTREG_H_ */ 125