1/*	$NetBSD: octeon_uart.c,v 1.10 2022/01/26 18:57:55 martin Exp $	*/
2
3/*
4 * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.10 2022/01/26 18:57:55 martin Exp $");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/types.h>
35#include <sys/device.h>
36#include <sys/tty.h>
37
38#include <sys/bus.h>
39#include <sys/cpu.h>
40#include <machine/intr.h>
41
42#include <dev/cons.h>
43#include <dev/ic/comreg.h>
44#include <dev/ic/comvar.h>
45
46#include <mips/cavium/include/iobusvar.h>
47#include <mips/cavium/dev/octeon_uartreg.h>
48#include <mips/cavium/dev/octeon_uartvar.h>
49#include <mips/cavium/dev/octeon_ciureg.h>
50
51struct octuart_iobus_softc {
52	struct com_softc sc_com;
53	int sc_irq;
54	void *sc_ih;
55};
56
57static int	octuart_iobus_match(device_t, struct cfdata *, void *);
58static void	octuart_iobus_attach(device_t, device_t, void *);
59static int	octuart_com_enable(struct com_softc *);
60static void	octuart_com_disable(struct com_softc *);
61
62/* octputc() is not declared static so it can be used for debugging elsewhere */
63void		octputc(dev_t, int);
64
65/* XXX */
66const bus_addr_t octuart_com_bases[] = {
67	MIO_UART0_BASE,
68	MIO_UART1_BASE
69};
70const struct com_regs octuart_com_regs = {
71	.cr_map = {
72		[COM_REG_RXDATA] =	MIO_UART_RBR_OFFSET,
73		[COM_REG_TXDATA] =	MIO_UART_THR_OFFSET,
74		[COM_REG_DLBL] =	MIO_UART_DLL_OFFSET,
75		[COM_REG_DLBH] =	MIO_UART_DLH_OFFSET,
76		[COM_REG_IER] =		MIO_UART_IER_OFFSET,
77		[COM_REG_IIR] =		MIO_UART_IIR_OFFSET,
78		[COM_REG_FIFO] =	MIO_UART_FCR_OFFSET,
79		[COM_REG_EFR] =		0,
80		[COM_REG_LCR] =		MIO_UART_LCR_OFFSET,
81		[COM_REG_MCR] =		MIO_UART_MCR_OFFSET,
82		[COM_REG_LSR] =		MIO_UART_LSR_OFFSET,
83		[COM_REG_MSR] =		MIO_UART_MSR_OFFSET,
84#if 0 /* XXX COM_TYPE_16750_NOERS */
85		[COM_REG_USR] =		MIO_UART_USR_OFFSET,
86		[COM_REG_SRR] =		MIO_UART_SRR_OFFSET
87#endif
88	}
89};
90
91CFATTACH_DECL_NEW(com_iobus, sizeof(struct octuart_iobus_softc),
92    octuart_iobus_match, octuart_iobus_attach, NULL, NULL);
93
94static int
95octuart_iobus_match(device_t parent, struct cfdata *cf, void *aux)
96{
97	struct iobus_attach_args *aa = aux;
98	int result = 0;
99
100	if (strcmp(cf->cf_name, aa->aa_name) != 0)
101		goto out;
102	if (cf->cf_unit != aa->aa_unitno)
103		goto out;
104	result = 1;
105
106out:
107	return result;
108}
109
110static void
111octuart_iobus_attach(device_t parent, device_t self, void *aux)
112{
113	struct octuart_iobus_softc *sc = device_private(self);
114	struct com_softc *sc_com = &sc->sc_com;
115	struct iobus_attach_args *aa = aux;
116	int status;
117
118	sc_com->sc_dev = self;
119	com_init_regs(&sc_com->sc_regs, aa->aa_bust, 0, aa->aa_unit->addr);
120	memcpy(sc_com->sc_regs.cr_map, octuart_com_regs.cr_map,
121	    sizeof(octuart_com_regs.cr_map));
122
123	sc->sc_irq = aa->aa_unit->irq;
124
125	status = bus_space_map(
126		aa->aa_bust,
127		aa->aa_unit->addr,
128		COM_NPORTS,
129		0,
130		&sc_com->sc_regs.cr_ioh);
131	if (status != 0) {
132		aprint_error(": can't map i/o space\n");
133		return;
134	}
135
136	sc_com->sc_type = COM_TYPE_16550_NOERS;
137	sc_com->sc_frequency = octeon_ioclock_speed();
138	sc_com->enable = octuart_com_enable;
139	sc_com->disable = octuart_com_disable;
140
141	octuart_com_enable(sc_com);
142	sc_com->enabled = 1;
143
144	com_attach_subr(sc_com);
145
146	sc->sc_ih = octeon_intr_establish(CIU_INT_UART_0 + device_unit(self),
147	    IPL_SERIAL, comintr, sc_com);
148	if (sc->sc_ih == NULL)
149		panic("%s: can't establish interrupt\n",
150		    device_xname(self));
151
152	/* XXX disable if kgdb? */
153}
154
155static int
156octuart_com_enable(struct com_softc *sc_com)
157{
158	struct com_regs *regsp = &sc_com->sc_regs;
159
160	/* XXX Clear old busy detect interrupts */
161	bus_space_read_1(regsp->cr_iot, regsp->cr_ioh,
162	    MIO_UART_USR_OFFSET);
163
164	return 0;
165}
166
167static void
168octuart_com_disable(struct com_softc *sc_com)
169{
170	/*
171	 * XXX chip specific procedure
172	 */
173}
174
175
176#ifndef CONMODE
177#define	CONMODE	((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
178#endif
179
180int
181octuart_com_cnattach(bus_space_tag_t bust, int portno, int speed)
182{
183	struct com_regs regs;
184
185	com_init_regs(&regs, bust, 0, octuart_com_bases[portno]);
186	memcpy(regs.cr_map, octuart_com_regs.cr_map,
187	    sizeof(octuart_com_regs.cr_map));
188
189	return comcnattach1(
190		&regs,
191		speed,
192		octeon_ioclock_speed(),
193		COM_TYPE_16550_NOERS,
194		CONMODE);
195}
196
197
198/*
199 * A very simple output-only console so early printf() can work.
200 */
201struct consdev early_console = {
202	.cn_putc = octputc,
203	.cn_pollc = nullcnpollc,
204	.cn_dev = makedev(0, 0),
205	.cn_pri = CN_DEAD
206};
207static int early_comcnrate;
208
209void
210octputc(dev_t dev, int c)
211{
212
213	octeon_xkphys_write_8(MIO_UART0_RBR, (uint8_t)c);
214	delay(1000000 / (early_comcnrate / 10)); /* wait for char to drain */
215}
216
217void
218octuart_early_cnattach(int rate)
219{
220
221	early_comcnrate = rate;
222	cn_tab = &early_console;
223}
224