com_aubus.c revision 1.6
1/* $NetBSD: com_aubus.c,v 1.6 2011/07/01 18:39:29 dyoung Exp $ */ 2 3/* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <sys/cdefs.h> 39__KERNEL_RCSID(0, "$NetBSD: com_aubus.c,v 1.6 2011/07/01 18:39:29 dyoung Exp $"); 40 41#include <sys/param.h> 42#include <sys/device.h> 43#include <sys/lwp.h> 44#include <sys/systm.h> 45#include <sys/tty.h> 46 47#include <sys/bus.h> 48#include <dev/ic/comvar.h> 49 50#include <mips/alchemy/include/aureg.h> 51#include <mips/alchemy/include/auvar.h> 52#include <mips/alchemy/include/aubusvar.h> 53#include <mips/alchemy/dev/com_aubus_reg.h> 54 55struct com_aubus_softc { 56 struct com_softc sc_com; 57 int sc_irq; 58 void *sc_ih; 59}; 60 61static int com_aubus_probe(device_t, cfdata_t , void *); 62static void com_aubus_attach(device_t, device_t, void *); 63static int com_aubus_enable(struct com_softc *); 64static void com_aubus_disable(struct com_softc *); 65static void com_aubus_initmap(struct com_regs *); 66 67CFATTACH_DECL_NEW(com_aubus, sizeof(struct com_aubus_softc), 68 com_aubus_probe, com_aubus_attach, NULL, NULL); 69 70#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 71 72#ifndef COM_REGMAP 73#error COM_REGMAP not defined! 74#endif 75 76int 77com_aubus_probe(device_t parent, cfdata_t cf, void *aux) 78{ 79 struct aubus_attach_args *aa = aux; 80 81 /* match only aucom devices */ 82 if (strcmp(aa->aa_name, cf->cf_name) == 0) 83 return (1); 84 85 return (0); 86} 87 88void 89com_aubus_attach(device_t parent, device_t self, void *aux) 90{ 91 struct com_aubus_softc *asc = device_private(self); 92 struct com_softc *sc = &asc->sc_com; 93 struct aubus_attach_args *aa = aux; 94 int addr = aa->aa_addr; 95 96 sc->sc_dev = self; 97 sc->sc_regs.cr_iot = aa->aa_st; 98 sc->sc_regs.cr_iobase = addr; 99 asc->sc_irq = aa->aa_irq[0]; 100 101 if (com_is_console(aa->aa_st, addr, &sc->sc_regs.cr_ioh) == 0 && 102 bus_space_map(aa->aa_st, addr, AUCOM_NPORTS, 0, 103 &sc->sc_regs.cr_ioh) != 0) { 104 aprint_error(": can't map i/o space\n"); 105 return; 106 } 107 com_aubus_initmap(&sc->sc_regs); 108 109 /* 110 * The input to the clock divider is the internal pbus clock (1/4 the 111 * processor frequency). The actual baud rate of the interface will 112 * be pbus_freq / CLKDIV. 113 */ 114 sc->sc_frequency = curcpu()->ci_cpu_freq / 4; 115 116 sc->sc_hwflags = COM_HW_NO_TXPRELOAD; 117 sc->sc_type = COM_TYPE_AU1x00; 118 119 sc->enable = com_aubus_enable; 120 sc->disable = com_aubus_disable; 121 122 /* Enable UART so we can access it. */ 123 com_aubus_enable(sc); 124 sc->enabled = 1; 125 126 /* Attach MI com driver. */ 127 com_attach_subr(sc); 128 129 /* Disable UART if it's not the console. (XXX kgdb?) */ 130 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 131 com_aubus_disable(sc); 132 sc->enabled = 0; 133 } 134} 135 136int 137com_aubus_enable(struct com_softc *sc) 138{ 139 struct com_aubus_softc *asc = (void *)sc; /* XXX mi prototype */ 140 141 /* Ignore requests to enable an already enabled console. */ 142 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && (asc->sc_ih != NULL)) 143 return (0); 144 145 /* Enable the UART module. */ 146 bus_space_write_1(sc->sc_regs.cr_iot, sc->sc_regs.cr_ioh, AUCOM_MODCTL, 147 UMC_ME | UMC_CE); 148 149 /* Establish the interrupt. */ 150 asc->sc_ih = au_intr_establish(asc->sc_irq, 0, IPL_SERIAL, IST_LEVEL, 151 comintr, sc); 152 if (asc->sc_ih == NULL) { 153 aprint_error_dev(sc->sc_dev, 154 "unable to establish interrupt\n"); 155 return (1); 156 } 157 158 return (0); 159} 160 161void 162com_aubus_disable(struct com_softc *sc) 163{ 164 struct com_aubus_softc *asc = (void *)sc; /* XXX mi prototype */ 165 166 /* Ignore requests to disable the console. */ 167 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 168 return; 169 170 /* Disestablish the interrupt. */ 171 au_intr_disestablish(asc->sc_ih); 172 173 /* Disable the UART module. */ 174 bus_space_write_1(sc->sc_regs.cr_iot, sc->sc_regs.cr_ioh, 175 AUCOM_MODCTL, 0); 176} 177 178void 179com_aubus_initmap(struct com_regs *regsp) 180{ 181 regsp->cr_nports = AUCOM_NPORTS; 182 regsp->cr_map[COM_REG_RXDATA] = AUCOM_RXDATA; 183 regsp->cr_map[COM_REG_TXDATA] = AUCOM_TXDATA; 184 regsp->cr_map[COM_REG_DLBL] = AUCOM_DLB; 185 regsp->cr_map[COM_REG_DLBH] = AUCOM_DLB; 186 regsp->cr_map[COM_REG_IER] = AUCOM_IER; 187 regsp->cr_map[COM_REG_IIR] = AUCOM_IIR; 188 regsp->cr_map[COM_REG_FIFO] = AUCOM_FIFO; 189 regsp->cr_map[COM_REG_EFR] = 0; 190 regsp->cr_map[COM_REG_LCR] = AUCOM_LCTL; 191 regsp->cr_map[COM_REG_MCR] = AUCOM_MCR; 192 regsp->cr_map[COM_REG_LSR] = AUCOM_LSR; 193 regsp->cr_map[COM_REG_MSR] = AUCOM_MSR; 194} 195 196int 197com_aubus_cnattach(bus_addr_t addr, int baud) 198{ 199 struct com_regs regs; 200 uint32_t sysfreq; 201 202 regs.cr_iot = aubus_st; 203 regs.cr_iobase = addr; 204 regs.cr_nports = AUCOM_NPORTS; 205 com_aubus_initmap(®s); 206 207 sysfreq = curcpu()->ci_cpu_freq / 4; 208 209 return comcnattach1(®s, baud, sysfreq, COM_TYPE_AU1x00, CONMODE); 210} 211