dbdma.c revision 1.3 
1/*	$NetBSD: dbdma.c,v 1.3 2000/06/29 08:10:45 mrg Exp $	*/
2
3/*
4 * Copyright 1991-1998 by Open Software Foundation, Inc.
5 *              All Rights Reserved
6 *
7 * Permission to use, copy, modify, and distribute this software and
8 * its documentation for any purpose and without fee is hereby granted,
9 * provided that the above copyright notice appears in all copies and
10 * that both the copyright notice and this permission notice appear in
11 * supporting documentation.
12 *
13 * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
14 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
15 * FOR A PARTICULAR PURPOSE.
16 *
17 * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
19 * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
20 * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
21 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 *
23 */
24
25#include <sys/param.h>
26#include <sys/malloc.h>
27#include <sys/systm.h>
28
29#include <uvm/uvm_extern.h>
30
31#include <machine/pio.h>
32#include <macppc/dev/dbdma.h>
33
34#define eieio() __asm__ volatile("eieio")
35
36
37static int	dbdma_alloc_index = 0;
38dbdma_command_t	*dbdma_alloc_commands = NULL;
39
40void
41dbdma_start(dmap, commands)
42	dbdma_regmap_t *dmap;
43	dbdma_command_t *commands;
44{
45	unsigned long addr = vtophys((vaddr_t)commands);
46
47	if (addr & 0xf)
48		panic("dbdma_start command structure not 16-byte aligned");
49
50	dmap->d_intselect = 0xff;  /* Endian magic - clear out interrupts */
51	DBDMA_ST4_ENDIAN(&dmap->d_control,
52			 DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE	|
53					     DBDMA_CNTRL_DEAD	|
54					     DBDMA_CNTRL_WAKE	|
55					     DBDMA_CNTRL_FLUSH	|
56					     DBDMA_CNTRL_PAUSE	|
57					     DBDMA_CNTRL_RUN      )));
58	eieio();
59
60	while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)
61		eieio();
62
63	dmap->d_cmdptrhi = 0;	eieio();/* 64-bit not yet */
64	DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr); eieio();
65
66	DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN));
67	eieio();
68}
69
70void
71dbdma_stop(dmap)
72	dbdma_regmap_t *dmap;
73{
74	out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |
75			  DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
76
77	while (in32rb(&dmap->d_status) &
78		(DBDMA_CNTRL_ACTIVE|DBDMA_CNTRL_FLUSH));
79}
80
81void
82dbdma_flush(dmap)
83	dbdma_regmap_t *dmap;
84{
85	out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
86
87	while (in32rb(&dmap->d_status) & (DBDMA_CNTRL_FLUSH));
88}
89
90void
91dbdma_reset(dmap)
92	dbdma_regmap_t *dmap;
93{
94	out32rb(&dmap->d_control,
95			 DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE	|
96					     DBDMA_CNTRL_DEAD	|
97					     DBDMA_CNTRL_WAKE	|
98					     DBDMA_CNTRL_FLUSH	|
99					     DBDMA_CNTRL_PAUSE	|
100					     DBDMA_CNTRL_RUN      )));
101
102	while (in32rb(&dmap->d_status) & DBDMA_CNTRL_RUN);
103}
104
105void
106dbdma_continue(dmap)
107	dbdma_regmap_t *dmap;
108{
109	out32rb(&dmap->d_control,
110		DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN | DBDMA_CNTRL_WAKE) |
111		DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_PAUSE | DBDMA_CNTRL_DEAD));
112}
113
114void
115dbdma_pause(dmap)
116	dbdma_regmap_t *dmap;
117{
118	DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE));
119	eieio();
120
121	while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)
122		eieio();
123}
124
125dbdma_command_t	*
126dbdma_alloc(size)
127	int size;
128{
129	u_int buf;
130
131	buf = (u_int)malloc(size + 0x0f, M_DEVBUF, M_WAITOK);
132	buf = (buf + 0x0f) & ~0x0f;
133
134	return (dbdma_command_t *)buf;
135}
136