1/*	$NetBSD: dig64.h,v 1.4 2022/07/21 14:27:46 andvar Exp $	*/
2
3/*-
4 * Copyright (c) 2002 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31#ifndef _MACHINE_DIG64_H_
32#define	_MACHINE_DIG64_H_
33
34/*
35 * This header file written refer to 'DIG64 Descriptions for Primary Console &
36 * Debug Port Devices'.
37 */
38
39/* ACPI GAS (Generic Address Structure) */
40struct dig64_gas {
41	uint8_t		addr_space;
42	uint8_t		bit_width;
43	uint8_t		bit_offset;
44	uint8_t		_reserved_;
45	/*
46	 * XXX using a 64-bit type for the address would cause padding and
47	 * using __packed would cause unaligned accesses...
48	 */
49	uint32_t	addr_low;
50	uint32_t	addr_high;
51};
52
53struct dig64_hcdp_entry {
54	uint8_t		type;
55#define	DIG64_HCDP_CONSOLE		DIG64_ENTRYTYPE_TYPE0
56#define	DIG64_HCDP_DBGPORT		DIG64_ENTRYTYPE_TYPE1
57	uint8_t		databits;
58	uint8_t		parity;
59#define	DIG64_HCDP_PARITY_NO		1
60#define	DIG64_HCDP_PARITY_EVEN		2
61#define	DIG64_HCDP_PARITY_ODD		3
62#define	DIG64_HCDP_PARITY_MARK		4
63#define	DIG64_HCDP_PARITY_SPACE		5
64	uint8_t		stopbits;
65#define	DIG64_HCDP_STOPBITS_1		1
66#define	DIG64_HCDP_STOPBITS_15		2
67#define	DIG64_HCDP_STOPBITS_2		3
68	uint8_t		pci_segment;
69	uint8_t		pci_bus;
70	uint8_t		pci_device:5;
71	uint8_t		_reserved1_:3;
72	uint8_t		pci_function:3;
73	uint8_t		_reserved2_:3;
74	uint8_t		interrupt:1;
75	uint8_t		pci_flag:1;
76	/*
77	 * XXX using a 64-bit type for the baudrate would cause padding and
78	 * using __packed would cause unaligned accesses...
79	 */
80	uint32_t	baud_low;
81	uint32_t	baud_high;
82	struct dig64_gas address;
83	uint16_t	pci_devid;
84	uint16_t	pci_vendor;
85	uint32_t	irq;
86	uint32_t	pclock;
87	uint8_t		pci_interface;
88	uint8_t		_reserved3_[7];
89};
90
91
92/* Device Specific Structures */
93
94struct dig64_vga_spec {
95	uint8_t		num;	/*Number of Extended Address Space Descriptors*/
96	struct {
97		uint8_t	data[56];
98	} edesc[0];
99} __packed;
100
101
102/* Interconnect Specific Structure */
103
104#define DIG64_FLAGS_INTR_LEVEL		(0 << 0)	/* Level Triggered */
105#define DIG64_FLAGS_INTR_EDGE		(1 << 0)	/* Edge Triggered */
106#define DIG64_FLAGS_INTR_ACTH		(0 << 1)	/* Intr Active High */
107#define DIG64_FLAGS_INTR_ACTL		(1 << 1)	/* Intr Active Low */
108#define DIG64_FLAGS_TRANS_DENSE		(0 << 3)	/* Dense Translation */
109#define DIG64_FLAGS_TRANS_SPARSE	(1 << 3)	/* Sparse Translation */
110#define DIG64_FLAGS_TYPE_STATIC		(0 << 4)	/* Type Static */
111#define DIG64_FLAGS_TYPE_TRANS		(1 << 4)	/* Type Translation */
112#define DIG64_FLAGS_INTR_SUPP		(1 << 6)	/* Interrupt supported */
113#define DIG64_FLAGS_MMIO_TRA_VALID	(1 << 8)
114#define DIG64_FLAGS_IOPORT_TRA_VALID	(1 << 9)
115
116struct dig64_acpi_spec {
117	uint8_t		type;		/* = 0 indicating ACPI */
118	uint8_t		resv;		/* must be 0 */
119	uint16_t	length;		/* of the ACPI Specific Structure */
120	uint32_t	uid;
121	uint32_t	hid;
122	uint32_t	acpi_gsi;	/* ACPI Global System Interrupt */
123	uint64_t	mmio_tra;
124	uint64_t	ioport_tra;
125	uint16_t	flags;
126} __packed;
127
128struct dig64_pci_spec {
129	uint8_t		type;		/* = 1 indicating PCI */
130	uint8_t		resv;		/* must be 0 */
131	uint16_t	length;		/* of the PCI Specific Structure */
132	uint8_t		sgn;		/* PCI Segment Group Number */
133	uint8_t		bus;		/* PCI Bus Number */
134	uint8_t		device;		/* PCI Device Number */
135	uint8_t		function;	/* PCI Function Number */
136	uint16_t	device_id;
137	uint16_t	vendor_id;
138	uint32_t	acpi_gsi;	/* ACPI Global System Interrupt */
139	uint64_t	mmio_tra;
140	uint64_t	ioport_tra;
141	uint16_t	flags;
142} __packed;
143
144
145struct dig64_pcdp_entry {
146	uint8_t		type;
147	uint8_t		primary;
148	uint16_t	length;		/* in bytes */
149	uint16_t	index;
150#define	DIG64_PCDP_CONOUTDEV		0
151#define	DIG64_PCDP_NOT_VALID		1
152#define	DIG64_PCDP_CONOUTDEV2		2
153#define	DIG64_PCDP_CONINDEV		3
154
155	union {
156		/*
157		 * Interconnect Specific Structure,
158		 *   and Device Specific Structure(s)
159		 */
160		uint8_t	type;
161#define DIG64_PCDP_SPEC_ACPI		0
162		struct dig64_acpi_spec acpi;
163#define DIG64_PCDP_SPEC_PCI		1
164		struct dig64_pci_spec pci;
165	} specs;
166} __packed;
167
168struct dig64_hcdp_table {
169	char		signature[4];
170#define	HCDP_SIGNATURE	"HCDP"
171	uint32_t	length;
172	uint8_t		revision;	/* It is PCDP, if '3' or greater. */
173	uint8_t		checksum;
174	char		oem_id[6];
175	char		oem_tbl_id[8];
176	uint32_t	oem_rev;
177	char		creator_id[4];
178	uint32_t	creator_rev;
179	uint32_t	entries;	/* Number of Type0 and Type1 Entries. */
180	union dev_desc {	/* Device Descriptor */
181		uint8_t type;
182#define	DIG64_ENTRYTYPE_TYPE0		0	/* (UART | Bidirect) */
183#define	DIG64_ENTRYTYPE_TYPE1		1	/* (UART | Debug Port) */
184#define	DIG64_ENTRYTYPE_BIDIRECT	(0<<0)	/* bidirectional console */
185#define	DIG64_ENTRYTYPE_DEBUGPORT	(1<<0)	/* debug port */
186#define	DIG64_ENTRYTYPE_OUTONLY		(2<<0)	/* console output-only */
187#define	DIG64_ENTRYTYPE_INONLY		(3<<0)	/* console input-only */
188#define	DIG64_ENTRYTYPE_UART		(0<<3)
189#define	DIG64_ENTRYTYPE_VGA		(1<<3)
190#define	DIG64_ENTRYTYPE_VENDOR		(1<<7)	/* Vendor specific */
191		struct dig64_hcdp_entry uart;
192		struct dig64_pcdp_entry pcdp;
193	} entry[0];
194};
195
196#endif
197