apic.c revision 1.3 
1/*	$NetBSD: apic.c,v 1.3 2019/11/10 21:16:28 chs Exp $	*/
2
3/*	$OpenBSD: apic.c,v 1.14 2011/05/01 21:59:39 kettenis Exp $	*/
4
5/*
6 * Copyright (c) 2005 Michael Shalayeff
7 * Copyright (c) 2007 Mark Kettenis
8 * All rights reserved.
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
19 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
20 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
21
22#include <sys/param.h>
23#include <sys/systm.h>
24#include <sys/device.h>
25#include <sys/malloc.h>
26
27#include <machine/autoconf.h>
28#include <machine/pdc.h>
29#include <machine/intr.h>
30
31#include <dev/pci/pcireg.h>
32#include <dev/pci/pcivar.h>
33#include <dev/pci/pcidevs.h>
34
35#include <hppa/dev/elroyreg.h>
36#include <hppa/dev/elroyvar.h>
37
38#define APIC_INT_LINE_MASK	0x0000ff00
39#define APIC_INT_LINE_SHIFT	8
40#define APIC_INT_IRQ_MASK	0x0000001f
41
42#define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT)
43#define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK)
44
45/*
46 * Interrupt types match the Intel MP Specification.
47 */
48
49#define MPS_INTPO_DEF		0
50#define MPS_INTPO_ACTHI		1
51#define MPS_INTPO_ACTLO		3
52#define MPS_INTPO_SHIFT		0
53#define MPS_INTPO_MASK		3
54
55#define MPS_INTTR_DEF		0
56#define MPS_INTTR_EDGE		1
57#define MPS_INTTR_LEVEL		3
58#define MPS_INTTR_SHIFT		2
59#define MPS_INTTR_MASK		3
60
61#define MPS_INT(p,t) \
62    ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \
63     (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT))
64
65struct apic_iv {
66	struct elroy_softc *sc;
67	pci_intr_handle_t ih;
68	int (*handler)(void *);
69	void *arg;
70	struct apic_iv *next;
71	struct evcnt *cnt;
72	char aiv_name[32];
73};
74
75struct apic_iv *apic_intr_list[CPU_NINTS];
76
77void apic_write(volatile struct elroy_regs *, uint32_t, uint32_t);
78uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg);
79
80void	apic_get_int_tbl(struct elroy_softc *);
81uint32_t apic_get_int_ent0(struct elroy_softc *, int);
82#ifdef DEBUG
83void	apic_dump(struct elroy_softc *);
84#endif
85
86void
87apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val)
88{
89	elroy_write32(&r->apic_addr, htole32(reg));
90	elroy_write32(&r->apic_data, htole32(val));
91	elroy_read32(&r->apic_data);
92}
93
94uint32_t
95apic_read(volatile struct elroy_regs *r, uint32_t reg)
96{
97	elroy_write32(&r->apic_addr, htole32(reg));
98	return le32toh(elroy_read32(&r->apic_data));
99}
100
101void
102apic_attach(struct elroy_softc *sc)
103{
104	volatile struct elroy_regs *r = sc->sc_regs;
105	uint32_t data;
106
107	data = apic_read(r, APIC_VERSION);
108	sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT;
109	aprint_normal(" APIC ver %x, %d pins",
110	    data & APIC_VERSION_MASK, sc->sc_nints);
111
112	sc->sc_irq = malloc(sc->sc_nints * sizeof(int), M_DEVBUF,
113	    M_WAITOK | M_ZERO);
114
115	apic_get_int_tbl(sc);
116
117#ifdef DEBUG
118	apic_dump(sc);
119#endif
120}
121
122int
123apic_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
124{
125	struct elroy_softc *sc = pa->pa_pc->_cookie;
126	struct cpu_info *ci = &cpus[0];
127	pci_chipset_tag_t pc = pa->pa_pc;
128	pcitag_t tag = pa->pa_tag;
129	pcireg_t reg;
130	int line;
131
132	reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
133#ifdef DEBUG
134	printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
135	    PCI_INTERRUPT_LINE(reg));
136#endif
137	line = PCI_INTERRUPT_LINE(reg);
138	if (sc->sc_irq[line] == 0)
139		sc->sc_irq[line] = hppa_intr_allocate_bit(&ci->ci_ir, -1);
140	KASSERT(sc->sc_irq[line] != -1);
141	*ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line];
142
143	return APIC_INT_IRQ(*ihp) == 0;
144}
145
146const char *
147apic_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
148{
149	snprintf(buf, len, "line %ld irq %ld",
150	    APIC_INT_LINE(ih), APIC_INT_IRQ(ih));
151
152	return buf;
153}
154
155void *
156apic_intr_establish(void *v, pci_intr_handle_t ih,
157    int pri, int (*handler)(void *), void *arg)
158{
159	struct elroy_softc *sc = v;
160	volatile struct elroy_regs *r = sc->sc_regs;
161	struct cpu_info *ci = &cpus[0];
162	hppa_hpa_t hpa = ci->ci_hpa;
163	struct evcnt *cnt;
164	struct apic_iv *aiv, *biv;
165	void *iv;
166	int irq = APIC_INT_IRQ(ih);
167	int line = APIC_INT_LINE(ih);
168	uint32_t ent0;
169
170	/* no mapping or bogus */
171	if (irq <= 0 || irq > 31)
172		return NULL;
173
174	aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_WAITOK);
175	cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_WAITOK);
176	aiv->sc = sc;
177	aiv->ih = ih;
178	aiv->handler = handler;
179	aiv->arg = arg;
180	aiv->next = NULL;
181	aiv->cnt = cnt;
182
183	biv = apic_intr_list[irq];
184	if (biv == NULL) {
185		iv = hppa_intr_establish(pri, apic_intr, aiv, &ci->ci_ir, irq);
186		if (iv == NULL) {
187			free(aiv, M_DEVBUF);
188			free(cnt, M_DEVBUF);
189
190			return NULL;
191		}
192	}
193
194	snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d",
195	    line, irq);
196
197	evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
198	    device_xname(sc->sc_dv), aiv->aiv_name);
199
200	if (biv) {
201		while (biv->next)
202			biv = biv->next;
203		biv->next = aiv;
204		return arg;
205	}
206
207	ent0 = (31 - irq) & APIC_ENT0_VEC;
208	ent0 |= apic_get_int_ent0(sc, line);
209#if 0
210	if (cold) {
211		sc->sc_imr |= (1 << irq);
212		ent0 |= APIC_ENT0_MASK;
213	}
214#endif
215	apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
216	apic_write(sc->sc_regs, APIC_ENT1(line),
217	    ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
218	apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
219
220	/* Signal EOI. */
221	elroy_write32(&r->apic_eoi,
222	    htole32((31 - irq) & APIC_ENT0_VEC));
223
224	apic_intr_list[irq] = aiv;
225
226	return arg;
227}
228
229void
230apic_intr_disestablish(void *v, void *cookie)
231{
232}
233
234int
235apic_intr(void *v)
236{
237	struct apic_iv *iv = v;
238	struct elroy_softc *sc = iv->sc;
239	volatile struct elroy_regs *r = sc->sc_regs;
240	uint32_t irq = APIC_INT_IRQ(iv->ih);
241	int claimed = 0;
242
243	while (iv) {
244		claimed = iv->handler(iv->arg);
245		if (claimed && iv->cnt)
246			iv->cnt->ev_count++;
247		if (claimed)
248			break;
249		iv = iv->next;
250	}
251	/* Signal EOI. */
252	elroy_write32(&r->apic_eoi, htole32((31 - irq) & APIC_ENT0_VEC));
253
254	return claimed;
255}
256
257void
258apic_get_int_tbl(struct elroy_softc *sc)
259{
260	int nentries;
261	size_t size;
262	int err;
263
264	err = pdcproc_pci_inttblsz(&nentries);
265	if (err)
266		return;
267
268	size = nentries * sizeof(struct pdc_pat_pci_rt);
269	sc->sc_int_tbl_sz = nentries;
270	sc->sc_int_tbl = malloc(size, M_DEVBUF, M_WAITOK);
271
272	pdcproc_pci_gettable(nentries, size, sc->sc_int_tbl);
273}
274
275uint32_t
276apic_get_int_ent0(struct elroy_softc *sc, int line)
277{
278	volatile struct elroy_regs *r = sc->sc_regs;
279	int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF);
280	uint32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV;
281	int bus, mpspo, mpstr;
282	int i;
283
284	bus = le32toh(elroy_read32(&r->busnum)) & 0xff;
285	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
286		if (bus == sc->sc_int_tbl[i].bus &&
287		    line == sc->sc_int_tbl[i].line)
288			trigger = sc->sc_int_tbl[i].trigger;
289	}
290
291	mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK;
292	mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK;
293
294	switch (mpspo) {
295	case MPS_INTPO_DEF:
296		break;
297	case MPS_INTPO_ACTHI:
298		ent0 &= ~APIC_ENT0_LOW;
299		break;
300	case MPS_INTPO_ACTLO:
301		ent0 |= APIC_ENT0_LOW;
302		break;
303	default:
304		panic("unknown MPS interrupt polarity %d", mpspo);
305	}
306
307	switch(mpstr) {
308	case MPS_INTTR_DEF:
309		break;
310	case MPS_INTTR_LEVEL:
311		ent0 |= APIC_ENT0_LEV;
312		break;
313	case MPS_INTTR_EDGE:
314		ent0 &= ~APIC_ENT0_LEV;
315		break;
316	default:
317		panic("unknown MPS interrupt trigger %d", mpstr);
318	}
319
320	return ent0;
321}
322
323#ifdef DEBUG
324void
325apic_dump(struct elroy_softc *sc)
326{
327	int i;
328
329	for (i = 0; i < sc->sc_nints; i++)
330		printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)),
331		    apic_read(sc->sc_regs, APIC_ENT1(i)));
332
333	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
334		printf("type=%x ", sc->sc_int_tbl[i].type);
335		printf("len=%d ", sc->sc_int_tbl[i].len);
336		printf("itype=%d ", sc->sc_int_tbl[i].itype);
337		printf("trigger=%x ", sc->sc_int_tbl[i].trigger);
338		printf("pin=%x ", sc->sc_int_tbl[i].pin);
339		printf("bus=%d ", sc->sc_int_tbl[i].bus);
340		printf("line=%d ", sc->sc_int_tbl[i].line);
341		printf("addr=%llx\n", sc->sc_int_tbl[i].addr);
342	}
343}
344#endif
345