apic.c revision 1.2 
1/*	$NetBSD: apic.c,v 1.2 2014/03/31 20:51:20 christos Exp $	*/
2
3/*	$OpenBSD: apic.c,v 1.14 2011/05/01 21:59:39 kettenis Exp $	*/
4
5/*
6 * Copyright (c) 2005 Michael Shalayeff
7 * Copyright (c) 2007 Mark Kettenis
8 * All rights reserved.
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
19 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
20 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
21
22#include <sys/param.h>
23#include <sys/systm.h>
24#include <sys/device.h>
25#include <sys/malloc.h>
26
27#include <machine/autoconf.h>
28#include <machine/pdc.h>
29#include <machine/intr.h>
30
31#include <dev/pci/pcireg.h>
32#include <dev/pci/pcivar.h>
33#include <dev/pci/pcidevs.h>
34
35#include <hppa/dev/elroyreg.h>
36#include <hppa/dev/elroyvar.h>
37
38#define APIC_INT_LINE_MASK	0x0000ff00
39#define APIC_INT_LINE_SHIFT	8
40#define APIC_INT_IRQ_MASK	0x0000001f
41
42#define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT)
43#define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK)
44
45/*
46 * Interrupt types match the Intel MP Specification.
47 */
48
49#define MPS_INTPO_DEF		0
50#define MPS_INTPO_ACTHI		1
51#define MPS_INTPO_ACTLO		3
52#define MPS_INTPO_SHIFT		0
53#define MPS_INTPO_MASK		3
54
55#define MPS_INTTR_DEF		0
56#define MPS_INTTR_EDGE		1
57#define MPS_INTTR_LEVEL		3
58#define MPS_INTTR_SHIFT		2
59#define MPS_INTTR_MASK		3
60
61#define MPS_INT(p,t) \
62    ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \
63     (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT))
64
65struct apic_iv {
66	struct elroy_softc *sc;
67	pci_intr_handle_t ih;
68	int (*handler)(void *);
69	void *arg;
70	struct apic_iv *next;
71	struct evcnt *cnt;
72	char aiv_name[32];
73};
74
75struct apic_iv *apic_intr_list[CPU_NINTS];
76
77void apic_write(volatile struct elroy_regs *, uint32_t, uint32_t);
78uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg);
79
80void	apic_get_int_tbl(struct elroy_softc *);
81uint32_t apic_get_int_ent0(struct elroy_softc *, int);
82#ifdef DEBUG
83void	apic_dump(struct elroy_softc *);
84#endif
85
86void
87apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val)
88{
89	elroy_write32(&r->apic_addr, htole32(reg));
90	elroy_write32(&r->apic_data, htole32(val));
91	elroy_read32(&r->apic_data);
92}
93
94uint32_t
95apic_read(volatile struct elroy_regs *r, uint32_t reg)
96{
97	elroy_write32(&r->apic_addr, htole32(reg));
98	return le32toh(elroy_read32(&r->apic_data));
99}
100
101void
102apic_attach(struct elroy_softc *sc)
103{
104	volatile struct elroy_regs *r = sc->sc_regs;
105	uint32_t data;
106
107	data = apic_read(r, APIC_VERSION);
108	sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT;
109	aprint_normal(" APIC ver %x, %d pins",
110	    data & APIC_VERSION_MASK, sc->sc_nints);
111
112	sc->sc_irq = malloc(sc->sc_nints * sizeof(int), M_DEVBUF,
113	    M_NOWAIT | M_ZERO);
114	if (sc->sc_irq == NULL)
115		panic("apic_attach: can't allocate irq table\n");
116
117	apic_get_int_tbl(sc);
118
119#ifdef DEBUG
120	apic_dump(sc);
121#endif
122}
123
124int
125apic_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
126{
127	struct elroy_softc *sc = pa->pa_pc->_cookie;
128	struct cpu_info *ci = &cpus[0];
129	pci_chipset_tag_t pc = pa->pa_pc;
130	pcitag_t tag = pa->pa_tag;
131	pcireg_t reg;
132	int line;
133
134	reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
135#ifdef DEBUG
136	printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
137	    PCI_INTERRUPT_LINE(reg));
138#endif
139	line = PCI_INTERRUPT_LINE(reg);
140	if (sc->sc_irq[line] == 0)
141		sc->sc_irq[line] = hppa_intr_allocate_bit(&ci->ci_ir, -1);
142	KASSERT(sc->sc_irq[line] != -1);
143	*ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line];
144
145	return APIC_INT_IRQ(*ihp) == 0;
146}
147
148const char *
149apic_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
150{
151	snprintf(buf, len, "line %ld irq %ld",
152	    APIC_INT_LINE(ih), APIC_INT_IRQ(ih));
153
154	return buf;
155}
156
157void *
158apic_intr_establish(void *v, pci_intr_handle_t ih,
159    int pri, int (*handler)(void *), void *arg)
160{
161	struct elroy_softc *sc = v;
162	volatile struct elroy_regs *r = sc->sc_regs;
163	struct cpu_info *ci = &cpus[0];
164	hppa_hpa_t hpa = ci->ci_hpa;
165	struct evcnt *cnt;
166	struct apic_iv *aiv, *biv;
167	void *iv;
168	int irq = APIC_INT_IRQ(ih);
169	int line = APIC_INT_LINE(ih);
170	uint32_t ent0;
171
172	/* no mapping or bogus */
173	if (irq <= 0 || irq > 31)
174		return NULL;
175
176	aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT);
177	if (aiv == NULL)
178		return NULL;
179
180	cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_NOWAIT);
181	if (cnt == NULL) {
182		free(aiv, M_DEVBUF);
183		return NULL;
184	}
185
186	aiv->sc = sc;
187	aiv->ih = ih;
188	aiv->handler = handler;
189	aiv->arg = arg;
190	aiv->next = NULL;
191	aiv->cnt = cnt;
192
193	biv = apic_intr_list[irq];
194	if (biv == NULL) {
195		iv = hppa_intr_establish(pri, apic_intr, aiv, &ci->ci_ir, irq);
196		if (iv == NULL) {
197			free(aiv, M_DEVBUF);
198			free(cnt, M_DEVBUF);
199
200			return NULL;
201		}
202	}
203
204	snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d",
205	    line, irq);
206
207	evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
208	    device_xname(sc->sc_dv), aiv->aiv_name);
209
210	if (biv) {
211		while (biv->next)
212			biv = biv->next;
213		biv->next = aiv;
214		return arg;
215	}
216
217	ent0 = (31 - irq) & APIC_ENT0_VEC;
218	ent0 |= apic_get_int_ent0(sc, line);
219#if 0
220	if (cold) {
221		sc->sc_imr |= (1 << irq);
222		ent0 |= APIC_ENT0_MASK;
223	}
224#endif
225	apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
226	apic_write(sc->sc_regs, APIC_ENT1(line),
227	    ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
228	apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
229
230	/* Signal EOI. */
231	elroy_write32(&r->apic_eoi,
232	    htole32((31 - irq) & APIC_ENT0_VEC));
233
234	apic_intr_list[irq] = aiv;
235
236	return arg;
237}
238
239void
240apic_intr_disestablish(void *v, void *cookie)
241{
242}
243
244int
245apic_intr(void *v)
246{
247	struct apic_iv *iv = v;
248	struct elroy_softc *sc = iv->sc;
249	volatile struct elroy_regs *r = sc->sc_regs;
250	uint32_t irq = APIC_INT_IRQ(iv->ih);
251	int claimed = 0;
252
253	while (iv) {
254		claimed = iv->handler(iv->arg);
255		if (claimed && iv->cnt)
256			iv->cnt->ev_count++;
257		if (claimed)
258			break;
259		iv = iv->next;
260	}
261	/* Signal EOI. */
262	elroy_write32(&r->apic_eoi, htole32((31 - irq) & APIC_ENT0_VEC));
263
264	return claimed;
265}
266
267void
268apic_get_int_tbl(struct elroy_softc *sc)
269{
270	int nentries;
271	size_t size;
272	int err;
273
274	err = pdcproc_pci_inttblsz(&nentries);
275	if (err)
276		return;
277
278	size = nentries * sizeof(struct pdc_pat_pci_rt);
279	sc->sc_int_tbl_sz = nentries;
280	sc->sc_int_tbl = malloc(size, M_DEVBUF, M_NOWAIT);
281	if (sc->sc_int_tbl == NULL)
282		return;
283
284	pdcproc_pci_gettable(nentries, size, sc->sc_int_tbl);
285}
286
287uint32_t
288apic_get_int_ent0(struct elroy_softc *sc, int line)
289{
290	volatile struct elroy_regs *r = sc->sc_regs;
291	int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF);
292	uint32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV;
293	int bus, mpspo, mpstr;
294	int i;
295
296	bus = le32toh(elroy_read32(&r->busnum)) & 0xff;
297	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
298		if (bus == sc->sc_int_tbl[i].bus &&
299		    line == sc->sc_int_tbl[i].line)
300			trigger = sc->sc_int_tbl[i].trigger;
301	}
302
303	mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK;
304	mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK;
305
306	switch (mpspo) {
307	case MPS_INTPO_DEF:
308		break;
309	case MPS_INTPO_ACTHI:
310		ent0 &= ~APIC_ENT0_LOW;
311		break;
312	case MPS_INTPO_ACTLO:
313		ent0 |= APIC_ENT0_LOW;
314		break;
315	default:
316		panic("unknown MPS interrupt polarity %d", mpspo);
317	}
318
319	switch(mpstr) {
320	case MPS_INTTR_DEF:
321		break;
322	case MPS_INTTR_LEVEL:
323		ent0 |= APIC_ENT0_LEV;
324		break;
325	case MPS_INTTR_EDGE:
326		ent0 &= ~APIC_ENT0_LEV;
327		break;
328	default:
329		panic("unknown MPS interrupt trigger %d", mpstr);
330	}
331
332	return ent0;
333}
334
335#ifdef DEBUG
336void
337apic_dump(struct elroy_softc *sc)
338{
339	int i;
340
341	for (i = 0; i < sc->sc_nints; i++)
342		printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)),
343		    apic_read(sc->sc_regs, APIC_ENT1(i)));
344
345	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
346		printf("type=%x ", sc->sc_int_tbl[i].type);
347		printf("len=%d ", sc->sc_int_tbl[i].len);
348		printf("itype=%d ", sc->sc_int_tbl[i].itype);
349		printf("trigger=%x ", sc->sc_int_tbl[i].trigger);
350		printf("pin=%x ", sc->sc_int_tbl[i].pin);
351		printf("bus=%d ", sc->sc_int_tbl[i].bus);
352		printf("line=%d ", sc->sc_int_tbl[i].line);
353		printf("addr=%llx\n", sc->sc_int_tbl[i].addr);
354	}
355}
356#endif
357