1/*	$NetBSD: apic.c,v 1.4 2020/11/21 21:01:16 thorpej Exp $	*/
2
3/*	$OpenBSD: apic.c,v 1.14 2011/05/01 21:59:39 kettenis Exp $	*/
4
5/*
6 * Copyright (c) 2005 Michael Shalayeff
7 * Copyright (c) 2007 Mark Kettenis
8 * All rights reserved.
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
19 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
20 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
21
22#include <sys/param.h>
23#include <sys/systm.h>
24#include <sys/device.h>
25#include <sys/kmem.h>
26
27#include <machine/autoconf.h>
28#include <machine/pdc.h>
29#include <machine/intr.h>
30
31#include <dev/pci/pcireg.h>
32#include <dev/pci/pcivar.h>
33#include <dev/pci/pcidevs.h>
34
35#include <hppa/dev/elroyreg.h>
36#include <hppa/dev/elroyvar.h>
37
38#define APIC_INT_LINE_MASK	0x0000ff00
39#define APIC_INT_LINE_SHIFT	8
40#define APIC_INT_IRQ_MASK	0x0000001f
41
42#define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT)
43#define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK)
44
45/*
46 * Interrupt types match the Intel MP Specification.
47 */
48
49#define MPS_INTPO_DEF		0
50#define MPS_INTPO_ACTHI		1
51#define MPS_INTPO_ACTLO		3
52#define MPS_INTPO_SHIFT		0
53#define MPS_INTPO_MASK		3
54
55#define MPS_INTTR_DEF		0
56#define MPS_INTTR_EDGE		1
57#define MPS_INTTR_LEVEL		3
58#define MPS_INTTR_SHIFT		2
59#define MPS_INTTR_MASK		3
60
61#define MPS_INT(p,t) \
62    ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \
63     (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT))
64
65struct apic_iv {
66	struct elroy_softc *sc;
67	pci_intr_handle_t ih;
68	int (*handler)(void *);
69	void *arg;
70	struct apic_iv *next;
71	struct evcnt *cnt;
72	char aiv_name[32];
73};
74
75struct apic_iv *apic_intr_list[CPU_NINTS];
76
77void apic_write(volatile struct elroy_regs *, uint32_t, uint32_t);
78uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg);
79
80void	apic_get_int_tbl(struct elroy_softc *);
81uint32_t apic_get_int_ent0(struct elroy_softc *, int);
82#ifdef DEBUG
83void	apic_dump(struct elroy_softc *);
84#endif
85
86void
87apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val)
88{
89	elroy_write32(&r->apic_addr, htole32(reg));
90	elroy_write32(&r->apic_data, htole32(val));
91	elroy_read32(&r->apic_data);
92}
93
94uint32_t
95apic_read(volatile struct elroy_regs *r, uint32_t reg)
96{
97	elroy_write32(&r->apic_addr, htole32(reg));
98	return le32toh(elroy_read32(&r->apic_data));
99}
100
101void
102apic_attach(struct elroy_softc *sc)
103{
104	volatile struct elroy_regs *r = sc->sc_regs;
105	uint32_t data;
106
107	data = apic_read(r, APIC_VERSION);
108	sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT;
109	aprint_normal(" APIC ver %x, %d pins",
110	    data & APIC_VERSION_MASK, sc->sc_nints);
111
112	sc->sc_irq = kmem_zalloc(sc->sc_nints * sizeof(int), KM_SLEEP);
113
114	apic_get_int_tbl(sc);
115
116#ifdef DEBUG
117	apic_dump(sc);
118#endif
119}
120
121int
122apic_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
123{
124	struct elroy_softc *sc = pa->pa_pc->_cookie;
125	struct cpu_info *ci = &cpus[0];
126	pci_chipset_tag_t pc = pa->pa_pc;
127	pcitag_t tag = pa->pa_tag;
128	pcireg_t reg;
129	int line;
130
131	reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
132#ifdef DEBUG
133	printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
134	    PCI_INTERRUPT_LINE(reg));
135#endif
136	line = PCI_INTERRUPT_LINE(reg);
137	if (sc->sc_irq[line] == 0)
138		sc->sc_irq[line] = hppa_intr_allocate_bit(&ci->ci_ir, -1);
139	KASSERT(sc->sc_irq[line] != -1);
140	*ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line];
141
142	return APIC_INT_IRQ(*ihp) == 0;
143}
144
145const char *
146apic_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
147{
148	snprintf(buf, len, "line %ld irq %ld",
149	    APIC_INT_LINE(ih), APIC_INT_IRQ(ih));
150
151	return buf;
152}
153
154void *
155apic_intr_establish(void *v, pci_intr_handle_t ih,
156    int pri, int (*handler)(void *), void *arg)
157{
158	struct elroy_softc *sc = v;
159	volatile struct elroy_regs *r = sc->sc_regs;
160	struct cpu_info *ci = &cpus[0];
161	hppa_hpa_t hpa = ci->ci_hpa;
162	struct evcnt *cnt;
163	struct apic_iv *aiv, *biv;
164	void *iv;
165	int irq = APIC_INT_IRQ(ih);
166	int line = APIC_INT_LINE(ih);
167	uint32_t ent0;
168
169	/* no mapping or bogus */
170	if (irq <= 0 || irq > 31)
171		return NULL;
172
173	aiv = kmem_alloc(sizeof(struct apic_iv), KM_SLEEP);
174	cnt = kmem_alloc(sizeof(struct evcnt), KM_SLEEP);
175	aiv->sc = sc;
176	aiv->ih = ih;
177	aiv->handler = handler;
178	aiv->arg = arg;
179	aiv->next = NULL;
180	aiv->cnt = cnt;
181
182	biv = apic_intr_list[irq];
183	if (biv == NULL) {
184		iv = hppa_intr_establish(pri, apic_intr, aiv, &ci->ci_ir, irq);
185		if (iv == NULL) {
186			kmem_free(aiv, sizeof(*aiv));
187			kmem_free(cnt, sizeof(*cnt));
188
189			return NULL;
190		}
191	}
192
193	snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d",
194	    line, irq);
195
196	evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
197	    device_xname(sc->sc_dv), aiv->aiv_name);
198
199	if (biv) {
200		while (biv->next)
201			biv = biv->next;
202		biv->next = aiv;
203		return arg;
204	}
205
206	ent0 = (31 - irq) & APIC_ENT0_VEC;
207	ent0 |= apic_get_int_ent0(sc, line);
208#if 0
209	if (cold) {
210		sc->sc_imr |= (1 << irq);
211		ent0 |= APIC_ENT0_MASK;
212	}
213#endif
214	apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
215	apic_write(sc->sc_regs, APIC_ENT1(line),
216	    ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
217	apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
218
219	/* Signal EOI. */
220	elroy_write32(&r->apic_eoi,
221	    htole32((31 - irq) & APIC_ENT0_VEC));
222
223	apic_intr_list[irq] = aiv;
224
225	return arg;
226}
227
228void
229apic_intr_disestablish(void *v, void *cookie)
230{
231}
232
233int
234apic_intr(void *v)
235{
236	struct apic_iv *iv = v;
237	struct elroy_softc *sc = iv->sc;
238	volatile struct elroy_regs *r = sc->sc_regs;
239	uint32_t irq = APIC_INT_IRQ(iv->ih);
240	int claimed = 0;
241
242	while (iv) {
243		claimed = iv->handler(iv->arg);
244		if (claimed && iv->cnt)
245			iv->cnt->ev_count++;
246		if (claimed)
247			break;
248		iv = iv->next;
249	}
250	/* Signal EOI. */
251	elroy_write32(&r->apic_eoi, htole32((31 - irq) & APIC_ENT0_VEC));
252
253	return claimed;
254}
255
256void
257apic_get_int_tbl(struct elroy_softc *sc)
258{
259	int nentries;
260	size_t size;
261	int err;
262
263	err = pdcproc_pci_inttblsz(&nentries);
264	if (err)
265		return;
266
267	size = nentries * sizeof(struct pdc_pat_pci_rt);
268	sc->sc_int_tbl_sz = nentries;
269	sc->sc_int_tbl = kmem_alloc(size, KM_SLEEP);
270
271	pdcproc_pci_gettable(nentries, size, sc->sc_int_tbl);
272}
273
274uint32_t
275apic_get_int_ent0(struct elroy_softc *sc, int line)
276{
277	volatile struct elroy_regs *r = sc->sc_regs;
278	int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF);
279	uint32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV;
280	int bus, mpspo, mpstr;
281	int i;
282
283	bus = le32toh(elroy_read32(&r->busnum)) & 0xff;
284	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
285		if (bus == sc->sc_int_tbl[i].bus &&
286		    line == sc->sc_int_tbl[i].line)
287			trigger = sc->sc_int_tbl[i].trigger;
288	}
289
290	mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK;
291	mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK;
292
293	switch (mpspo) {
294	case MPS_INTPO_DEF:
295		break;
296	case MPS_INTPO_ACTHI:
297		ent0 &= ~APIC_ENT0_LOW;
298		break;
299	case MPS_INTPO_ACTLO:
300		ent0 |= APIC_ENT0_LOW;
301		break;
302	default:
303		panic("unknown MPS interrupt polarity %d", mpspo);
304	}
305
306	switch(mpstr) {
307	case MPS_INTTR_DEF:
308		break;
309	case MPS_INTTR_LEVEL:
310		ent0 |= APIC_ENT0_LEV;
311		break;
312	case MPS_INTTR_EDGE:
313		ent0 &= ~APIC_ENT0_LEV;
314		break;
315	default:
316		panic("unknown MPS interrupt trigger %d", mpstr);
317	}
318
319	return ent0;
320}
321
322#ifdef DEBUG
323void
324apic_dump(struct elroy_softc *sc)
325{
326	int i;
327
328	for (i = 0; i < sc->sc_nints; i++)
329		printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)),
330		    apic_read(sc->sc_regs, APIC_ENT1(i)));
331
332	for (i = 0; i < sc->sc_int_tbl_sz; i++) {
333		printf("type=%x ", sc->sc_int_tbl[i].type);
334		printf("len=%d ", sc->sc_int_tbl[i].len);
335		printf("itype=%d ", sc->sc_int_tbl[i].itype);
336		printf("trigger=%x ", sc->sc_int_tbl[i].trigger);
337		printf("pin=%x ", sc->sc_int_tbl[i].pin);
338		printf("bus=%d ", sc->sc_int_tbl[i].bus);
339		printf("line=%d ", sc->sc_int_tbl[i].line);
340		printf("addr=%llx\n", sc->sc_int_tbl[i].addr);
341	}
342}
343#endif
344