vrc4173bcu.c revision 1.11
1/* $NetBSD: vrc4173bcu.c,v 1.11 2002/10/02 05:26:54 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2001,2002 Enami Tsugutomo. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/device.h> 32 33#include <machine/bus.h> 34 35#include <dev/pci/pcivar.h> 36#include <dev/pci/pcidevs.h> 37 38#include <machine/platid.h> 39#include <machine/platid_mask.h> 40#include <machine/config_hook.h> 41 42#include <hpcmips/vr/vripunit.h> 43#include <hpcmips/vr/vripif.h> 44#include <hpcmips/vr/vrc4173bcuvar.h> 45#include <hpcmips/vr/vrc4173icureg.h> 46#include <hpcmips/vr/vrc4173cmureg.h> 47 48#ifdef VRC4173BCU_DEBUG 49#define DPRINTF_ENABLE 50#define DPRINTF_DEBUG vrc4173bcu_debug 51#endif 52#define USE_HPC_DPRINTF 53#include <machine/debug.h> 54 55#define VRC4173BCU_BADR 0x10 56#define USE_WINCE_CLKMASK (~0) 57 58static int vrc4173bcu_match(struct device *, struct cfdata *, void *); 59static void vrc4173bcu_attach(struct device *, struct device *, void *); 60static int vrc4173bcu_intr(void *); 61static int vrc4173bcu_print(void *, const char *); 62static int vrc4173bcu_search(struct device *, struct cfdata *cf, void *); 63static int vrc4173bcu_pci_intr(void *); 64#ifdef VRC4173BCU_DEBUG 65static void vrc4173bcu_dump_level2mask(vrip_chipset_tag_t, 66 vrip_intr_handle_t); 67#endif 68 69int __vrc4173bcu_power(vrip_chipset_tag_t, int, int); 70vrip_intr_handle_t __vrc4173bcu_intr_establish(vrip_chipset_tag_t, int, int, 71 int, int(*)(void*), void*); 72void __vrc4173bcu_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 73void __vrc4173bcu_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 74void __vrc4173bcu_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 75 u_int32_t, int); 76void __vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 77 u_int32_t*); 78void __vrc4173bcu_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 79void __vrc4173bcu_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 80void __vrc4173bcu_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 81void __vrc4173bcu_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 82int __vrc4173bcu_clock(vrcmu_chipset_tag_t, u_int16_t, int); 83 84/* 85 * machine dependent info 86 */ 87static struct vrc4173bcu_platdep { 88 platid_mask_t *platidmask; 89 u_int32_t clkmask; 90 int intrmask; 91} platdep_table[] = { 92 { 93 &platid_mask_MACH_VICTOR_INTERLINK_MPC303, 94 USE_WINCE_CLKMASK, /* clock mask */ 95 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 96 (1 << VRC4173ICU_PCMCIA1INTR)| 97 (1 << VRC4173ICU_PCMCIA2INTR), 98 }, 99 { 100 &platid_mask_MACH_VICTOR_INTERLINK_MPC304, 101 USE_WINCE_CLKMASK, /* clock mask */ 102 (1 << VRC4173ICU_USBINTR)| /* intrrupts */ 103 (1 << VRC4173ICU_PCMCIA1INTR)| 104 (1 << VRC4173ICU_PCMCIA2INTR), 105 }, 106 { 107 &platid_mask_MACH_NEC_MCR_SIGMARION2, 108 USE_WINCE_CLKMASK, /* clock mask */ 109 (1 << VRC4173ICU_USBINTR), /* intrrupts */ 110 }, 111 { 112 &platid_wild, 113 USE_WINCE_CLKMASK, /* XXX */ 114 -1, 115 }, 116}; 117 118struct vrc4173bcu_unit { 119 char *vu_name; 120 int vu_intr[2]; 121 int vu_clkmask; 122 bus_addr_t vu_lreg; 123 bus_addr_t vu_mlreg; 124 bus_addr_t vu_hreg; 125 bus_addr_t vu_mhreg; 126}; 127 128struct vrc4173bcu_softc { 129 struct device sc_dev; 130 struct vrip_chipset_tag sc_chipset; 131 struct vrcmu_chipset_tag sc_cmuchip; 132 133 pci_chipset_tag_t sc_pc; 134 bus_space_tag_t sc_iot; 135 bus_space_handle_t sc_ioh; 136 bus_size_t sc_size; 137 138 bus_space_handle_t sc_icuh; /* I/O handle for ICU. */ 139 bus_space_handle_t sc_cmuh; /* I/O handle for CMU. */ 140 void *sc_ih; 141#define VRC4173BCU_NINTRS 16 142 int sc_intrmask; 143 struct vrc4173bcu_intrhand { 144 int (*ih_fun)(void *); 145 void *ih_arg; 146 const struct vrc4173bcu_unit *ih_unit; 147 } sc_intrhands[32]; 148 149 struct vrc4173bcu_unit *sc_units; 150 int sc_nunits; 151 int sc_pri; 152 153 struct vrc4173bcu_platdep *sc_platdep; 154}; 155 156#define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 157 158static struct vrc4173bcu_unit vrc4173bcu_units[] = { 159 [VRIP_UNIT_KIU] = { 160 "kiu", 161 { VRC4173ICU_KIUINTR, }, 162 VRC4173CMU_CLKMSK_KIU, 163 VRC4173ICU_KIUINT, VRC4173ICU_MKIUINT, 164 }, 165 [VRIP_UNIT_PIU] = { 166 "piu", 167 { VRC4173ICU_PIUINTR, VRC4173ICU_DOZEPIUINTR}, 168 VRC4173CMU_CLKMSK_PIU, 169 VRC4173ICU_PIUINT, VRC4173ICU_MPIUINT, 170 }, 171 [VRIP_UNIT_AIU] = { 172 "aiu", 173 { VRC4173ICU_AIUINTR, }, 174 VRC4173CMU_CLKMSK_AIU, 175 VRC4173ICU_AIUINT, VRC4173ICU_MAIUINT, 176 }, 177 [VRIP_UNIT_GIU] = { 178 "giu", 179 { VRC4173ICU_GIUINTR, }, 180 0, 181 VRC4173ICU_GIULINT, VRC4173ICU_MGIULINT, 182 VRC4173ICU_GIUHINT, VRC4173ICU_MGIUHINT, 183 }, 184 [VRIP_UNIT_PS2U0] = { 185 "PS/2-Ch1", 186 { VRC4173ICU_PS2CH1INTR, }, 187 VRC4173CMU_CLKMSK_PS2CH1, 188 }, 189 [VRIP_UNIT_PS2U1] = { 190 "PS/2-Ch2", 191 { VRC4173ICU_PS2CH2INTR, }, 192 VRC4173CMU_CLKMSK_PS2CH2, 193 }, 194 [VRIP_UNIT_USBU] = { 195 "usbu", 196 { VRC4173ICU_USBINTR, }, 197 VRC4173CMU_CLKMSK_USB, 198 }, 199 [VRIP_UNIT_CARDU0] = { 200 "cardu0", 201 { VRC4173ICU_PCMCIA1INTR, }, 202 VRC4173CMU_CLKMSK_CARD1, 203 }, 204 [VRIP_UNIT_CARDU1] = { 205 "cardu1", 206 { VRC4173ICU_PCMCIA2INTR, }, 207 VRC4173CMU_CLKMSK_CARD2, 208 }, 209}; 210 211CFATTACH_DECL(vrc4173bcu, sizeof(struct vrc4173bcu_softc), 212 vrc4173bcu_match, vrc4173bcu_attach, NULL, NULL); 213 214static const struct vrip_chipset_tag vrc4173bcu_chipset_methods = { 215 .vc_power = __vrc4173bcu_power, 216 .vc_intr_establish = __vrc4173bcu_intr_establish, 217 .vc_intr_disestablish = __vrc4173bcu_intr_disestablish, 218 .vc_intr_setmask1 = __vrc4173bcu_intr_setmask1, 219 .vc_intr_setmask2 = __vrc4173bcu_intr_setmask2, 220 .vc_intr_getstatus2 = __vrc4173bcu_intr_getstatus2, 221 .vc_register_cmu = __vrc4173bcu_register_cmu, 222 .vc_register_gpio = __vrc4173bcu_register_gpio, 223 .vc_register_dmaau = __vrc4173bcu_register_dmaau, 224 .vc_register_dcu = __vrc4173bcu_register_dcu, 225}; 226 227int 228vrc4173bcu_match(struct device *parent, struct cfdata *match, void *aux) 229{ 230 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 231 232 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NEC && 233 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NEC_VRC4173_BCU) 234 return (1); 235 236 return (0); 237} 238 239void 240vrc4173bcu_attach(struct device *parent, struct device *self, void *aux) 241{ 242 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)self; 243 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 244 pci_chipset_tag_t pc = pa->pa_pc; 245 pcitag_t tag = pa->pa_tag; 246 pcireg_t csr; 247 char devinfo[256]; 248 u_int16_t reg; 249 pci_intr_handle_t ih; 250 const char *intrstr; 251 int bus, device, function; 252#ifdef DEBUG 253 char buf[80]; 254#endif 255 256 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 257 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 258 259#if 0 260 printf("%s: ", sc->sc_dev.dv_xname); 261 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 262#endif 263 264 sc->sc_pc = pc; 265 sc->sc_cmuchip.cc_sc = sc; 266 sc->sc_cmuchip.cc_clock = __vrc4173bcu_clock; 267 sc->sc_units = vrc4173bcu_units; 268 sc->sc_nunits = sizeof(vrc4173bcu_units)/sizeof(struct vrc4173bcu_unit); 269 sc->sc_chipset = vrc4173bcu_chipset_methods; /* structure assignment */ 270 sc->sc_chipset.vc_sc = sc; 271 272 sc->sc_platdep = platid_search(&platid, platdep_table, 273 sizeof(platdep_table)/sizeof(*platdep_table), 274 sizeof(*platdep_table)); 275 276 /* Map I/O registers */ 277 if (pci_mapreg_map(pa, VRC4173BCU_BADR, PCI_MAPREG_TYPE_IO, 0, 278 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 279 printf("%s: can't map mem space\n", sc->sc_dev.dv_xname); 280 return; 281 } 282 283 /* Enable the device. */ 284 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 285 DPRINTF(("%s: csr = 0x%08x", sc->sc_dev.dv_xname, csr)); 286 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 287 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 288 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 289 DPRINTF((" -> 0x%08x\n", csr)); 290 291 csr = pci_conf_read(pc, tag, VRC4173BCU_BADR); 292 DPRINTF(("%s: base addr = %x@0x%08x\n", sc->sc_dev.dv_xname, 293 (int)sc->sc_size, csr)); 294 DPRINTF(("%s: iot = 0x%08x, ioh = 0x%08x\n", sc->sc_dev.dv_xname, 295 (int)sc->sc_iot, (int)sc->sc_ioh)); 296 297 /* 298 * Map I/O space for ICU. 299 */ 300 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 301 VRC4173ICU_IOBASE, VRC4173ICU_IOSIZE, &sc->sc_icuh)) { 302 printf(": can't map ICU i/o space\n"); 303 return; 304 } 305 306 /* 307 * Map I/O space for CMU. 308 */ 309 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 310 VRC4173CMU_IOBASE, VRC4173CMU_IOSIZE, &sc->sc_cmuh)) { 311 printf(": can't map CMU i/o space\n"); 312 return; 313 } 314 315 /* machine dependent setup */ 316 if (sc->sc_platdep->clkmask == USE_WINCE_CLKMASK) { 317 /* XXX, You can nothing! */ 318 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, 319 VRC4173CMU_CLKMSK); 320 printf("%s: default clock mask is %04x\n", 321 sc->sc_dev.dv_xname, reg); 322 } else { 323 /* assert all reset bits */ 324 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 325 VRC4173CMU_SRST_AC97 | VRC4173CMU_SRST_USB | 326 VRC4173CMU_SRST_CARD2 | VRC4173CMU_SRST_CARD1); 327 /* set clock mask */ 328 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, 329 VRC4173CMU_CLKMSK, sc->sc_platdep->clkmask); 330 /* clear reset bit */ 331 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_SRST, 0); 332 } 333 334#ifdef DEBUG 335 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 336 bitmask_snprintf(reg, 337 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 338 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 339 buf, sizeof(buf)); 340 printf("%s: SYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 341 342 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MKIUINT); 343 bitmask_snprintf(reg, 344 "\20\1SCANINT\2KDATRDY\3KDATLOST\4B3\5B4\6B5\7B6\10B7" 345 "\11B8\12B9\13B10\14B11\15B12\16B13\17B14\20B15", 346 buf, sizeof(buf)); 347 printf("%s: MKIUINT = 0x%s\n", sc->sc_dev.dv_xname, buf); 348 349 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 350 bitmask_snprintf(reg, 351 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 352 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 353 buf, sizeof(buf)); 354 printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 355 356#if 1 357 reg = VRC4173ICU_USBINTR | VRC4173ICU_PIUINTR | VRC4173ICU_KIUINTR | 358 VRC4173ICU_DOZEPIUINTR; 359 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, reg); 360 361 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1); 362 bitmask_snprintf(reg, 363 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 364 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 365 buf, sizeof(buf)); 366 printf("%s: MSYSINT1 = 0x%s\n", sc->sc_dev.dv_xname, buf); 367#endif 368#endif 369 370 /* 371 * set interrupt mask 372 */ 373 sc->sc_intrmask = sc->sc_platdep->intrmask; 374 bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 375 sc->sc_intrmask); 376 377 /* 378 * install interrupt handler 379 */ 380 if (pci_intr_map(pa, &ih)) { 381 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 382 return; 383 } 384 intrstr = pci_intr_string(pc, ih); 385 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vrc4173bcu_intr, sc); 386 if (sc->sc_ih == NULL) { 387 printf("%s: couldn't establish interrupt", 388 sc->sc_dev.dv_xname); 389 if (intrstr != NULL) 390 printf(" at %s", intrstr); 391 printf("\n"); 392 return; 393 } 394 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 395 396 /* 397 * install pci intr hooks 398 */ 399 pci_decompose_tag(pc, pa->pa_intrtag, &bus, &device, &function); 400 /* USB unit */ 401 if (sc->sc_intrmask & (1 << VRC4173ICU_USBINTR)) 402 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_USBU, 0, 403 IPL_NET, vrc4173bcu_pci_intr, 404 config_connect(CONFIG_HOOK_PCIINTR, 405 CONFIG_HOOK_PCIINTR_ID(bus, device, 2))); 406 /* PC card unit 1 */ 407 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA1INTR)) 408 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU0, 0, 409 IPL_NET, vrc4173bcu_pci_intr, 410 config_connect(CONFIG_HOOK_PCIINTR, 411 CONFIG_HOOK_PCIINTR_ID(bus, 1, 0))); 412 /* PC card unit 2 */ 413 if (sc->sc_intrmask & (1 << VRC4173ICU_PCMCIA2INTR)) 414 vrip_intr_establish(&sc->sc_chipset, VRIP_UNIT_CARDU1, 0, 415 IPL_NET, vrc4173bcu_pci_intr, 416 config_connect(CONFIG_HOOK_PCIINTR, 417 CONFIG_HOOK_PCIINTR_ID(bus, 2, 0))); 418 419 /* 420 * Attach each devices 421 * sc->sc_pri = 2~1 422 */ 423 for (sc->sc_pri = 2; 0 < sc->sc_pri; sc->sc_pri--) 424 config_search(vrc4173bcu_search, self, vrc4173bcu_print); 425} 426 427int 428vrc4173bcu_print(void *aux, const char *hoge) 429{ 430 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 431 432 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 433 printf(" addr 0x%04lx", va->va_addr); 434 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) 435 printf("-%04lx", (va->va_addr + va->va_size - 1) & 0xffff); 436 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 437 printf(", 0x%04lx", va->va_addr2); 438 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 439 printf("-%04lx", (va->va_addr2 + va->va_size2 - 1) & 0xffff); 440 441 return (UNCONF); 442} 443 444int 445vrc4173bcu_search(struct device *parent, struct cfdata *cf, void *aux) 446{ 447 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)parent; 448 struct vrip_attach_args va; 449 450 memset(&va, 0, sizeof(va)); 451 va.va_vc = &sc->sc_chipset; 452 va.va_iot = sc->sc_iot; 453 va.va_parent_ioh = sc->sc_ioh; 454 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 455 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 456 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 457 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 458 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 459 va.va_gpio_chips = NULL; /* XXX */ 460 va.va_cc = sc->sc_chipset.vc_cc; 461 va.va_ac = sc->sc_chipset.vc_ac; 462 va.va_dc = sc->sc_chipset.vc_dc; 463 if ((config_match(parent, cf, &va) == sc->sc_pri)) 464 config_attach(parent, cf, &va, vrc4173bcu_print); 465 466 return (0); 467} 468 469int 470vrc4173bcu_intr(void *arg) 471{ 472 struct vrc4173bcu_softc *sc = (struct vrc4173bcu_softc *)arg; 473 u_int16_t reg; 474 struct vrc4173bcu_intrhand *ih; 475 int i; 476 477 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1); 478 reg &= sc->sc_intrmask; 479 if (reg == 0) 480 return (0); 481 482#if 0 483 { 484 char buf[80]; 485 bitmask_snprintf(reg, 486 "\20\1USB\2PCMCIA2\3PCMCIA1\4PS2CH2\5PS2CH1\6PIU\7AIU\10KIU" 487 "\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", 488 buf, sizeof(buf)); 489 printf("%s: %s\n", sc->sc_dev.dv_xname, buf); 490 } 491#endif 492 for (ih = sc->sc_intrhands, i = 0; i < VRC4173BCU_NINTRS; i++, ih++) 493 if ((reg & (1 << i)) && ih->ih_fun != NULL) 494 ih->ih_fun(ih->ih_arg); 495 496 return (1); 497} 498 499static int 500vrc4173bcu_pci_intr(void *arg) 501{ 502 config_call_tag ct = (config_call_tag)arg; 503 config_connected_call(ct, NULL); 504 505 return (0); 506} 507 508#ifdef VRC4173BCU_DEBUG 509static void 510vrc4173bcu_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 511{ 512 struct vrc4173bcu_softc *sc = vc->vc_sc; 513 struct vrc4173bcu_intrhand *ih = handle; 514 const struct vrc4173bcu_unit *vu = ih->ih_unit; 515 u_int32_t reg; 516 517 if (vu->vu_mlreg) { 518 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 519 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 520 if (vu->vu_mhreg) { 521 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, 522 vu->vu_mhreg) << 16); 523 dbg_bit_print(reg); 524 } else 525 dbg_bit_print(reg); 526 } 527} 528#endif 529 530int 531__vrc4173bcu_power(vrip_chipset_tag_t vc, int unit, int onoff) 532{ 533 struct vrc4173bcu_softc *sc = vc->vc_sc; 534 const struct vrc4173bcu_unit *vu; 535 536 if (sc->sc_chipset.vc_cc == NULL) 537 return (0); /* You have no clock mask unit yet. */ 538 if (!VALID_UNIT(sc, unit)) 539 return (0); 540 vu = &sc->sc_units[unit]; 541 542 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 543 vu->vu_clkmask, onoff); 544} 545 546vrip_intr_handle_t 547__vrc4173bcu_intr_establish(vrip_chipset_tag_t vc, int unit, int line, 548 int level, int (*ih_fun)(void *), void *ih_arg) 549{ 550 struct vrc4173bcu_softc *sc = vc->vc_sc; 551 const struct vrc4173bcu_unit *vu; 552 struct vrc4173bcu_intrhand *ih; 553 554 if (!VALID_UNIT(sc, unit)) 555 return (NULL); 556 vu = &sc->sc_units[unit]; 557 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 558 if (ih->ih_fun) /* Can't share level 1 interrupt */ 559 return (NULL); 560 ih->ih_fun = ih_fun; 561 ih->ih_arg = ih_arg; 562 ih->ih_unit = vu; 563 564 /* Mask level 2 interrupt mask register. (disable interrupt) */ 565 vrip_intr_setmask2(vc, ih, ~0, 0); 566 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 567 vrip_intr_setmask1(vc, ih, 1); 568 569 return ((void *)ih); 570} 571 572void 573__vrc4173bcu_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 574{ 575 struct vrc4173bcu_intrhand *ih = handle; 576 577 /* Mask Level 1 interrupt mask register (disable interrupt) */ 578 vrip_intr_setmask1(vc, ih, 0); 579 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 580 vrip_intr_setmask2(vc, ih, ~0, 0); 581 ih->ih_fun = NULL; 582 ih->ih_arg = NULL; 583} 584 585/* Set level 1 interrupt mask. */ 586void 587__vrc4173bcu_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 588 int enable) 589{ 590 struct vrc4173bcu_softc *sc = vc->vc_sc; 591 struct vrc4173bcu_intrhand *ih = handle; 592 int level1 = ih - sc->sc_intrhands; 593 594 DPRINTF(("__vrc4173bcu_intr_setmask1: SYSINT: %s %d\n", 595 enable ? "enable" : "disable", level1)); 596 if (enable) 597 sc->sc_intrmask |= (1 << level1); 598 else 599 sc->sc_intrmask &= ~(1 << level1); 600 bus_space_write_2 (sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, 601 sc->sc_intrmask); 602#ifdef VRC4173BCU_DEBUG 603 if (vrc4173bcu_debug) 604 dbg_bit_print(sc->sc_intrmask); 605#endif 606 607 return; 608} 609 610/* Get level 2 interrupt status */ 611void 612__vrc4173bcu_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 613 u_int32_t *status /* Level 2 status */) 614{ 615 struct vrc4173bcu_softc *sc = vc->vc_sc; 616 struct vrc4173bcu_intrhand *ih = handle; 617 const struct vrc4173bcu_unit *vu = ih->ih_unit; 618 u_int32_t reg; 619 620 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_lreg); 621 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_hreg) << 16); 622 *status = reg; 623} 624 625/* Set level 2 interrupt mask. */ 626void 627__vrc4173bcu_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 628 u_int32_t mask /* Level 2 mask */, int onoff) 629{ 630 struct vrc4173bcu_softc *sc = vc->vc_sc; 631 struct vrc4173bcu_intrhand *ih = handle; 632 const struct vrc4173bcu_unit *vu = ih->ih_unit; 633 u_int16_t reg; 634 635 DPRINTF(("vrc4173bcu_intr_setmask2:\n")); 636#ifdef VRC4173BCU_DEBUG 637 if (vrc4173bcu_debug) 638 vrc4173bcu_dump_level2mask(vc, handle); 639#endif 640 if (vu->vu_mlreg) { 641 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg); 642 if (onoff) 643 reg |= (mask & 0xffff); 644 else 645 reg &= ~(mask & 0xffff); 646 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 647 } 648 if (vu->vu_mhreg) { 649 reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg); 650 if (onoff) 651 reg |= ((mask >> 16) & 0xffff); 652 else 653 reg &= ~((mask >> 16) & 0xffff); 654 bus_space_write_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg, reg); 655 } 656#ifdef VRC4173BCU_DEBUG 657 if (vrc4173bcu_debug) 658 vrc4173bcu_dump_level2mask(vc, handle); 659#endif 660 661 return; 662} 663 664int 665__vrc4173bcu_clock(vrcmu_chipset_tag_t cc, u_int16_t mask, int onoff) 666{ 667 struct vrc4173bcu_softc *sc = cc->cc_sc; 668 u_int16_t reg; 669 670 reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK); 671#if 0 672 printf("cmu register(enter):"); 673 dbg_bit_print(reg); 674#endif 675 if (onoff) 676 reg |= mask; 677 else 678 reg &= ~mask; 679 bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK, reg); 680#if 0 681 printf("cmu register(exit) :"); 682 dbg_bit_print(reg); 683#endif 684 return (0); 685} 686 687void 688__vrc4173bcu_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 689{ 690 vc->vc_cc = cmu; 691} 692 693void 694__vrc4173bcu_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 695{ 696 /* XXX, not implemented yet */ 697} 698 699void 700__vrc4173bcu_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 701{ 702 703 vc->vc_ac = dmaau; 704} 705 706void 707__vrc4173bcu_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 708{ 709 710 vc->vc_dc = dcu; 711} 712