1/* $NetBSD: vrc4172pmureg.h,v 1.1 2000/11/11 04:42:09 sato Exp $ */ 2 3/* 4 * Copyright (c) 2000 SATO Kazumi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Vrc4172 PMU unit register definition 30 */ 31 32#define VRC2_PMU_SYSCLKCTRL 0x00 33#define VRC2_PMU_IRST 0x20 /* internal reset */ 34#define VRC2_PMU_OSCDIS 0x10 /* OSC disable */ 35#define VRC2_PMU_CKO48 0x01 /* CKO48 enable */ 36#define VRC2_PMU_1284CTRL 0x02 37#define VRC2_PMU_1284EN 0x04 /* 1284 enable */ 38#define VRC2_PMU_1284RST 0x02 /* 1284 reset (>= 1us) */ 39#define VRC2_PMU_1284CLKDIS 0x01 /* 1284 clock disanle */ 40#define VRC2_PMU_16550CTRL 0x04 41#define VRC2_PMU_16550RST 0x02 /* 16550 reset (>= 200ms) */ 42#define VRC2_PMU_16550CLKDIS 0x01 /* 16550 clock disable */ 43#define VRC2_PMU_USBCTL 0x0c 44#define VRC2_PMU_USBCLKDIS 0x01 /* USB clock disable */ 45#define VRC2_PMU_PS2PWMCTL 0x0e 46#define VRC2_PMU_PWMCLKDIS 0x10 /* PWM clock disable */ 47#define VRC2_PMU_PS2RST 0x02 /* PS2 reset */ 48#define VRC2_PMU_PS2CLKDIS 0x01 /* PS2 clock disable */ 49 50/* end */ 51