1/* -*-C++-*-	$NetBSD: mips_tx39.h,v 1.3 2005/12/11 12:17:28 christos Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <hpcboot.h>
33#include <mips/mips_arch.h>
34
35class TX39XX : public MIPSArchitecture {
36private:
37
38public:
39	TX39XX(Console *&, MemoryManager *&, enum ArchitectureOps);
40	~TX39XX(void);
41
42	virtual BOOL init(void);
43	virtual void systemInfo(void);
44	virtual void cacheFlush(void);
45	static void boot_func(struct BootArgs *, struct PageTag *);
46};
47
48#define	MIPS_TX39XX_CACHE_FLUSH()					\
49__asm(									\
50	".set	noreorder;"						\
51	"li	t1, 16384;"						\
52	"li	t2, 8192;"						\
53									\
54	/* Disable I-cache */						\
55	"li	t5, ~0x00000020;"					\
56	"mfc0	t6, $3;"						\
57	"and	t5, t5, t6;"						\
58	"nop;"								\
59	"mtc0	t5, $3;"						\
60									\
61	/* Stop streaming */						\
62	"beq	zero, zero, 1f;"					\
63	"nop;"								\
64"1:"									\
65	/* Flush I-cache */						\
66	"li	t0, 0x80000000;"					\
67	"addu	t1, t0, t1;"						\
68	"subu	t1, t1, 128;"						\
69"2:"									\
70	"cache	0x0, 0($0);"						\
71	"cache	0x0, 16(t0);"						\
72	"cache	0x0, 32(t0);"						\
73	"cache	0x0, 48(t0);"						\
74	"cache	0x0, 64(t0);"						\
75	"cache	0x0, 80(t0);"						\
76	"cache	0x0, 96(t0);"						\
77	"cache	0x0, 112(t0);"						\
78	"bne	t0, t1, 2b;"						\
79	"addu	t0, t0, 128;"						\
80									\
81	/* Flush D-cache */						\
82	"li	t0, 0x80000000;"					\
83	"addu	t1, t0, t2;"						\
84									\
85"3:"									\
86	"lw	t2, 0(t0);"						\
87	"bne	t1, t0, 3b;"						\
88	"addiu	t0, t0, 4;"						\
89									\
90	/* Enable I-cache */						\
91	"nop;"								\
92	"mtc0	t6, $3;"						\
93	"nop;"								\
94	".set reorder;"							\
95)
96