1/*	$NetBSD: ifpga.c,v 1.31 2022/09/27 06:12:19 skrll Exp $ */
2
3/*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 *    products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32/*
33 * Integrator FPGA core logic support.
34 *
35 * The integrator board supports the core logic in an FPGA which is loaded
36 * at POR with a custom design.  This code supports the default logic as the
37 * board is shipped.
38 */
39
40#include <sys/cdefs.h>
41__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.31 2022/09/27 06:12:19 skrll Exp $");
42
43#include <sys/param.h>
44#include <sys/types.h>
45#include <sys/device.h>
46#include <sys/systm.h>
47#include <sys/kmem.h>
48#include <sys/null.h>
49
50#include <dev/pci/pcivar.h>
51#include <dev/pci/pciconf.h>
52
53#include <arm/cpufunc.h>
54
55#include "opt_pci.h"
56#include "pci.h"
57
58#include <evbarm/ifpga/ifpgamem.h>
59#include <evbarm/ifpga/ifpgavar.h>
60#include <evbarm/ifpga/ifpgareg.h>
61#include <evbarm/ifpga/ifpga_pcivar.h>
62#include <evbarm/dev/v360reg.h>
63
64#include <evbarm/integrator/int_bus_dma.h>
65#include "locators.h"
66
67/* Prototypes */
68static int  ifpga_match		(device_t, cfdata_t, void *);
69static void ifpga_attach	(device_t, device_t, void *);
70static int  ifpga_print		(void *, const char *);
71
72/* Drive and attach structures */
73CFATTACH_DECL_NEW(ifpga, sizeof(struct ifpga_softc),
74    ifpga_match, ifpga_attach, NULL, NULL);
75
76int ifpga_found;
77
78/* Default UART clock speed (we should make this a boot option).  */
79int ifpga_uart_clk = IFPGA_UART_CLK;
80
81#if NPCI > 0
82/* PCI handles */
83extern struct arm32_pci_chipset ifpga_pci_chipset;
84extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag;
85
86static struct bus_space ifpga_pci_io_tag;
87static struct bus_space ifpga_pci_mem_tag;
88#endif /* NPCI > 0 */
89
90extern struct bus_space ifpga_common_bs_tag;
91
92struct ifpga_softc *ifpga_sc;
93device_t ifpga_dev;
94
95/*
96 * Print the configuration information for children
97 */
98
99static int
100ifpga_print(void *aux, const char *pnp)
101{
102	struct ifpga_attach_args *ifa = aux;
103
104	if (ifa->ifa_addr != -1)
105		aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr);
106	if (ifa->ifa_irq != -1)
107		aprint_normal(" irq %d", ifa->ifa_irq);
108
109	return UNCONF;
110}
111
112static int
113ifpga_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
114{
115	struct ifpga_softc *sc = device_private(parent);
116	struct ifpga_attach_args ifa;
117	int tryagain;
118
119	do {
120		ifa.ifa_iot = sc->sc_iot;
121		ifa.ifa_addr = cf->cf_iobase;
122		ifa.ifa_irq = cf->cf_irq;
123		ifa.ifa_sc_ioh = sc->sc_sc_ioh;
124
125		tryagain = 0;
126		if (config_probe(parent, cf, &ifa)) {
127			config_attach(parent, cf, &ifa, ifpga_print, CFARGS_NONE);
128			tryagain = (cf->cf_fstate == FSTATE_STAR);
129		}
130	} while (tryagain);
131
132	return 0;
133}
134
135static int
136ifpga_match(device_t parent, cfdata_t cf, void *aux)
137{
138#if 0
139	struct mainbus_attach_args *ma = aux;
140
141	/* Make sure that we're looking for the IFPGA.  */
142	if (strcmp(ma->ma_name, ifpga_md.md_name))
143		return 0;
144#endif
145
146	/* We can only have one instance of the IFPGA.  */
147	if (ifpga_found)
148		return 0;
149
150	return 1;
151}
152
153static void
154ifpga_attach(device_t parent, device_t self, void *aux)
155{
156	struct ifpga_softc *sc = device_private(self);
157	u_int id, sysclk;
158	extern struct bus_space ifpga_common_bs_tag;
159#if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0
160	struct pciconf_resources *pcires;
161	struct ifpga_pci_softc *pci_sc;
162	struct pcibus_attach_args pci_pba;
163#endif
164
165	ifpga_intr_init();
166
167	ifpga_found = 1;
168
169#if NPCI > 0
170	/* But the PCI config space is quite large, so we have a linear region
171	   for that pre-allocated.  */
172
173	ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE);
174	ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0);
175#endif
176
177	sc->sc_iot = &ifpga_common_bs_tag;
178
179	ifpga_dev = self;
180	ifpga_sc = sc;
181
182	/* Now map in the IFPGA motherboard registers.  */
183	if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0,
184	    &sc->sc_sc_ioh))
185		panic("%s: Cannot map system controller registers",
186		    device_xname(self));
187
188	id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID);
189
190	printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >>
191	    IFPGA_SC_ID_BUILD_SHIFT);
192	switch (id & IFPGA_SC_ID_REV_MASK)
193	{
194	case IFPGA_SC_ID_REV_A:
195		printf("Rev A, ");
196		break;
197	case IFPGA_SC_ID_REV_B:
198		printf("Rev B, ");
199		break;
200	}
201
202	printf("Manufacturer ");
203	switch (id & IFPGA_SC_ID_MAN_MASK)
204	{
205	case IFPGA_SC_ID_MAN_ARM:
206		printf("ARM Ltd,");
207		break;
208	default:
209		printf("Unknown,");
210		break;
211	}
212
213	switch (id & IFPGA_SC_ID_ARCH_MASK)
214	{
215	case IFPGA_SC_ID_ARCH_ASBLE:
216		printf(" ASB, Little-endian,");
217		break;
218	case IFPGA_SC_ID_ARCH_AHBLE:
219		printf(" AHB, Little-endian,");
220		break;
221	default:
222		panic(" Unsupported bus");
223	}
224
225	printf("\n%s: FPGA ", device_xname(self));
226
227	switch (id & IFPGA_SC_ID_FPGA_MASK)
228	{
229	case IFPGA_SC_ID_FPGA_XC4062:
230		printf("XC4062");
231		break;
232	case IFPGA_SC_ID_FPGA_XC4085:
233		printf("XC4085");
234		break;
235	default:
236		printf("unknown");
237		break;
238	}
239
240	sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC);
241	sysclk &= IFPGA_SC_OSC_S_VDW;
242	sysclk += 8;
243
244	printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25);
245
246	/* Map the Interrupt controller */
247	if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE,
248	    BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh))
249		panic("%s: Cannot map irq controller registers",
250		    device_xname(self));
251
252	/* We can write to the IRQ/FIQ controller now.  */
253	ifpga_intr_postinit();
254
255	/* Map the core module */
256	if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0,
257	    &sc->sc_cm_ioh)) {
258		panic("%s: Cannot map core module registers",
259		    device_xname(self));
260	}
261
262	/* Map the timers */
263	if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0,
264	    &sc->sc_tmr_ioh))
265		panic("%s: Cannot map timer registers", device_xname(self));
266
267	printf("\n");
268
269#if NPCI > 0
270	pci_sc = kmem_alloc(sizeof(*pci_sc), KM_SLEEP);
271	pci_sc->sc_iot = &ifpga_pci_io_tag;
272	pci_sc->sc_memt = &ifpga_pci_mem_tag;
273
274	if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0,
275	    &pci_sc->sc_io_ioh)
276	    || bus_space_map(pci_sc->sc_iot,
277	    IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0,
278	    &pci_sc->sc_conf_ioh)
279	    || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE,
280	    IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh))
281		panic("%s: Cannot map pci memory", device_xname(self));
282
283	{
284		pcireg_t id_reg, class_reg;
285		char buf[1000];
286
287		id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh,
288		    V360_PCI_VENDOR);
289		class_reg = bus_space_read_4(pci_sc->sc_memt,
290		    pci_sc->sc_reg_ioh, V360_PCI_CC_REV);
291
292		pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf));
293		printf("%s: %s\n", device_xname(self), buf);
294	}
295
296#if defined(PCI_NETBSD_CONFIGURE)
297	pcires = pciconf_resource_init();
298
299	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
300	    0x00000000, IFPGA_PCI_IO_VSIZE);
301	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
302	    IFPGA_PCI_APP0_BASE, IFPGA_PCI_APP0_SIZE);
303	pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM,
304	    IFPGA_PCI_APP1_BASE, IFPGA_PCI_APP1_SIZE);
305
306	ifpga_pci_chipset.pc_conf_v = (void *)pci_sc;
307	pci_configure_bus(&ifpga_pci_chipset, pcires, 0,
308	    arm_dcache_align);
309	pciconf_resource_fini(pcires);
310
311	printf("pci_configure_bus done\n");
312#endif /* PCI_NETBSD_CONFIGURE */
313#endif /* NPCI > 0 */
314
315	/* Finally, search for children.  */
316	config_search(self, NULL,
317	    CFARGS(.search = ifpga_search,
318		   .iattr = "ifpga"));
319
320#if NPCI > 0
321	integrator_pci_dma_init(&ifpga_pci_bus_dma_tag);
322
323	pci_pba.pba_pc = &ifpga_pci_chipset;
324	pci_pba.pba_iot = &ifpga_pci_io_tag;
325	pci_pba.pba_memt = &ifpga_pci_mem_tag;
326	pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag;
327	pci_pba.pba_dmat64 = NULL;
328	pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
329	pci_pba.pba_bus = 0;
330	pci_pba.pba_bridgetag = NULL;
331
332	config_found(self, &pci_pba, pcibusprint,
333	    CFARGS(.iattr = "pcibus"));
334#endif
335}
336
337void
338ifpga_reset(void)
339{
340	bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh,
341	    IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET);
342}
343