1/* 2 * Copyright (c) 2002, 2005 Genetec corp. All rights reserved. 3 * Written by Hiroyuki Bessho for Genetec corp. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The name of Genetec corp. may not be used to endorse 14 * or promote products derived from this software without specific prior 15 * written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#ifndef _EVBARM_G42XXEB_REG_H 31#define _EVBARM_G42XXEB_REG_H 32 33#include <arm/xscale/pxa2x0reg.h> 34 35/* g42xxeb on-board IOs */ 36#define G42XXEB_PLDREG_BASE PXA2X0_CS3_START /* Phisical address */ 37#define G42XXEB_PLDREG_SIZE 0x00000100 38 39#define G42XXEB_AX88796_PBASE (PXA2X0_CS3_START+0x02000000) 40 41 42/* 43 * Logical mapping for onboard/integrated peripherals 44 * that are used while bootstrapping. 45 */ 46#define G42XXEB_IO_AREA_VBASE 0xfd000000 47#define G42XXEB_PLDREG_VBASE 0xfd000000 48#define G42XXEB_INTCTL_VBASE 0xfd100000 49#define G42XXEB_CLKMAN_VBASE 0xfd200000 50#define G42XXEB_GPIO_VBASE 0xfd300000 51#define G42XXEB_FFUART_VBASE 0xfd400000 52#define G42XXEB_BTUART_VBASE 0xfd500000 53 54/* 55 * Onboard register address 56 * (offset from G42XXEB_OBIO_PBASE) 57 */ 58#define G42XXEB_INTSTS1 0x0a 59#define G42XXEB_INTSTS2 0x0c 60#define G42XXEB_INTCNTL 0x0e 61#define G42XXEB_INTCNTH 0x10 62#define G42XXEB_INTMASK 0x14 63 64#define G42XXEB_INT_MMCSD 0 65#define G42XXEB_INT_SDIO 1 66#define G42XXEB_INT_EXT0 2 67#define G42XXEB_INT_EXT1 3 68#define G42XXEB_INT_USB 4 69#define G42XXEB_INT_ETH 5 70#define G42XXEB_INT_CODEC 6 71#define G42XXEB_INT_EXT2 7 72#define G42XXEB_INT_KEY 8 73#define G42XXEB_INT_EXT3 9 74 75#define G42XXEB_N_INTS 10 76 77/* interrupt type */ 78#define G42XXEB_INT_LEVEL_LOW 0 79#define G42XXEB_INT_LEVEL_HIGH 1 80#define G42XXEB_INT_EDGE_FALLING 4 81#define G42XXEB_INT_EDGE_RISING 5 82#define G42XXEB_INT_EDGE_BOTH 6 83 84 85#define G42XXEB_DIPSW 0x16 86#define G42XXEB_LED 0x18 87 88#define G42XXEB_RST 0x1a 89#define RST_ASIX88796 (1<<0) 90#define RST_EXT(n) (1<<((n)+1)) 91#define G42XXEB_EXTCTRL 0x1c 92#define G42XXEB_OPTBRDID 0x20 93#define G42XXEB_PLDVER 0x22 94 95 96#define G42XXEB_LCDCTL 0x28 97#define LCDCTL_BL_ON (1<<7) 98#define LCDCTL_DPSH (1<<1) 99#define LCDCTL_DPSV (1<<0) 100#define LCDCTL_BL_PWM_SHIFT 8 /* Backlight blightness */ 101#define LCDCTL_BL_PWN (0xff<<LCDCTL_BL_PWM_SHIFT) 102 103#define G42XXEB_KEYSCAN 0x2a 104#define KEYSCAN_SCAN_OUT 0x1f00 105#define KEYSCAN_SENSE_IN 0x0f 106#define G42XXEB_WP 0x2c // SD/MMC write protect status 107 108#define ioreg_read(a) (*(volatile unsigned *)(a)) 109#define ioreg_write(a,v) (*(volatile unsigned *)(a)=(v)) 110 111#define ioreg16_read(a) (*(volatile uint16_t *)(a)) 112#define ioreg16_write(a,v) (*(volatile uint16_t *)(a)=(v)) 113 114#define ioreg8_read(a) (*(volatile uint8_t *)(a)) 115#define ioreg8_write(a,v) (*(volatile uint8_t *)(a)=(v)) 116 117#define pldreg16_read(off) ioreg16_read(G42XXEB_PLDREG_VBASE+(off)) 118#define pldreg16_write(off,v) ioreg16_write(G42XXEB_PLDREG_VBASE+(off),v) 119#define pldreg8_read(off) ioreg8_read(G42XXEB_PLDREG_VBASE+(off)) 120#define pldreg8_write(off,v) ioreg8_write(G42XXEB_PLDREG_VBASE+(off),v) 121 122#endif /* _EVBARM_G42XXEB_REG_H */ 123