files.tsarm revision 1.5 
1#	$NetBSD: files.tsarm,v 1.5 2005/01/09 21:40:02 joff Exp $
2#
3# First try for arm-specific configuration info
4#
5
6# Use the generic ARM soft interrupt code.
7file	arch/arm/arm/softintr.c
8file	arch/evbarm/tsarm/tsarm_machdep.c
9
10# EP93xx Processor CPU support
11include "arch/arm/ep93xx/files.ep93xx"
12
13attach epsoc at mainbus
14
15attach epcom at epsoc with epcom_ts
16file	arch/evbarm/tsarm/epcom_ts.c
17
18define  tspldbus {}
19device	tspld: isabus, tspldbus, sysmon_wdog
20attach tspld at mainbus
21file	arch/evbarm/tsarm/tspld.c	tspld
22
23file	arch/evbarm/tsarm/isa/isa_machdep.c	isa
24file	arch/evbarm/tsarm/isa/isa_io.c		isa
25file	arch/evbarm/tsarm/isa/isa_io_asm.S	isa
26
27attach wdc at tspldbus with wdc_ts
28file 	arch/evbarm/tsarm/wdc_ts.c		wdc_ts
29
30device tsrtc: mc146818
31attach tsrtc at tspldbus
32file	arch/evbarm/tsarm/tsrtc.c		tsrtc
33
34device	tslcd: hd44780
35attach	tslcd at tspldbus
36file	arch/evbarm/tsarm/tslcd.c		tslcd
37
38# XXXX pcic here because it needs to be late.  The catch: pcic needs
39# to be late, so devices which attach to it are attached late.  But it
40# needs to be before its isa and pci attachments.  This answer is
41# non-optimal, but I don't have a better answer right now.
42
43# PCIC pcmcia controller
44# XXX this needs to be done very late, so it's done here.  This feels
45# like a kludge, but it might be for the best.
46
47defparam		PCIC_ISA_ALLOC_IOBASE
48defparam		PCIC_ISA_ALLOC_IOSIZE
49defparam		PCIC_ISA_INTR_ALLOC_MASK
50
51device	pcic: pcmciabus
52file	dev/ic/i82365.c			pcic
53
54# PCIC pcmcia controller on ISA bus.
55attach	pcic at isa with pcic_isa
56file	dev/isa/i82365_isa.c		pcic_isa
57
58# Code common to ISA and ISAPnP attachments
59file	dev/isa/i82365_isasubr.c	pcic_isa
60
61# this wants to be probed as late as possible.
62#
63# Machine-independent PCMCIA drivers
64#
65include	"dev/pcmcia/files.pcmcia"
66