1/* $NetBSD$ */ 2 3/*- 4 * Copyright (c) 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code was written by Alessandro Forin and Neil Pittman 8 * at Microsoft Research and contributed to The NetBSD Foundation 9 * by Microsoft Corporation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Reference: 35 * TBD MSR techreport by Richard Pittman and Alessandro Forin 36 * 37 * Definitions for the Xilinx ML40x dev boards with MSR's eMIPS. 38 */ 39 40#ifndef _MIPS32_EMIPS_EMIPSREG_H_ 41#define _MIPS32_EMIPS_EMIPSREG_H_ 1 42 43/* 44 * Peripheral Mapping Table (PMT) definitions 45 * 46 * Each entry in this table holds the physical address of a section of peripherals 47 * and the tag for the type of peripherals in that section. 48 * Peripherals of the same type go into the same section, which is subdivided 49 * as appropriate for that peripheral type. 50 * Each section is at least 64KB wide, each subdivision is at least 4KB wide. 51 * 52 * NB: This table grows *down* from the top of the address space 53 * The value 0xffffffff for an entry indicates the section is not populated. 54 * The tag 0xffff is therefore invalid. 55 * The end-of-table is indicated by the first invalid entry. 56 * 57 * Entries in the table are (preferably) in the processor's own byteorder. 58 * The first entry is for the table itself and has a known tag. 59 * From this software can verify the byteorder is correct. 60 * 61 * For each section we also define here its favorite placement in the address space. 62 * Software should verify the table for the ultimate truth, peripherals might 63 * or might not be present in the FPGA bitfile being used. 64 * 65 */ 66#ifndef __ASSEMBLER__ 67struct _Pmt { 68 69 volatile uint16_t TopOfPhysicalAddress; 70 volatile uint16_t Tag; 71}; 72#define ThePmt (((struct _Pmt *)0)-1) 73 74#endif /* !__ASSEMBLER__ */ 75 76/* 77 * Peripheral tags 78 */ 79# define PMTTAG_END_OF_TABLE 0xffff /* required, last entry */ 80# define PMTTAG_BRAM 0 81# define PMTTAG_PMT 1 /* required, first entry */ 82# define PMTTAG_SRAM 2 83# define PMTTAG_DDRAM 3 84# define PMTTAG_FLASH 4 85# define PMTTAG_INTERRUPT_CONTROLLER 5 86# define PMTTAG_USART 6 87# define PMTTAG_TIMER 7 88# define PMTTAG_WATCHDOG 8 89# define PMTTAG_GPIO 9 90# define PMTTAG_SYSTEM_ACE 10 91# define PMTTAG_LCD 11 92# define PMTTAG_PS2 12 93# define PMTTAG_VGA 13 94# define PMTTAG_ETHERNET 14 95# define PMTTAG_AC97 15 96# define PMTTAG_POWER_MGR 16 97# define PMTTAG_EXTENSION_CONTROLLER 17 98# define PMTTAG_ICAP 18 99# define PMTTAG_LAST_TAG_DEFINED 18 100 101/* 102 * Preferred addresses (nb: for the control registers of...) 103 */ 104# define BRAM_DEFAULT_ADDRESS (0xffff << 16) 105# define SRAM_0_DEFAULT_ADDRESS (0xfffd << 16) 106# define DDRAM_0_DEFAULT_ADDRESS (0xfffc << 16) 107# define FLASH_0_DEFAULT_ADDRESS (0xfffb << 16) 108# define INTERRUPT_CONTROLLER_DEFAULT_ADDRESS (0xfffa << 16) 109# define USART_DEFAULT_ADDRESS (0xfff9 << 16) 110# define TIMER_DEFAULT_ADDRESS (0xfff8 << 16) 111# define WATCHDOG_DEFAULT_ADDRESS (0xfff7 << 16) 112# define GPIO_DEFAULT_ADDRESS (0xfff6 << 16) 113# define IDE_DEFAULT_ADDRESS (0xfff5 << 16) 114# define LCD_DEFAULT_ADDRESS (0xfff4 << 16) 115# define PS2_DEFAULT_ADDRESS (0xfff3 << 16) 116# define VGA_DEFAULT_ADDRESS (0xfff2 << 16) 117# define ETHERNET_DEFAULT_ADDRESS (0xfff1 << 16) 118# define POWER_MGR_DEFAULT_ADDRESS (0xfff0 << 16) 119# define AC97_DEFAULT_ADDRESS (0xffef << 16) 120# define EXTENSION_CONTROLLER_DEFAULT_ADDRESS (0xffee << 16) 121# define ICAP_DEFAULT_ADDRESS (0xffed << 16) 122 123 124/* 125 * SRAM controller 126 */ 127#ifndef __ASSEMBLER__ 128struct _Sram { 129 volatile uint32_t BaseAddressAndTag; /* rw */ 130 volatile uint32_t Control; /* rw */ 131}; 132#else 133# define SRAMBT 0 134# define SRAMST 4 135#endif /* !__ASSEMBLER__ */ 136 137# define SRAMBT_TAG 0x0000ffff /* ro */ 138# define SRAMBT_BASE 0xffff0000 /* rw */ 139 140# define SRAMST_DELAY 0x0000000f /* rw */ 141# define SRAMST_BURST_INTERLEAVED 0x00000010 /* ro */ 142# define SRAMST_BURST_LINEAR 0x00000000 /* ro */ 143# define SRAMST_BURST_ENABLE 0x00000020 /* rw */ 144# define SRAMST_BURST_DISABLE 0x00000000 /* rw */ 145# define SRAMST_CLOCK_MASK 0x00000040 /* rw */ 146# define SRAMST_SLEEP 0x00000080 /* rw */ 147# define SRAMST_PARITY 0x00000f00 /* rw */ 148# define SRAMST_RESET 0x00001000 /* rw */ 149# define SRAMST_BUS_8 0x00002000 /* rw */ 150# define SRAMST_BUS_16 0x00004000 /* rw */ 151# define SRAMST_BUS_32 0x00008000 /* rw */ 152# define SRAMST_SIZE 0xffff0000 /* ro 153 * in bytes, masked */ 154 155/* 156 * DDRAM controller 157 */ 158#ifndef __ASSEMBLER__ 159struct _Ddram { 160 volatile uint32_t BaseAddressAndTag; /* rw */ 161 volatile uint32_t Control; /* rw */ 162 volatile uint32_t PreCharge; /* wo */ 163 volatile uint32_t Refresh; /* wo */ 164}; 165#else 166# define DDRAMBT 0 167# define DDRAMST 4 168# define DDRAMPC 8 169# define DDRAMRF 12 170# define DDRAMCTRL_SIZE 16 171#endif /* !__ASSEMBLER__ */ 172 173# define DDRAMBT_TAG 0x0000ffff /* ro */ 174# define DDRAMBT_BASE 0xffff0000 /* rw */ 175 176# define DDRAMST_RST 0x00000001 /* rw */ 177# define DDRAMST_CLR 0x00000002 /* rw */ 178# define DDRAMST_TSTEN 0x00000004 /* rw */ 179# define DDRAMST_BUF 0x00000008 /* rw */ 180# define DDRAMST_CALDNE 0x00000010 /* ro */ 181# define DDRAMST_CALFAIL 0x00000020 /* ro */ 182# define DDRAMST_SERR 0x00000040 /* ro */ 183# define DDRAMST_DERR 0x00000080 /* ro */ 184# define DDRAMST_BURST 0x00000f00 /* ro */ 185# define DDRAMST_OVF 0x00001000 /* ro */ 186# define DDRAMST_BUS8 0x00002000 /* ro */ 187# define DDRAMST_BUS16 0x00004000 /* ro */ 188# define DDRAMST_BUS32 0x00008000 /* ro */ 189# define DDRAMST_SIZE 0xffff0000 /* ro */ 190 191/* 192 * FLASH controller 193 */ 194#ifndef __ASSEMBLER__ 195struct _Flash { 196 volatile uint32_t BaseAddressAndTag; /* rw */ 197 volatile uint32_t Control; /* rw */ 198}; 199#else 200# define FLASHBT 0 201# define FLASHST 4 202#endif /* !__ASSEMBLER__ */ 203 204# define FLASHBT_TAG 0x0000ffff /* ro */ 205# define FLASHBT_BASE 0xffff0000 /* rw */ 206 207# define FLASHST_DELAY 0x0000000f /* rw */ 208# define FLASHST_RESET_PIN 0x00000010 /* rw */ 209# define FLASHST_RESET_CONTROLLER 0x00001000 /* rw */ 210# define FLASHST_BUS_8 0x00002000 /* rw */ 211# define FLASHST_BUS_16 0x00004000 /* rw */ 212# define FLASHST_BUS_32 0x00008000 /* rw */ 213# define FLASHST_SIZE 0xffff0000 /* ro 214 * in bytes, masked */ 215 216/* 217 * ARM RPS Interrupt Controller (AIC) 218 */ 219#ifndef __ASSEMBLER__ 220struct _Aic { 221 volatile uint32_t Tag; /* ro */ 222 volatile uint32_t IrqStatus; /* rw */ 223 volatile uint32_t IrqRawStatus; /* ro */ 224 volatile uint32_t IrqEnable; /* rw */ 225 volatile uint32_t IrqEnableClear; 226 volatile uint32_t IrqSoft; 227}; 228#else 229# define AICT 0 230# define AICS 4 231# define AICRS 8 232# define AICEN 12 233# define AICEC 16 234#endif /* !__ASSEMBLER__ */ 235 236# define AIC_TIMER 0 237# define AIC_SOFTWARE 1 238# define AIC_GPIO 2 239# define AIC_WATCHDOG 3 240# define AIC_SYSTEM_ACE 4 241# define AIC_ETHERNET 5 242# define AIC_PS2 6 243# define AIC_AC97 7 244# define AIC_USART 9 245# define AIC_EXTENSION_CONTROLLER 10 246# define AIC_ICAP 11 247# define AIC_SYSTEM_ACE2 12 248# define AIC_VGA 13 249# define AIC_EXTENSION_2 29 250# define AIC_EXTENSION_1 30 251# define AIC_EXTENSION_0 31 252 253# define AIC_TIMER_BIT (1 << AIC_TIMER) 254# define AIC_SOFTWARE_BIT (1 << AIC_SOFTWARE) 255# define AIC_GPIO_BIT (1 << AIC_GPIO) 256# define AIC_WATCHDOG_BIT (1 << AIC_WATCHDOG) 257# define AIC_SYSTEM_ACE_BIT (1 << AIC_SYSTEM_ACE) 258# define AIC_ETHERNET_BIT (1 << AIC_ETHERNET) 259# define AIC_PS2_BIT (1 << AIC_PS2) 260# define AIC_AC97_BIT (1 << AIC_AC97) 261# define AIC_USART_BIT (1 << AIC_USART) 262# define AIC_EXTENSION_CONTROLLER_BIT (1 << AIC_EXTENSION_CONTROLLER) 263# define AIC_ICAP_BIT (1 << AIC_ICAP) 264# define AIC_SYSTEM_ACE2_BIT (1 << AIC_SYSTEM_ACE2) 265# define AIC_VGA_BIT (1 << AIC_VGA) 266# define AIC_EXTENSION_2_BIT (1 << AIC_EXTENSION_2) 267# define AIC_EXTENSION_1_BIT (1 << AIC_EXTENSION_1) 268# define AIC_EXTENSION_0_BIT (1 << AIC_EXTENSION_0) 269 270/* 271 * General Purpose I/O pads controller (GPIO) 272 */ 273#ifndef __ASSEMBLER__ 274struct _Pio { 275 volatile uint32_t Tag; /* ro value=9 NB: All other registers RESET to 0 */ 276 volatile uint32_t Enable; /* rw READ: 0 => high-z, 1 => In/Out based on DIRECTION 277 * WRITE: 0 => no effect, 1 => pin is enabled for I/O */ 278 volatile uint32_t Disable; /* wo 0 => no effect, 1 => disabled, set in high-z */ 279 volatile uint32_t Direction; /* rw READ: 0 => input, 1 => output (if enabled) 280 * WRITE: 0 => no-effect, 1 => output */ 281 volatile uint32_t OutDisable; /* wo 0 => no effect, 1 => set for input */ 282 283 volatile uint32_t PinData; /* rw READ: 0 => LOW, 1 => HIGH 284 * WRITE: 0 => no effect, 1 => set pin HIGH */ 285 volatile uint32_t ClearData; /* wo 0 => no effect, 1 => set pin LOW */ 286 volatile uint32_t PinStatus; /* ro 0 => LOW, 1 => HIGH */ 287 288 volatile uint32_t IntrStatus; /* rw READ: 0 => none 1 => pending (regardless of INTRMASK) 289 * WRITE: 0 => no-effect, 1 => clear if pending */ 290 volatile uint32_t IntrEnable; /* rw READ: 0 => none, 1 => enabled 291 * WRITE: 0 => no-effect, 1 => enable */ 292 volatile uint32_t IntrDisable; /* wo 0 => no effect, 1 => disable */ 293 volatile uint32_t IntrTrigger; /* rw 0 => intr on level change, 1 => on transition */ 294 volatile uint32_t IntrNotLevel; /* rw 0 => HIGH, 1 => LOW -- Combinations: 295 * Trig Lev InterruptOn.. 296 * 0 0 level high 297 * 0 1 level low 298 * 1 0 low to high transition 299 * 1 1 high to low transition 300 */ 301 volatile uint32_t reserved[3]; /* ro padding to 64 bytes total */ 302}; 303#else 304# define PIOT 0 305# define PIOEN 4 306# define PIOD 8 307# define PIODIR 12 308# define PIOOD 16 309# define PIOPD 20 310# define PIOCD 24 311# define PIOPS 28 312# define PIOIS 32 313# define PIOIE 36 314# define PIOID 40 315# define PIOIT 44 316# define PIOINL 48 317#endif /* !__ASSEMBLER__ */ 318 319/* DIP switches on SW1 and their known uses */ 320# define PIO_SW1_1 0 321# define PIO_SW1_1_BIT (1 << PIO_SW1_1) 322# define PIO_SW1_2 1 323# define PIO_SW1_2_BIT (1 << PIO_SW1_2) 324# define PIO_SW1_3 2 325# define PIO_SW1_3_BIT (1 << PIO_SW1_3) 326# define PIO_SW1_4 3 327# define PIO_SW1_4_BIT (1 << PIO_SW1_4) 328# define PIO_SW1_5 4 329# define PIO_SW1_5_BIT (1 << PIO_SW1_5) 330# define PIO_SW1_6 5 331# define PIO_SW1_6_BIT (1 << PIO_SW1_6) 332# define PIO_SW1_7 6 333# define PIO_SW1_7_BIT (1 << PIO_SW1_7) 334# define PIO_SW1_8 7 335# define PIO_SW1_8_BIT (1 << PIO_SW1_8) 336# define SW1_BOOT_FROM_FLASH PIO_SW1_1_BIT /* else USART */ 337# define SW1_BOOT_FS_IN_FLASH PIO_SW1_2_BIT /* else serplexd via USART */ 338# define SW1_BOOT_FROM_SRAM PIO_SW1_3_BIT /* else USART */ 339/* LEDs */ 340# define PIO_LED_NORTH 8 341# define PIO_LED_NORTH_BIT (1 << PIO_LED_NORTH) 342# define PIO_LED_EAST 9 343# define PIO_LED_EAST_BIT (1 << PIO_LED_EAST) 344# define PIO_LED_SOUTH 10 345# define PIO_LED_SOUTH_BIT (1 << PIO_LED_SOUTH) 346# define PIO_LED_WEST 11 347# define PIO_LED_WEST_BIT (1 << PIO_LED_WEST) 348# define PIO_LED_CENTER 12 349# define PIO_LED_CENTER_BIT (1 << PIO_LED_CENTER) 350# define PIO_LED_GP0 13 351# define PIO_LED_GP0_BIT (1 << PIO_LED_GP0) 352# define PIO_LED_GP1 14 353# define PIO_LED_GP1_BIT (1 << PIO_LED_GP1) 354# define PIO_LED_GP2 15 355# define PIO_LED_GP2_BIT (1 << PIO_LED_GP2) 356# define PIO_LED_GP3 16 357# define PIO_LED_GP3_BIT (1 << PIO_LED_GP3) 358# define PIO_LED_ERROR1 17 359# define PIO_LED_ERROR1_BIT (1 << PIO_LED_ERROR1) 360# define PIO_LED_ERROR2 18 361# define PIO_LED_ERROR2_BIT (1 << PIO_LED_ERROR2) 362/* Buttons */ 363# define PIO_BUTTON_NORTH 19 364# define PIO_BUTTON_NORTH_BIT (1 << PIO_BUTTON_NORTH) 365# define PIO_BUTTON_EAST 20 366# define PIO_BUTTON_EAST_BIT (1 << PIO_BUTTON_EAST) 367# define PIO_BUTTON_SOUTH 21 368# define PIO_BUTTON_SOUTH_BIT (1 << PIO_BUTTON_SOUTH) 369# define PIO_BUTTON_WEST 22 370# define PIO_BUTTON_WEST_BIT (1 << PIO_BUTTON_WEST) 371# define PIO_BUTTON_CENTER 23 372# define PIO_BUTTON_CENTER_BIT (1 << PIO_BUTTON_CENTER) 373 374/* 375 * Universal Synch/Asynch Receiver/Transmitter (USART) 376 */ 377#ifndef __ASSEMBLER__ 378struct _Usart { 379 volatile uint32_t Tag; /* ro */ 380 volatile uint32_t Control; /* rw */ 381 volatile uint32_t IntrEnable; 382 volatile uint32_t IntrDisable; 383 volatile uint32_t IntrMask; 384 volatile uint32_t ChannelStatus; /* all these with.. */ 385 volatile uint32_t RxData; 386 volatile uint32_t TxData; 387 volatile uint32_t Baud; 388 volatile uint32_t Timeout; 389 volatile uint32_t reserved[6]; /* ro padding to 64 bytes total */ 390}; 391#else 392# define USARTT 0 393# define USARTC 4 394# define USARTIE 8 395# define USARTID 12 396# define USARTM 16 397# define USARTST 20 398# define USARTRX 24 399# define USARTTX 28 400# define USARTBD 32 401# define USARTTO 36 402#endif /* !__ASSEMBLER__ */ 403 404# define USC_RESET 0x00000001 405# define USC_RSTRX 0x00000004 406# define USC_RSTTX 0x00000008 407# define USC_RXEN 0x00000010 408# define USC_RXDIS 0x00000020 409# define USC_TXEN 0x00000040 410# define USC_TXDIS 0x00000080 411# define USC_RSTSTA 0x00000100 412# define USC_STTBRK 0x00000200 413# define USC_STPBRK 0x00000400 414# define USC_STTO 0x00000800 415# define USC_CLK_SENDA 0x00010000 416# define USC_BPC_9 0x00020000 417# define USC_CLKO 0x00040000 418# define USC_EVEN 0x00000000 419# define USC_ODD 0x00080000 420# define USC_SPACE 0x00100000 /* forced 0 */ 421# define USC_MARK 0x00180000 /* forced 1 */ 422# define USC_NONE 0x00200000 423# define USC_MDROP 0x00300000 424# define USC_BPC_5 0x00000000 425# define USC_BPC_6 0x00400000 426# define USC_BPC_7 0x00800000 427# define USC_BPC_8 0x00c00000 428# define USC_CLKDIV 0x0f000000 429# define USC_CLKDIV_1 0x00000000 430# define USC_CLKDIV_2 0x01000000 431# define USC_CLKDIV_4 0x02000000 432# define USC_CLKDIV_8 0x03000000 433# define USC_CLKDIV_16 0x04000000 434# define USC_CLKDIV_32 0x05000000 435# define USC_CLKDIV_64 0x06000000 436# define USC_CLKDIV_128 0x07000000 437# define USC_CLKDIV_EXT 0x08000000 438# define USC_1STOP 0x00000000 439# define USC_1_5STOP 0x10000000 440# define USC_2STOP 0x20000000 441# define USC_ECHO 0x40000000 /* rx->tx, tx disabled */ 442# define USC_LOOPBACK 0x80000000 /* tx->rx, rx/tx disabled */ 443# define USC_ECHO2 0xc0000000 /* rx->tx, rx disabled */ 444 445# define USI_RXRDY 0x00000001 446# define USI_TXRDY 0x00000002 447# define USI_RXBRK 0x00000004 448# define USI_ENDRX 0x00000008 449# define USI_ENDTX 0x00000010 450# define USI_OVRE 0x00000020 451# define USI_FRAME 0x00000040 452# define USI_PARE 0x00000080 453# define USI_TIMEOUT 0x00000100 454# define USI_TXEMPTY 0x00000200 455 456/* 457 * Timer/Counter (TC) 458 */ 459#ifndef __ASSEMBLER__ 460struct _Tc { 461 volatile uint32_t Tag; /* ro */ 462 volatile uint32_t Control; /* rw */ 463 volatile uint64_t FreeRunning; 464 volatile uint32_t DownCounterHigh; /* rw */ 465 volatile uint32_t DownCounter; /* rw */ 466 volatile uint32_t reserved[2]; /* ro padding to 32 bytes total */ 467}; 468#else 469# define TCT 0 470# define TCC 4 471# define TCFH 8 472# define TCFL 12 473# define TCCH 16 474# define TCCL 20 475#endif /* !__ASSEMBLER__ */ 476 477# define TCCT_ENABLE 0x00000001 478# define TCCT_INT_ENABLE 0x00000002 479# define TCCT_CLKO 0x00000008 480# define TCCT_RESET 0x00000010 481# define TCCT_FINTEN 0x00000020 482# define TCCT_CLOCK 0x000000c0 483# define TCCT_INTERRUPT 0x00000100 484# define TCCT_FINT 0x00000200 485# define TCCT_OVERFLOW 0x00000400 486# define TCCT_OVERRUN 0x00000800 487 488/* 489 * LCD controller 490 */ 491#ifndef __ASSEMBLER__ 492struct _Lcd { 493 volatile uint32_t TypeAndTag; /* ro */ 494 volatile uint32_t Control; /* rw */ 495 volatile uint32_t Data; /* wo */ 496 volatile uint32_t Refresh; /* wo */ 497}; 498#else 499# define LCDBT 0 500# define LCDST 4 501# define LCDPC 8 502# define LCDRF 12 503#endif /* !__ASSEMBLER__ */ 504 505# define LCDBT_TAG 0x0000ffff /* ro */ 506# define LCDBT_TYPE 0xffff0000 /* ro */ 507 508# define LCDST_RST 0x00000001 /* rw */ 509/* other bits are type-specific */ 510 511/* 512 * Watchdog Timer (WD) 513 */ 514#ifndef __ASSEMBLER__ 515struct _Wd { 516 volatile uint32_t Tag; /* ro */ 517 volatile uint32_t OvflMode; 518 volatile uint32_t ClockMode; 519 volatile uint32_t Control; 520 volatile uint32_t Status; 521 volatile uint32_t reserved[3]; /* ro padding to 32 bytes total */ 522}; 523#else 524# define WDT 0 525# define WDO 4 526# define WDM 8 527# define WDC 12 528# define WDS 16 529#endif /* !__ASSEMBLER__ */ 530 531/* 532 * Power Management Controller (PMC) 533 */ 534#ifndef __ASSEMBLER__ 535struct _Pmc { 536 volatile uint32_t Tag; /* ro */ 537 volatile uint32_t SystemPowerEnable; /* rw */ 538 volatile uint32_t SystemPowerDisable; /* wo */ 539 volatile uint32_t PeripheralPowerEnable; /* rw */ 540 volatile uint32_t PeripheralPowerDisable; /* wo */ 541 volatile uint32_t reserved[3]; /* ro padding to 32 bytes total */ 542}; 543#else 544# define PMCT 0 545# define PMCSE 4 546# define PMCSD 8 547# define PMCPE 12 548# define PMCPD 16 549#endif /* !__ASSEMBLER__ */ 550 551# define PMCSC_CPU 0x00000001 552 553/* more as we get more.. */ 554# define PMCPC_USART 0x00000001 555 556 557/* 558 * System ACE Controller (SAC) 559 */ 560 561#ifndef __ASSEMBLER__ 562struct _Sac { 563 volatile uint32_t Tag; /*0x00000000 */ 564 volatile uint32_t Control; /*0x00000004 */ 565 volatile uint32_t reserved0[30]; 566 volatile uint32_t BUSMODEREG; /*0x00000080 */ 567 volatile uint32_t STATUS; /*0x00000084 */ 568 volatile uint32_t ERRORREG; /*0x00000088 */ 569 volatile uint32_t CFGLBAREG; /*0x0000008c */ 570 volatile uint32_t MPULBAREG; /*0x00000090 */ 571 volatile uint16_t VERSIONREG; /*0x00000094 */ 572 volatile uint16_t SECCNTCMDREG; /*0x00000096 */ 573 volatile uint32_t CONTROLREG; /*0x00000098 */ 574 volatile uint16_t reserved1[1]; 575 volatile uint16_t FATSTATREG; /*0x0000009e */ 576 volatile uint32_t reserved2[8]; 577 volatile uint32_t DATABUFREG[16]; /*0x000000c0 */ 578}; 579#endif /* !__ASSEMBLER__ */ 580 581/* volatile uint32_t Tag; 0x00000000 */ 582# define SAC_TAG 0x0000ffff 583 584/* volatile uint32_t Control; 0x00000004 */ 585# define SAC_SIZE 0x0000ffff 586# define SAC_RST 0x00010000 587# define SAC_BUS8 0x00020000 588# define SAC_BUS16 0x00040000 589# define SAC_BUS32 0x00080000 590# define SAC_IRQ 0x00100000 591# define SAC_BRDY 0x00200000 592# define SAC_INTMASK 0x00c00000 593# define SAC_TDELAY 0x0f000000 594# define SAC_BUFW8 0x10000000 595# define SAC_BUFW16 0x20000000 596# define SAC_BUFW32 0x40000000 597# define SAC_DEBUG 0x80000000 598 599/* volatile uint32_t BUSMODEREG; 0x00000080 */ 600# define SAC_MODE16 0x00000001 601 602/* volatile uint32_t STATUS; 0x00000084 */ 603# define SAC_CFGLOCK 0x00000001 604# define SAC_MPULOCK 0x00000002 605# define SAC_CFGERROR 0x00000004 606# define SAC_CFCERROR 0x00000008 607# define SAC_CFDETECT 0x00000010 608# define SAC_DATABUFRDY 0x00000020 609# define SAC_DATABUFMODE 0x00000040 610# define SAC_CFGDONE 0x00000080 611# define SAC_RDYFORCFCMD 0x00000100 612# define SAC_CFGMODEPIN 0x00000200 613# define SAC_CFGADDRPINS 0x0000e000 614# define SAC_CFBSY 0x00020000 615# define SAC_CFRDY 0x00040000 616# define SAC_CFDWF 0x00080000 617# define SAC_CFDSC 0x00100000 618# define SAC_CFDRQ 0x00200000 619# define SAC_CFCORR 0x00400000 620# define SAC_CFERR 0x00800000 621 622/* volatile uint32_t ERRORREG; 0x00000088 */ 623# define SAC_CARDRESETERR 0x00000001 624# define SAC_CARDRDYERR 0x00000002 625# define SAC_CARDREADERR 0x00000004 626# define SAC_CARDWRITEERR 0x00000008 627# define SAC_SECTORRDYERR 0x00000010 628# define SAC_CFGADDRERR 0x00000020 629# define SAC_CFGFAILED 0x00000040 630# define SAC_CFGREADERR 0x00000080 631# define SAC_CFGINSTRERR 0x00000100 632# define SAC_CFGINITERR 0x00000200 633# define SAC_CFBBK 0x00000800 634# define SAC_CFUNC 0x00001000 635# define SAC_CFIDNF 0x00002000 636# define SAC_CFABORT 0x00004000 637# define SAC_CFAMNF 0x00008000 638 639/* volatile uint16_t VERSIONREG; 0x00000094 */ 640# define SAC_VERREV 0x000000ff 641# define SAC_VERMINOR 0x00000f00 642# define SAC_VERMAJOR 0x0000f000 643 644/* volatile uint16_t SECCNTCMDREG; 0x00000096 */ 645# define SAC_SECCCNT 0x000000ff 646# define SAC_CMD 0x00000700 647# define SAC_CMD_RESETMEMCARD 0x00000100 648# define SAC_CMD_IDENTIFYMEMCARD 0x00000200 649# define SAC_CMD_READMEMCARDDATA 0x00000300 650# define SAC_CMD_WRITEMEMCARDDATA 0x00000400 651# define SAC_CMD_ABORT 0x00000600 652 653/* volatile uint32_t CONTROLREG; 0x00000098 */ 654# define SAC_FORCELOCKREQ 0x00000001 655# define SAC_LOCKREQ 0x00000002 656# define SAC_FORCECFGADDR 0x00000004 657# define SAC_FORCECFGMODE 0x00000008 658# define SAC_CFGMODE 0x00000010 659# define SAC_CFGSTART 0x00000020 660# define SAC_CFGSEL 0x00000040 661# define SAC_CFGRESET 0x00000080 662# define SAC_DATABUFRDYIRQ 0x00000100 663# define SAC_ERRORIRQ 0x00000200 664# define SAC_CFGDONEIRQ 0x00000400 665# define SAC_RESETIRQ 0x00000800 666# define SAC_CFGPROG 0x00001000 667# define SAC_CFGADDRBIT 0x0000e000 668# define SAC_CFGADDR_0 0x00000000 669# define SAC_CFGADDR_1 0x00002000 670# define SAC_CFGADDR_2 0x00004000 671# define SAC_CFGADDR_3 0x00006000 672# define SAC_CFGADDR_4 0x00008000 673# define SAC_CFGADDR_5 0x0000a000 674# define SAC_CFGADDR_6 0x0000c000 675# define SAC_CFGADDR_7 0x0000e000 676# define SAC_CFGRSVD 0x00070000 677 678/* volatile uint16_t FATSTATREG; 0x0000009e */ 679# define SAC_MBRVALID 0x00000001 680# define SAC_PBRVALID 0x00000002 681# define SAC_MBRFAT12 0x00000004 682# define SAC_PBRFAT12 0x00000008 683# define SAC_MBRFAT16 0x00000010 684# define SAC_PBRFAT16 0x00000020 685# define SAC_CALCFAT12 0x00000040 686# define SAC_CALCFAT16 0x00000080 687 688/* 689 * Extension Controller (EC) 690 */ 691 692#define EC_MAX_BATS 5 693#ifndef __ASSEMBLER__ 694struct _Ec { 695 volatile uint32_t Tag; /*0x00000000 */ 696 volatile uint32_t Control; /*0x00000004 */ 697 volatile uint32_t SlotStatusAndTag; /*0x00000008 */ 698 volatile uint32_t BatOrSize[EC_MAX_BATS]; /*0x0000000c */ 699}; 700#endif /* !__ASSEMBLER__ */ 701 702/* volatile uint32_t Tag; 0x00000000 */ 703# define ECT_TAG 0x0000ffff 704 705/* volatile uint32_t Control; 0x00000004 */ 706# define ECC_SIZE 0x0000ffff 707# define ECC_RST 0x00010000 708# define ECC_IRQ 0x00020000 /* write-one-to-clear */ 709# define ECC_IRQ_ENABLE 0x00040000 710# define ECC_INT_LOAD 0x00100000 711# define ECC_INT_UNLOAD 0x00200000 712# define ECC_SLOTNO 0xff000000 713# define ECC_SLOTNO_SHIFT 24 714# define ECC_WANTS_INTERRUPT 0x00400000 /* extension needs interrupt */ 715# define ECC_PRIVILEDGED 0x00800000 /* extension needs priv interface */ 716 717/* volatile uint32_t SlotStatusAndTag; 0x00000008 */ 718# define ECS_TAG 0x0000ffff /* of the selected slot */ 719# define ECS_STATUS 0x00ff0000 720# define ECS_ABSENT 0x00000000 /* not loaded */ 721# define ECS_CONFIG 0x00010000 /* needs configuration */ 722# define ECS_RUN 0x00020000 /* running ok */ 723# define ECS_PM0 0x00030000 /* power management state 0 */ 724# define ECS_PM1 0x00040000 /* power management state 1 */ 725# define ECS_PM2 0x00050000 /* power management state 2 */ 726 727/* volatile uint32_t BatOrSize[5]; 0x0000000c */ 728/* In the CONFIG state reads the size (flipped decode mask) for the corresponding bat */ 729# define ECB_SIZE_NONE 0x00000000 730# define ECB_SIZE_4 0x00000003 731# define ECB_SIZE_8 0x00000007 /* and so on, 2^N */ 732/* In non-CONFIG states reads the value of the corresponding Base Address Translation */ 733/* In all states, writes back to the corresponding BAT */ 734# define ECB_BAT_VALID 0x00000001 735# define ECB_BAT 0xfffffff8 736 737/* 738 * Common interface for packet-based device interfaces (CPBDI) 739 */ 740 741#ifndef __ASSEMBLER__ 742#define CPBDI_STRUCT_DECLARATION { \ 743 volatile uint32_t Tag; /* ro */ \ 744 volatile uint32_t Control; /* rw */ \ 745 /* FIFO interface. Write-> input FIFO; Read-> output FIFO */ \ 746 volatile uint32_t SizeAndFlags; \ 747 volatile uint32_t BufferAddressHi32; \ 748 volatile uint32_t BufferAddressLo32; /* write/read of this word acts */ \ 749 volatile uint32_t Pad[3]; /* round to 32bytes */ \ 750} 751 752struct _Cpbdi CPBDI_STRUCT_DECLARATION; 753#else 754# define CPBDIT 0 755# define CPBDIC 4 756# define CPBDIS 8 757# define CPBDIH 12 758# define CPBDIL 16 759# define CPBDI_SIZE 32 760#endif /* !__ASSEMBLER__ */ 761 762/* Common defines for Control register */ 763# define CPBDI_RESET 0x00000001 /* autoclear */ 764# define CPBDI_INTEN 0x00000002 /* interrupt enable */ 765# define CPBDI_DONE 0x00000004 /* interrupt pending aka done */ 766# define CPBDI_IF_FULL 0x00000010 /* input fifo full */ 767# define CPBDI_OF_EMPTY 0x00000020 /* output fifo empty */ 768# define CPBDI_URUN 0x00000040 /* recvr ran out of buffers */ 769# define CPBDI_ERROR 0x80000000 /* unrecoverable error */ 770 771/* Common defines for SizeAndFlags register */ 772# define CPBDI_F_MASK 0xf0000000 773# define CPBDI_F_DONE 0x80000000 774# define CPBDI_F_XMIT 0x00000000 775# define CPBDI_F_RECV 0x10000000 776# define CPBDI_F_CMD 0x20000000 777 778/* 779 * Ethernet interface (ENIC) 780 */ 781 782#ifndef __ASSEMBLER__ 783struct _Enic CPBDI_STRUCT_DECLARATION; 784#else 785# define ENICT CPBDIT 786# define ENICC CPBDIC 787# define ENICS CPBDIS 788# define ENICH CPBDIH 789# define ENICL CPBDIL 790# define ENIC_SIZE CPBDI_SIZE 791#endif /* !__ASSEMBLER__ */ 792 793# define EC_RESET CPBDI_RESET 794# define EC_INTEN CPBDI_INTEN 795# define EC_DONE CPBDI_DONE 796# define EC_RXDIS 0x00000008 /* recv disabled */ 797# define EC_IF_FULL CPBDI_IF_FULL 798# define EC_OF_EMPTY CPBDI_OF_EMPTY 799# define EC_URUN CPBDI_URUN 800# define EC_ERROR CPBDI_ERROR 801# define EC_WMASK 0x0000000b /* user-writeable bits */ 802 803# define ES_F_MASK CPBDI_F_MASK 804# define ES_F_DONE CPBDI_F_DONE 805# define ES_F_XMIT CPBDI_F_XMIT 806# define ES_F_RECV CPBDI_F_RECV 807# define ES_F_CMD CPBDI_F_CMD 808# define ES_S_MASK 0xFFFF 809 810/* Command codes in a command buffer (first byte) 811 */ 812#define ENIC_CMD_NOP 0x00 813#define ENIC_CMD_GET_INFO 0x01 814#ifndef __ASSEMBLER__ 815typedef struct { 816 uint8_t InputFifoSize; 817 uint8_t OutputFifoSize; 818 uint8_t CompletionFifoSize; 819 uint8_t ErrorCount; 820 uint16_t FramesDropped; 821 uint16_t Reserved; 822} ENIC_INFO, *PENIC_INFO; 823#endif /* !__ASSEMBLER__ */ 824 825#define ENIC_CMD_GET_ADDRESS 0x02 826#ifndef __ASSEMBLER__ 827typedef struct { 828 uint8_t Mac[6]; 829} ENIC_MAC, *PENIC_MAC; 830#endif /* !__ASSEMBLER__ */ 831 832/* 833 * Internal Configuration Access Point (ICAP) interface 834 */ 835 836#ifndef __ASSEMBLER__ 837struct _Icap CPBDI_STRUCT_DECLARATION; 838#else 839# define ICAPT CPBDIT 840# define ICAPC CPBDIC 841# define ICAPS CPBDIS 842# define ICAPH CPBDIH 843# define ICAPL CPBDIL 844# define ICAP_SIZE CPBDI_SIZE 845#endif /* !__ASSEMBLER__ */ 846 847# define ICAPC_RESET CPBDI_RESET 848# define ICAPC_INTEN CPBDI_INTEN 849# define ICAPC_DONE CPBDI_DONE 850# define ICAPC_IF_FULL CPBDI_IF_FULL 851# define ICAPC_OF_EMPTY CPBDI_OF_EMPTY 852# define ICAPC_ERROR CPBDI_ERROR 853# define ICAPC_WMASK 0x00000007 /* user-writeable bits */ 854 855# define ICAPS_F_MASK CPBDI_F_MASK 856# define ICAPS_F_DONE CPBDI_F_DONE 857# define ICAPS_F_XMIT CPBDI_F_XMIT 858# define ICAPS_F_RECV CPBDI_F_RECV 859# define ICAPS_F_CMD CPBDI_F_CMD /* TBD */ 860# define ICAPS_S_MASK 0x0FFFFFFF 861 862/* 863 * Extensible Video Graphic Array (EVGA) interface 864 */ 865 866#ifndef __ASSEMBLER__ 867struct _Evga CPBDI_STRUCT_DECLARATION; 868#else 869# define EVGAT CPBDIT 870# define EVGAC CPBDIC 871# define EVGAS CPBDIS 872# define EVGAH CPBDIH 873# define EVGAL CPBDIL 874# define EVGA_SIZE CPBDI_SIZE 875#endif /* !__ASSEMBLER__ */ 876 877# define EVGAC_RESET CPBDI_RESET 878# define EVGAC_INTEN CPBDI_INTEN 879# define EVGAC_DONE CPBDI_DONE 880# define EVGAC_IF_FULL CPBDI_IF_FULL 881# define EVGAC_OF_EMPTY CPBDI_OF_EMPTY 882# define EVGAC_ERROR CPBDI_ERROR 883# define EVGAC_WMASK 0x00000007 /* user-writeable bits */ 884 885# define EVGAS_F_MASK CPBDI_F_MASK 886# define EVGAS_F_DONE CPBDI_F_DONE 887# define EVGAS_F_XMIT CPBDI_F_XMIT 888# define EVGAS_F_RECV CPBDI_F_RECV 889# define EVGAS_F_CMD CPBDI_F_CMD 890# define EVGAS_S_MASK 0x0FFFFFFF 891 892/* Command codes in a command buffer (first byte) */ 893#define EVGA_CMD_NOP 0x00 894#define EVGA_CMD_IDENTIFY 0x01 895#ifndef __ASSEMBLER__ 896typedef struct { 897 uint8_t CommandEcho; 898 uint8_t InterfaceVersion; 899 uint16_t Size; /* of this structure, all bytes counted */ 900 uint16_t PciVendorId; /* See PCI catalog */ 901 uint16_t PciProductId; /* See PCI catalog */ 902 uint32_t StandardCaps; /* TBD */ 903 uint8_t InputFifoSize; 904 uint8_t OutputFifoSize; 905 uint8_t CompletionFifoSize; 906 uint8_t ErrorCount; 907 /* More as needed */ 908} EVGA_IDENTIFY, *PEVGA_IDENTIFY; 909#endif /* !__ASSEMBLER__ */ 910#define EVGA_IDENTIFY_BIG_ENDIAN 0x00 911#define EVGA_IDENTIFY_LITTLE_ENDIAN 0x80 912#define EVGA_IDENTIFY_VERSION_1 0x01 913 914 915#define EVGA_CMD_2D_SET_BASE 0x02 916#define EVGA_CMD_2D_GET_BASE 0x03 917#ifndef __ASSEMBLER__ 918typedef struct { 919 uint8_t CommandEcho; 920 uint8_t Pad[3]; 921 uint32_t AddressLow32; 922 uint32_t AddressHigh32; 923} EVGA_2D_BASE, *PEVGA_2D_BASE; 924 925#endif /* !__ASSEMBLER__ */ 926 927 928 929#endif /* _MIPS32_EMIPS_EMIPSREG_H_ */ 930