1/* $NetBSD: mfp.h,v 1.5 2003/05/03 18:10:47 wiz Exp $ */ 2 3/* 4 * Copyright (c) 1995 Leo Weppelman. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#ifndef _MACHINE_MFP_H 29#define _MACHINE_MFP_H 30 31/* 32 * Atari TT hardware: MFP1/MFP2 33 * Motorola 68901 Multi-Function Peripheral 34 */ 35 36#define MFP ((struct mfp *)AD_MFP) 37#define MFP2 ((struct mfp *)AD_MFP2) 38 39#ifdef _MILANHW_ 40#define __MR(n) (3 + (4 * n)) 41#endif 42#ifdef _ATARIHW_ 43#define __MR(n) (1 + (2 * n)) 44#endif 45 46struct mfp { 47 volatile u_char mfb[__MR(24)-1]; /* Sparse */ 48}; 49 50#define mf_gpip mfb[__MR(0) ] /* gen-purp I/O interrupt port */ 51#define mf_aer mfb[__MR(1) ] /* active edge register */ 52#define mf_ddr mfb[__MR(2) ] /* data direction register */ 53#define mf_iera mfb[__MR(3) ] /* interrupt enable register A */ 54#define mf_ierb mfb[__MR(4) ] /* interrupt enable register B */ 55#define mf_ipra mfb[__MR(5) ] /* interrupt pending register A */ 56#define mf_iprb mfb[__MR(6) ] /* interrupt pending register B */ 57#define mf_isra mfb[__MR(7) ] /* interrupt in-service register A */ 58#define mf_isrb mfb[__MR(8) ] /* interrupt in-service register B */ 59#define mf_imra mfb[__MR(9) ] /* interrupt mask register A */ 60#define mf_imrb mfb[__MR(10)] /* interrupt mask register B */ 61#define mf_vr mfb[__MR(11)] /* vector register */ 62#define mf_tacr mfb[__MR(12)] /* timer control register A */ 63#define mf_tbcr mfb[__MR(13)] /* timer control register B */ 64#define mf_tcdcr mfb[__MR(14)] /* timer control register C+D */ 65#define mf_tadr mfb[__MR(15)] /* timer data register A */ 66#define mf_tbdr mfb[__MR(16)] /* timer data register B */ 67#define mf_tcdr mfb[__MR(17)] /* timer data register C */ 68#define mf_tddr mfb[__MR(18)] /* timer data register D */ 69#define mf_scr mfb[__MR(19)] /* synchronous character register */ 70#define mf_ucr mfb[__MR(20)] /* USART control register */ 71#define mf_rsr mfb[__MR(21)] /* receiver status register */ 72#define mf_tsr mfb[__MR(22)] /* transmitter status register */ 73#define mf_udr mfb[__MR(23)] /* USART data register */ 74 75/* names of IO port bits: */ 76#define IO_PBSY 0x01 /* Parallel Busy */ 77#define IO_SDCD 0x02 /* Serial Data Carrier Detect */ 78#define IO_SCTS 0x04 /* Serial Clear To Send */ 79#define IO_ISA1 0x08 /* ISA slot1 [ Hades only ] */ 80#define IO_AINT 0x10 /* ACIA interrupt (KB or MIDI) */ 81#define IO_DINT 0x20 /* DMA interrupt (FDC or HDC) */ 82#define IO_SRI 0x40 /* Serial Ring Indicator */ 83#define IO_MONO 0x80 /* Monochrome Monitor Detect */ 84#define IO_ISA2 0x80 /* ISA slot2 [ Hades only ] */ 85 86/* names of interrupts in register A: MFP1 */ 87#define IA_MONO 0x80 /* IO_MONO */ 88#define IA_ISA2 0x80 /* IO_ISA2 */ 89#define IA_SRI 0x40 /* IO_SRI */ 90#define IA_TIMA 0x20 /* Timer A */ 91#define IA_RRDY 0x10 /* Serial Receiver Ready(=Full) */ 92#define IA_RERR 0x08 /* Serial Receiver Error */ 93#define IA_TRDY 0x04 /* Serial Transmitter Ready(=Empty) */ 94#define IA_TERR 0x02 /* Serial Transmitter Error */ 95#define IA_TIMB 0x01 /* Timer B */ 96 97/* names of interrupts in register A: MFP2 */ 98#define IA_SCSI 0x80 /* SCSI-controller */ 99#define IA_RTC 0x40 /* Real Time Clock */ 100#define IA_TIMA2 0x20 /* Timer A */ 101/* 0x10 *//* reserved */ 102/* 0x08 *//* reserved */ 103/* 0x04 *//* reserved */ 104/* 0x02 *//* reserved */ 105#define IA_TIMB2 0x01 /* Timer B */ 106 107/* names of interrupts in register B: MFP1*/ 108#define IB_DINT 0x80 /* IO_DINT: from DMA devices */ 109#define IB_AINT 0x40 /* IO_AINT: from kbd or midi */ 110#define IB_TIMC 0x20 /* Timer C */ 111#define IB_TIMD 0x10 /* Timer D */ 112#define IB_ISA1 0x08 /* ISA1 interrupt [ Hades only ] */ 113#define IB_SCTS 0x04 /* IO_SCTS */ 114#define IB_SDCD 0x02 /* IO_SDCD */ 115#define IB_PBSY 0x01 /* IO_PBSY */ 116 117/* names of interrupts in register B: MFP2*/ 118#define IB_SCDM 0x80 /* SCSI-DMA */ 119#define IB_DCHG 0x40 /* Diskette change */ 120/* 0x20 *//* reserved */ 121/* 0x10 *//* reserved */ 122#define IB_RISB 0x80 /* Serial Ring indicator SCC port B */ 123#define IB_DMSC 0x40 /* SCC-DMA */ 124#define IB_J602_3 0x02 /* Pin 3 J602 */ 125#define IB_J602_1 0x01 /* Pin 1 J602 */ 126 127/* bits in VR: */ 128#define V_S 0x08 /* software end-of-interrupt mode */ 129#define V_V 0xF0 /* four high bits of vector */ 130 131/* bits in TCR: */ 132/* 0x07 *//* divider */ 133#define T_STOP 0x00 /* don't count */ 134#define T_Q004 0x01 /* divide by 4 */ 135#define T_Q010 0x02 /* divide by 10 */ 136#define T_Q016 0x03 /* divide by 16 */ 137#define T_Q050 0x04 /* divide by 50 */ 138#define T_Q064 0x05 /* divide by 64 */ 139#define T_Q100 0x06 /* divide by 100 */ 140#define T_Q200 0x07 /* divide by 200 */ 141#define T_EXTI 0x08 /* use extern impulse */ 142#define T_LOWO 0x10 /* force output low */ 143 144/* bits in UCR: */ 145/* 0x01 *//* not used */ 146#define U_EVEN 0x02 /* even parity */ 147#define U_PAR 0x04 /* use parity */ 148/* 0x18 *//* sync/async and stop bits */ 149#define U_SYNC 0x00 /* synchrone */ 150#define U_ST1 0x08 /* async, 1 stop bit */ 151#define U_ST1_5 0x10 /* async, 1.5 stop bit */ 152#define U_ST2 0x18 /* async, 2 stop bits */ 153/* 0x60 *//* number of data bits */ 154#define U_D8 0x00 /* 8 data bits */ 155#define U_D7 0x20 /* 7 data bits */ 156#define U_D6 0x40 /* 6 data bits */ 157#define U_D5 0x60 /* 5 data bits */ 158#define U_Q16 0x80 /* divide clock by 16 */ 159 160/* bits in RSR: */ 161#define RS_ENA 0x01 /* Receiver Enable */ 162#define RS_STRIP 0x02 /* Synchronous Strip Enable */ 163#define RS_CIP 0x04 /* Character in Progress */ 164#define RS_BREAK 0x08 /* Break Detected */ 165#define RS_FE 0x10 /* Frame Error */ 166#define RS_PE 0x20 /* Parity Error */ 167#define RS_OE 0x40 /* Overrun Error */ 168#define RS_FULL 0x80 /* Buffer Full */ 169 170/* bits in TSR: */ 171#define TS_ENA 0x01 /* Transmitter Enable */ 172/* 0x06 *//* state of dead transmitter output */ 173#define TS_TRI 0x00 /* Quiet Output Tristate */ 174#define TS_LOW 0x02 /* Quiet Output Low */ 175#define TS_HIGH 0x04 /* Quiet Output High */ 176#define TS_BACK 0x06 /* Loop Back Mode */ 177#define TS_BREAK 0x08 /* Break Detected */ 178#define TS_EOT 0x10 /* End of Transmission */ 179#define TS_TURN 0x20 /* Auto Turnaround */ 180#define TS_UE 0x40 /* Underrun Error */ 181#define TS_EMPTY 0x80 /* Buffer Empty */ 182#endif /* _MACHINE_MFP_H */ 183