zs.c revision 1.7
1/* $NetBSD: zs.c,v 1.7 1995/06/28 04:30:42 cgd Exp $ */ 2 3/* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49/* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56#include <sys/param.h> 57#include <sys/proc.h> 58#include <sys/device.h> 59#include <sys/conf.h> 60#include <sys/file.h> 61#include <sys/ioctl.h> 62#include <sys/tty.h> 63#include <sys/time.h> 64#include <sys/kernel.h> 65#include <sys/syslog.h> 66 67#include <machine/cpu.h> 68#include <machine/iomap.h> 69#include <machine/scu.h> 70#include <machine/mfp.h> 71 72#include <dev/ic/z8530reg.h> 73#include <atari/dev/zsvar.h> 74#include "zs.h" 75#if NZS > 1 76#error "This driver supports only 1 85C30!" 77#endif 78 79#if NZS > 0 80 81#define PCLK (8000000) /* PCLK pin input clock rate */ 82 83#define splzs spl5 84 85/* 86 * Software state per found chip. 87 */ 88struct zs_softc { 89 struct device zi_dev; /* base device */ 90 volatile struct zsdevice *zi_zs; /* chip registers */ 91 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 92}; 93 94/* 95 * Define the registers for a closed port 96 */ 97static u_char zs_init_regs[16] = { 98/* 0 */ 0, 99/* 1 */ 0, 100/* 2 */ 0x60, 101/* 3 */ 0, 102/* 4 */ 0, 103/* 5 */ 0, 104/* 6 */ 0, 105/* 7 */ 0, 106/* 8 */ 0, 107/* 9 */ ZSWR9_VECTOR_INCL_STAT, 108/* 10 */ ZSWR10_NRZ, 109/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 110/* 12 */ 0, 111/* 13 */ 0, 112/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 113/* 15 */ 0 114}; 115 116/* 117 * Define the machine dependant clock frequencies 118 * If BRgen feeds sender/receiver we always use a 119 * divisor 16, therefor the division by 16 can as 120 * well be done here. 121 */ 122static u_long zs_freqs_tt[] = { 123 /* 124 * Atari TT, RTxCB is generated by TT-MFP timer C, 125 * which is set to 307.2KHz during initialisation 126 * and never changed afterwards. 127 */ 128 PCLK/16, /* BRgen, PCLK, divisor 16 */ 129 229500, /* BRgen, RTxCA, divisor 16 */ 130 3672000, /* RTxCA, from PCLK4 */ 131 0, /* TRxCA, external */ 132 133 PCLK/16, /* BRgen, PCLK, divisor 16 */ 134 19200, /* BRgen, RTxCB, divisor 16 */ 135 307200, /* RTxCB, from TT-MFP TCO */ 136 2457600 /* TRxCB, from BCLK */ 137}; 138static u_long zs_freqs_falcon[] = { 139 /* 140 * Atari Falcon, XXX no specs available, this might be wrong 141 */ 142 PCLK/16, /* BRgen, PCLK, divisor 16 */ 143 229500, /* BRgen, RTxCA, divisor 16 */ 144 3672000, /* RTxCA, ??? */ 145 0, /* TRxCA, external */ 146 147 PCLK/16, /* BRgen, PCLK, divisor 16 */ 148 229500, /* BRgen, RTxCB, divisor 16 */ 149 3672000, /* RTxCB, ??? */ 150 2457600 /* TRxCB, ??? */ 151}; 152static u_long zs_freqs_generic[] = { 153 /* 154 * other machines, assume only PCLK is available 155 */ 156 PCLK/16, /* BRgen, PCLK, divisor 16 */ 157 0, /* BRgen, RTxCA, divisor 16 */ 158 0, /* RTxCA, unknown */ 159 0, /* TRxCA, unknown */ 160 161 PCLK/16, /* BRgen, PCLK, divisor 16 */ 162 0, /* BRgen, RTxCB, divisor 16 */ 163 0, /* RTxCB, unknown */ 164 0 /* TRxCB, unknown */ 165}; 166static u_long *zs_frequencies; 167 168/* Definition of the driver for autoconfig. */ 169static int zsmatch __P((struct device *, struct cfdata *, void *)); 170static void zsattach __P((struct device *, struct device *, void *)); 171struct cfdriver zscd = { 172 NULL, "zs", (cfmatch_t)zsmatch, zsattach, DV_TTY, 173 sizeof(struct zs_softc), NULL, 0 }; 174 175/* Interrupt handlers. */ 176int zshard __P((long)); 177static int zssoft __P((long)); 178static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 179static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 180static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 181 182static struct zs_chanstate *zslist; 183 184/* Routines called from other code. */ 185static void zsstart __P((struct tty *)); 186void zsstop __P((struct tty *, int)); 187static int zsparam __P((struct tty *, struct termios *)); 188static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 189 190/* Routines purely local to this driver. */ 191static void zs_reset __P((volatile struct zschan *, int, int)); 192static int zs_modem __P((struct zs_chanstate *, int, int)); 193static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 194 195static int zsshortcuts; /* number of "shortcut" software interrupts */ 196 197static int 198zsmatch(pdp, cfp, auxp) 199struct device *pdp; 200struct cfdata *cfp; 201void *auxp; 202{ 203 if(strcmp("zs", auxp) || cfp->cf_unit != 0) 204 return(0); 205 return(1); 206} 207 208/* 209 * Attach a found zs. 210 */ 211static void 212zsattach(parent, dev, aux) 213struct device *parent; 214struct device *dev; 215void *aux; 216{ 217 register struct zs_softc *zi; 218 register struct zs_chanstate *cs; 219 register volatile struct zsdevice *addr; 220 register struct tty *tp; 221 char tmp; 222 223 addr = (struct zsdevice *)AD_SCC; 224 zi = (struct zs_softc *)dev; 225 zi->zi_zs = addr; 226 cs = zi->zi_cs; 227 228 /* 229 * Get the command register into a known state. 230 */ 231 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 232 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 233 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 234 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 235 236 /* 237 * Do a hardware reset. 238 */ 239 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 240 delay(50000); /*enough ? */ 241 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 242 243 /* 244 * Initialize both channels 245 */ 246 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 247 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 248 249 if(machineid & ATARI_TT) { 250 /* 251 * ininitialise TT-MFP timer C: 307200Hz 252 * timer C and D share one control register: 253 * bits 0-2 control timer D 254 * bits 4-6 control timer C 255 */ 256 int cr = MFP2->mf_tcdcr & 7; 257 MFP2->mf_tcdcr = cr; /* stop timer C */ 258 MFP2->mf_tcdr = 1; /* counter 1 */ 259 cr |= T_Q004 << 4; /* divisor 4 */ 260 MFP2->mf_tcdcr = cr; /* start timer C */ 261 /* 262 * enable scc related interrupts 263 */ 264 SCU->sys_mask |= SCU_SCC; 265 266 zs_frequencies = zs_freqs_tt; 267 } else if (machineid & ATARI_FALCON) { 268 zs_frequencies = zs_freqs_falcon; 269 } else { 270 zs_frequencies = zs_freqs_generic; 271 } 272 273 /* link into interrupt list with order (A,B) (B=A+1) */ 274 cs[0].cs_next = &cs[1]; 275 cs[1].cs_next = zslist; 276 zslist = cs; 277 278 cs->cs_unit = 0; 279 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 280 cs++; 281 cs->cs_unit = 1; 282 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 283 284 printf(": serial2 on channel a and modem2 on channel b\n"); 285} 286 287/* 288 * Open a zs serial port. 289 */ 290int 291zsopen(dev, flags, mode, p) 292dev_t dev; 293int flags; 294int mode; 295struct proc *p; 296{ 297 register struct tty *tp; 298 register struct zs_chanstate *cs; 299 struct zs_softc *zi; 300 int unit = ZS_UNIT(dev); 301 int zs = unit >> 1; 302 int error, s; 303 304 if(zs >= zscd.cd_ndevs || (zi = zscd.cd_devs[zs]) == NULL) 305 return (ENXIO); 306 cs = &zi->zi_cs[unit & 1]; 307 tp = cs->cs_ttyp; 308 if(tp == NULL) { 309 cs->cs_ttyp = tp = ttymalloc(); 310 tp->t_dev = dev; 311 tp->t_oproc = zsstart; 312 tp->t_param = zsparam; 313 } 314 315 s = spltty(); 316 if((tp->t_state & TS_ISOPEN) == 0) { 317 ttychars(tp); 318 if(tp->t_ispeed == 0) { 319 tp->t_iflag = TTYDEF_IFLAG; 320 tp->t_oflag = TTYDEF_OFLAG; 321 tp->t_cflag = TTYDEF_CFLAG; 322 tp->t_lflag = TTYDEF_LFLAG; 323 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 324 } 325 (void)zsparam(tp, &tp->t_termios); 326 ttsetwater(tp); 327 } 328 else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 329 splx(s); 330 return (EBUSY); 331 } 332 error = 0; 333 for(;;) { 334 /* loop, turning on the device, until carrier present */ 335 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 336 if(cs->cs_softcar) 337 tp->t_state |= TS_CARR_ON; 338 if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL || 339 tp->t_state & TS_CARR_ON) 340 break; 341 tp->t_state |= TS_WOPEN; 342 if(error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH, 343 ttopen, 0)) { 344 if(!(tp->t_state & TS_ISOPEN)) { 345 zs_modem(cs, 0, DMSET); 346 tp->t_state &= ~TS_WOPEN; 347 ttwakeup(tp); 348 } 349 splx(s); 350 return error; 351 } 352 } 353 splx(s); 354 if(error == 0) 355 error = linesw[tp->t_line].l_open(dev, tp); 356 if(error) 357 zs_modem(cs, 0, DMSET); 358 return(error); 359} 360 361/* 362 * Close a zs serial port. 363 */ 364int 365zsclose(dev, flags, mode, p) 366dev_t dev; 367int flags; 368int mode; 369struct proc *p; 370{ 371 register struct zs_chanstate *cs; 372 register struct tty *tp; 373 struct zs_softc *zi; 374 int unit = ZS_UNIT(dev); 375 int s; 376 377 zi = zscd.cd_devs[unit >> 1]; 378 cs = &zi->zi_cs[unit & 1]; 379 tp = cs->cs_ttyp; 380 linesw[tp->t_line].l_close(tp, flags); 381 if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN || 382 (tp->t_state & TS_ISOPEN) == 0) { 383 zs_modem(cs, 0, DMSET); 384 /* hold low for 1 second */ 385 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 386 } 387 if(cs->cs_creg[5] & ZSWR5_BREAK) { 388 s = splzs(); 389 cs->cs_preg[5] &= ~ZSWR5_BREAK; 390 cs->cs_creg[5] &= ~ZSWR5_BREAK; 391 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 392 splx(s); 393 } 394 ttyclose(tp); 395 396 /* 397 * Drop all lines and cancel interrupts 398 */ 399 zs_loadchannelregs(&zi->zi_zs->zs_chan[unit & 1], zs_init_regs); 400 return (0); 401} 402 403/* 404 * Read/write zs serial port. 405 */ 406int 407zsread(dev, uio, flags) 408dev_t dev; 409struct uio *uio; 410int flags; 411{ 412 register struct zs_chanstate *cs; 413 register struct zs_softc *zi; 414 register struct tty *tp; 415 int unit; 416 417 unit = ZS_UNIT(dev); 418 zi = zscd.cd_devs[unit >> 1]; 419 cs = &zi->zi_cs[unit & 1]; 420 tp = cs->cs_ttyp; 421 422 return(linesw[tp->t_line].l_read(tp, uio, flags)); 423} 424 425int 426zswrite(dev, uio, flags) 427dev_t dev; 428struct uio *uio; 429int flags; 430{ 431 register struct zs_chanstate *cs; 432 register struct zs_softc *zi; 433 register struct tty *tp; 434 int unit; 435 436 unit = ZS_UNIT(dev); 437 zi = zscd.cd_devs[unit >> 1]; 438 cs = &zi->zi_cs[unit & 1]; 439 tp = cs->cs_ttyp; 440 441 return(linesw[tp->t_line].l_write(tp, uio, flags)); 442} 443 444struct tty * 445zstty(dev) 446dev_t dev; 447{ 448 register struct zs_chanstate *cs; 449 register struct zs_softc *zi; 450 int unit; 451 452 unit = ZS_UNIT(dev); 453 zi = zscd.cd_devs[unit >> 1]; 454 cs = &zi->zi_cs[unit & 1]; 455 return(cs->cs_ttyp); 456} 457 458/* 459 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 460 * channels are kept in (A,B) pairs. 461 * 462 * Do just a little, then get out; set a software interrupt if more 463 * work is needed. 464 * 465 * We deliberately ignore the vectoring Zilog gives us, and match up 466 * only the number of `reset interrupt under service' operations, not 467 * the order. 468 */ 469int 470zshard(sr) 471long sr; 472{ 473 register struct zs_chanstate *a; 474#define b (a + 1) 475 register volatile struct zschan *zc; 476 register int rr3, intflags = 0, v, i; 477 478 for(a = zslist; a != NULL; a = b->cs_next) { 479 rr3 = ZS_READ(a->cs_zc, 3); 480 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 481 intflags |= 2; 482 zc = a->cs_zc; 483 i = a->cs_rbput; 484 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 485 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 486 intflags |= 1; 487 } 488 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 489 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 490 intflags |= 1; 491 } 492 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 493 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 494 intflags |= 1; 495 } 496 a->cs_rbput = i; 497 } 498 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 499 intflags |= 2; 500 zc = b->cs_zc; 501 i = b->cs_rbput; 502 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 503 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 504 intflags |= 1; 505 } 506 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 507 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 508 intflags |= 1; 509 } 510 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 511 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 512 intflags |= 1; 513 } 514 b->cs_rbput = i; 515 } 516 } 517#undef b 518 519 if(intflags & 1) { 520 if(BASEPRI(sr)) { 521 spl1(); 522 zsshortcuts++; 523 return(zssoft(sr)); 524 } 525 else add_sicallback(zssoft, 0, 0); 526 } 527 return(intflags & 2); 528} 529 530static int 531zsrint(cs, zc) 532register struct zs_chanstate *cs; 533register volatile struct zschan *zc; 534{ 535 register int c = zc->zc_data; 536 537 /* compose receive character and status */ 538 c <<= 8; 539 c |= ZS_READ(zc, 1); 540 541 /* clear receive error & interrupt condition */ 542 zc->zc_csr = ZSWR0_RESET_ERRORS; 543 zc->zc_csr = ZSWR0_CLR_INTR; 544 545 return(ZRING_MAKE(ZRING_RINT, c)); 546} 547 548static int 549zsxint(cs, zc) 550register struct zs_chanstate *cs; 551register volatile struct zschan *zc; 552{ 553 register int i = cs->cs_tbc; 554 555 if(i == 0) { 556 zc->zc_csr = ZSWR0_RESET_TXINT; 557 zc->zc_csr = ZSWR0_CLR_INTR; 558 return(ZRING_MAKE(ZRING_XINT, 0)); 559 } 560 cs->cs_tbc = i - 1; 561 zc->zc_data = *cs->cs_tba++; 562 zc->zc_csr = ZSWR0_CLR_INTR; 563 return (0); 564} 565 566static int 567zssint(cs, zc) 568register struct zs_chanstate *cs; 569register volatile struct zschan *zc; 570{ 571 register int rr0; 572 573 rr0 = zc->zc_csr; 574 zc->zc_csr = ZSWR0_RESET_STATUS; 575 zc->zc_csr = ZSWR0_CLR_INTR; 576 /* 577 * The chip's hardware flow control is, as noted in zsreg.h, 578 * busted---if the DCD line goes low the chip shuts off the 579 * receiver (!). If we want hardware CTS flow control but do 580 * not have it, and carrier is now on, turn HFC on; if we have 581 * HFC now but carrier has gone low, turn it off. 582 */ 583 if(rr0 & ZSRR0_DCD) { 584 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 585 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 586 cs->cs_creg[3] |= ZSWR3_HFC; 587 ZS_WRITE(zc, 3, cs->cs_creg[3]); 588 } 589 } 590 else { 591 if (cs->cs_creg[3] & ZSWR3_HFC) { 592 cs->cs_creg[3] &= ~ZSWR3_HFC; 593 ZS_WRITE(zc, 3, cs->cs_creg[3]); 594 } 595 } 596 return(ZRING_MAKE(ZRING_SINT, rr0)); 597} 598 599/* 600 * Print out a ring or fifo overrun error message. 601 */ 602static void 603zsoverrun(unit, ptime, what) 604int unit; 605long *ptime; 606char *what; 607{ 608 609 if(*ptime != time.tv_sec) { 610 *ptime = time.tv_sec; 611 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 612 (unit & 1) + 'a', what); 613 } 614} 615 616/* 617 * ZS software interrupt. Scan all channels for deferred interrupts. 618 */ 619int 620zssoft(sr) 621long sr; 622{ 623 register struct zs_chanstate *cs; 624 register volatile struct zschan *zc; 625 register struct linesw *line; 626 register struct tty *tp; 627 register int get, n, c, cc, unit, s; 628 int retval = 0; 629 630 s = spltty(); 631 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 632 get = cs->cs_rbget; 633again: 634 n = cs->cs_rbput; /* atomic */ 635 if(get == n) /* nothing more on this line */ 636 continue; 637 retval = 1; 638 unit = cs->cs_unit; /* set up to handle interrupts */ 639 zc = cs->cs_zc; 640 tp = cs->cs_ttyp; 641 line = &linesw[tp->t_line]; 642 /* 643 * Compute the number of interrupts in the receive ring. 644 * If the count is overlarge, we lost some events, and 645 * must advance to the first valid one. It may get 646 * overwritten if more data are arriving, but this is 647 * too expensive to check and gains nothing (we already 648 * lost out; all we can do at this point is trade one 649 * kind of loss for another). 650 */ 651 n -= get; 652 if(n > ZLRB_RING_SIZE) { 653 zsoverrun(unit, &cs->cs_rotime, "ring"); 654 get += n - ZLRB_RING_SIZE; 655 n = ZLRB_RING_SIZE; 656 } 657 while(--n >= 0) { 658 /* race to keep ahead of incoming interrupts */ 659 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 660 switch (ZRING_TYPE(c)) { 661 662 case ZRING_RINT: 663 c = ZRING_VALUE(c); 664 if(c & ZSRR1_DO) 665 zsoverrun(unit, &cs->cs_fotime, "fifo"); 666 cc = c >> 8; 667 if(c & ZSRR1_FE) 668 cc |= TTY_FE; 669 if(c & ZSRR1_PE) 670 cc |= TTY_PE; 671 line->l_rint(cc, tp); 672 break; 673 674 case ZRING_XINT: 675 /* 676 * Transmit done: change registers and resume, 677 * or clear BUSY. 678 */ 679 if(cs->cs_heldchange) { 680 int sps; 681 682 sps = splzs(); 683 c = zc->zc_csr; 684 if((c & ZSRR0_DCD) == 0) 685 cs->cs_preg[3] &= ~ZSWR3_HFC; 686 bcopy((caddr_t)cs->cs_preg, 687 (caddr_t)cs->cs_creg, 16); 688 zs_loadchannelregs(zc, cs->cs_creg); 689 splx(sps); 690 cs->cs_heldchange = 0; 691 if(cs->cs_heldtbc 692 && (tp->t_state & TS_TTSTOP) == 0) { 693 cs->cs_tbc = cs->cs_heldtbc - 1; 694 zc->zc_data = *cs->cs_tba++; 695 goto again; 696 } 697 } 698 tp->t_state &= ~TS_BUSY; 699 if(tp->t_state & TS_FLUSH) 700 tp->t_state &= ~TS_FLUSH; 701 else ndflush(&tp->t_outq,cs->cs_tba 702 - (caddr_t)tp->t_outq.c_cf); 703 line->l_start(tp); 704 break; 705 706 case ZRING_SINT: 707 /* 708 * Status line change. HFC bit is run in 709 * hardware interrupt, to avoid locking 710 * at splzs here. 711 */ 712 c = ZRING_VALUE(c); 713 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 714 cc = (c & ZSRR0_DCD) != 0; 715 if(line->l_modem(tp, cc) == 0) 716 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 717 cc ? DMBIS : DMBIC); 718 } 719 cs->cs_rr0 = c; 720 break; 721 722 default: 723 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 724 unit >> 1, (unit & 1) + 'a', c); 725 break; 726 } 727 } 728 cs->cs_rbget = get; 729 goto again; 730 } 731 splx(s); 732 return (retval); 733} 734 735int 736zsioctl(dev, cmd, data, flag, p) 737dev_t dev; 738u_long cmd; 739caddr_t data; 740int flag; 741struct proc *p; 742{ 743 int unit = ZS_UNIT(dev); 744 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 745 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 746 register int error, s; 747 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 748 749 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 750 if(error >= 0) 751 return(error); 752 error = ttioctl(tp, cmd, data, flag, p); 753 if(error >= 0) 754 return (error); 755 756 switch (cmd) { 757 case TIOCSBRK: 758 s = splzs(); 759 cs->cs_preg[5] |= ZSWR5_BREAK; 760 cs->cs_creg[5] |= ZSWR5_BREAK; 761 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 762 splx(s); 763 break; 764 case TIOCCBRK: 765 s = splzs(); 766 cs->cs_preg[5] &= ~ZSWR5_BREAK; 767 cs->cs_creg[5] &= ~ZSWR5_BREAK; 768 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 769 splx(s); 770 break; 771 case TIOCGFLAGS: { 772 int bits = 0; 773 774 if(cs->cs_softcar) 775 bits |= TIOCFLAG_SOFTCAR; 776 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 777 bits |= TIOCFLAG_CLOCAL; 778 if(cs->cs_creg[3] & ZSWR3_HFC) 779 bits |= TIOCFLAG_CRTSCTS; 780 *(int *)data = bits; 781 break; 782 } 783 case TIOCSFLAGS: { 784 int userbits, driverbits = 0; 785 786 error = suser(p->p_ucred, &p->p_acflag); 787 if(error != 0) 788 return (EPERM); 789 790 userbits = *(int *)data; 791 792 /* 793 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 794 # defaulting to software flow control. 795 */ 796 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 797 return(EINVAL); 798 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 799 return(ENXIO); 800 801 s = splzs(); 802 if((userbits & TIOCFLAG_SOFTCAR)) { 803 cs->cs_softcar = 1; /* turn on softcar */ 804 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 805 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 806 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 807 } 808 else if(userbits & TIOCFLAG_CLOCAL) { 809 cs->cs_softcar = 0; /* turn off softcar */ 810 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 811 cs->cs_creg[15] |= ZSWR15_DCD_IE; 812 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 813 tp->t_termios.c_cflag |= CLOCAL; 814 } 815 if(userbits & TIOCFLAG_CRTSCTS) { 816 cs->cs_preg[15] |= ZSWR15_CTS_IE; 817 cs->cs_creg[15] |= ZSWR15_CTS_IE; 818 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 819 cs->cs_preg[3] |= ZSWR3_HFC; 820 cs->cs_creg[3] |= ZSWR3_HFC; 821 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 822 tp->t_termios.c_cflag |= CRTSCTS; 823 } 824 else { 825 /* no mdmbuf, so we must want software flow control */ 826 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 827 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 828 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 829 cs->cs_preg[3] &= ~ZSWR3_HFC; 830 cs->cs_creg[3] &= ~ZSWR3_HFC; 831 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 832 tp->t_termios.c_cflag &= ~CRTSCTS; 833 } 834 splx(s); 835 break; 836 } 837 case TIOCSDTR: 838 zs_modem(cs, ZSWR5_DTR, DMBIS); 839 break; 840 case TIOCCDTR: 841 zs_modem(cs, ZSWR5_DTR, DMBIC); 842 break; 843 case TIOCMGET: 844 zs_modem(cs, 0, DMGET); 845 break; 846 case TIOCMSET: 847 case TIOCMBIS: 848 case TIOCMBIC: 849 default: 850 return (ENOTTY); 851 } 852 return (0); 853} 854 855/* 856 * Start or restart transmission. 857 */ 858static void 859zsstart(tp) 860register struct tty *tp; 861{ 862 register struct zs_chanstate *cs; 863 register int s, nch; 864 int unit = ZS_UNIT(tp->t_dev); 865 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 866 867 cs = &zi->zi_cs[unit & 1]; 868 s = spltty(); 869 870 /* 871 * If currently active or delaying, no need to do anything. 872 */ 873 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 874 goto out; 875 876 /* 877 * If there are sleepers, and output has drained below low 878 * water mark, awaken. 879 */ 880 if(tp->t_outq.c_cc <= tp->t_lowat) { 881 if(tp->t_state & TS_ASLEEP) { 882 tp->t_state &= ~TS_ASLEEP; 883 wakeup((caddr_t)&tp->t_outq); 884 } 885 selwakeup(&tp->t_wsel); 886 } 887 888 nch = ndqb(&tp->t_outq, 0); /* XXX */ 889 if(nch) { 890 register char *p = tp->t_outq.c_cf; 891 892 /* mark busy, enable tx done interrupts, & send first byte */ 893 tp->t_state |= TS_BUSY; 894 (void) splzs(); 895 cs->cs_preg[1] |= ZSWR1_TIE; 896 cs->cs_creg[1] |= ZSWR1_TIE; 897 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 898 cs->cs_zc->zc_data = *p; 899 cs->cs_tba = p + 1; 900 cs->cs_tbc = nch - 1; 901 } else { 902 /* 903 * Nothing to send, turn off transmit done interrupts. 904 * This is useful if something is doing polled output. 905 */ 906 (void) splzs(); 907 cs->cs_preg[1] &= ~ZSWR1_TIE; 908 cs->cs_creg[1] &= ~ZSWR1_TIE; 909 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 910 } 911out: 912 splx(s); 913} 914 915/* 916 * Stop output, e.g., for ^S or output flush. 917 */ 918void 919zsstop(tp, flag) 920register struct tty *tp; 921 int flag; 922{ 923 register struct zs_chanstate *cs; 924 register int s, unit = ZS_UNIT(tp->t_dev); 925 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 926 927 cs = &zi->zi_cs[unit & 1]; 928 s = splzs(); 929 if(tp->t_state & TS_BUSY) { 930 /* 931 * Device is transmitting; must stop it. 932 */ 933 cs->cs_tbc = 0; 934 if ((tp->t_state & TS_TTSTOP) == 0) 935 tp->t_state |= TS_FLUSH; 936 } 937 splx(s); 938} 939 940/* 941 * Set ZS tty parameters from termios. 942 * 943 * This routine makes use of the fact that only registers 944 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 945 */ 946static int 947zsparam(tp, t) 948register struct tty *tp; 949register struct termios *t; 950{ 951 int unit = ZS_UNIT(tp->t_dev); 952 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 953 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 954 int cdiv, clkm, brgm, tcon; 955 register int tmp, tmp5, cflag, s; 956 957 tmp = t->c_ospeed; 958 tmp5 = t->c_ispeed; 959 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 960 return(EINVAL); 961 if(tmp == 0) { 962 /* stty 0 => drop DTR and RTS */ 963 zs_modem(cs, 0, DMSET); 964 return(0); 965 } 966 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 967 if (tmp < 0) 968 return(EINVAL); 969 tp->t_ispeed = tp->t_ospeed = tmp; 970 971 cflag = tp->t_cflag = t->c_cflag; 972 if (cflag & CSTOPB) 973 cdiv |= ZSWR4_TWOSB; 974 else 975 cdiv |= ZSWR4_ONESB; 976 if (!(cflag & PARODD)) 977 cdiv |= ZSWR4_EVENP; 978 if (cflag & PARENB) 979 cdiv |= ZSWR4_PARENB; 980 981 switch(cflag & CSIZE) { 982 case CS5: 983 tmp = ZSWR3_RX_5; 984 tmp5 = ZSWR5_TX_5; 985 break; 986 case CS6: 987 tmp = ZSWR3_RX_6; 988 tmp5 = ZSWR5_TX_6; 989 break; 990 case CS7: 991 tmp = ZSWR3_RX_7; 992 tmp5 = ZSWR5_TX_7; 993 break; 994 case CS8: 995 default: 996 tmp = ZSWR3_RX_8; 997 tmp5 = ZSWR5_TX_8; 998 break; 999 } 1000 tmp |= ZSWR3_RX_ENABLE; 1001 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1002 1003 /* 1004 * Block interrupts so that state will not 1005 * be altered until we are done setting it up. 1006 */ 1007 s = splzs(); 1008 cs->cs_preg[4] = cdiv; 1009 cs->cs_preg[11] = clkm; 1010 cs->cs_preg[12] = tcon; 1011 cs->cs_preg[13] = tcon >> 8; 1012 cs->cs_preg[14] = brgm; 1013 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1014 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1015 cs->cs_preg[10] = ZSWR10_NRZ; 1016 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1017 1018 /* 1019 * Output hardware flow control on the chip is horrendous: if 1020 * carrier detect drops, the receiver is disabled. Hence we 1021 * can only do this when the carrier is on. 1022 */ 1023 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1024 tmp |= ZSWR3_HFC; 1025 cs->cs_preg[3] = tmp; 1026 cs->cs_preg[5] = tmp5; 1027 1028 /* 1029 * If nothing is being transmitted, set up new current values, 1030 * else mark them as pending. 1031 */ 1032 if(cs->cs_heldchange == 0) { 1033 if (cs->cs_ttyp->t_state & TS_BUSY) { 1034 cs->cs_heldtbc = cs->cs_tbc; 1035 cs->cs_tbc = 0; 1036 cs->cs_heldchange = 1; 1037 } else { 1038 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1039 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1040 } 1041 } 1042 splx(s); 1043 return (0); 1044} 1045 1046/* 1047 * search for the best matching baudrate 1048 */ 1049static int 1050zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1051int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1052{ 1053 int bestdiff, bestbps, source; 1054 1055 unit = (unit & 1) << 2; 1056 for (source = 0; source < 4; ++source) { 1057 long freq = zs_frequencies[unit + source]; 1058 int diff, bps, div, clkm, brgm, tcon; 1059 switch (source) { 1060 case 0: /* BRgen, PCLK */ 1061 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1062 break; 1063 case 1: /* BRgen, RTxC */ 1064 brgm = ZSWR14_BAUD_ENA; 1065 break; 1066 case 2: /* RTxC */ 1067 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1068 break; 1069 case 3: /* TRxC */ 1070 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1071 break; 1072 } 1073 switch (source) { 1074 case 0: 1075 case 1: 1076 div = ZSWR4_CLK_X16; 1077 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1078 tcon = BPS_TO_TCONST(freq, wanted); 1079 if (tcon < 0) 1080 tcon = 0; 1081 bps = TCONST_TO_BPS(freq, tcon); 1082 break; 1083 case 2: 1084 case 3: 1085 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1086 int b2 = freq / 32, d2 = abs(b2 - wanted); 1087 int b3 = freq / 64, d3 = abs(b3 - wanted); 1088 1089 if (d1 < d2 && d1 < d3) { 1090 div = ZSWR4_CLK_X16; 1091 bps = b1; 1092 } else if (d2 < d3 && d2 < d1) { 1093 div = ZSWR4_CLK_X32; 1094 bps = b2; 1095 } else { 1096 div = ZSWR4_CLK_X64; 1097 bps = b3; 1098 } 1099 brgm = tcon = 0; 1100 break; 1101 } 1102 } 1103 diff = abs(bps - wanted); 1104 if (!source || diff < bestdiff) { 1105 *divisor = div; 1106 *clockmode = clkm; 1107 *brgenmode = brgm; 1108 *timeconst = tcon; 1109 bestbps = bps; 1110 bestdiff = diff; 1111 if (diff == 0) 1112 break; 1113 } 1114 } 1115 /* Allow deviations upto 5% */ 1116 if (20 * bestdiff > wanted) 1117 return -1; 1118 return bestbps; 1119} 1120 1121/* 1122 * Raise or lower modem control (DTR/RTS) signals. If a character is 1123 * in transmission, the change is deferred. 1124 */ 1125static int 1126zs_modem(cs, bits, how) 1127struct zs_chanstate *cs; 1128int bits, how; 1129{ 1130 int s, mbits; 1131 1132 bits &= ZSWR5_DTR | ZSWR5_RTS; 1133 1134 s = splzs(); 1135 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1136 1137 switch(how) { 1138 case DMSET: 1139 mbits = bits; 1140 break; 1141 case DMBIS: 1142 mbits |= bits; 1143 break; 1144 case DMBIC: 1145 mbits &= ~bits; 1146 break; 1147 case DMGET: 1148 splx(s); 1149 return(mbits); 1150 } 1151 1152 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1153 if(cs->cs_heldchange == 0) { 1154 if(cs->cs_ttyp->t_state & TS_BUSY) { 1155 cs->cs_heldtbc = cs->cs_tbc; 1156 cs->cs_tbc = 0; 1157 cs->cs_heldchange = 1; 1158 } 1159 else { 1160 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1161 } 1162 } 1163 splx(s); 1164 return(0); 1165} 1166 1167/* 1168 * Write the given register set to the given zs channel in the proper order. 1169 * The channel must not be transmitting at the time. The receiver will 1170 * be disabled for the time it takes to write all the registers. 1171 */ 1172static void 1173zs_loadchannelregs(zc, reg) 1174volatile struct zschan *zc; 1175u_char *reg; 1176{ 1177 int i; 1178 1179 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1180 i = zc->zc_data; /* drain fifo */ 1181 i = zc->zc_data; 1182 i = zc->zc_data; 1183 ZS_WRITE(zc, 4, reg[4]); 1184 ZS_WRITE(zc, 10, reg[10]); 1185 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1186 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1187 ZS_WRITE(zc, 1, reg[1]); 1188 ZS_WRITE(zc, 9, reg[9]); 1189 ZS_WRITE(zc, 11, reg[11]); 1190 ZS_WRITE(zc, 12, reg[12]); 1191 ZS_WRITE(zc, 13, reg[13]); 1192 ZS_WRITE(zc, 14, reg[14]); 1193 ZS_WRITE(zc, 15, reg[15]); 1194 ZS_WRITE(zc, 3, reg[3]); 1195 ZS_WRITE(zc, 5, reg[5]); 1196} 1197#endif /* NZS > 1 */ 1198