zs.c revision 1.45
1/* $NetBSD: zs.c,v 1.45 2005/12/11 12:16:54 christos Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)zs.c 8.1 (Berkeley) 7/19/93 42 */ 43 44/*- 45 * Copyright (c) 1995 The NetBSD Foundation, Inc. (Atari modifications) 46 * All rights reserved. 47 * 48 * This code is derived from software contributed to The NetBSD Foundation 49 * by Leo Weppelman. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of The NetBSD Foundation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76/* 77 * Zilog Z8530 (ZSCC) driver. 78 * 79 * Runs two tty ports (modem2 and serial2) on zs0. 80 * 81 * This driver knows far too much about chip to usage mappings. 82 */ 83 84#include <sys/cdefs.h> 85__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.45 2005/12/11 12:16:54 christos Exp $"); 86 87#include <sys/param.h> 88#include <sys/systm.h> 89#include <sys/proc.h> 90#include <sys/device.h> 91#include <sys/conf.h> 92#include <sys/file.h> 93#include <sys/ioctl.h> 94#include <sys/malloc.h> 95#include <sys/tty.h> 96#include <sys/time.h> 97#include <sys/kernel.h> 98#include <sys/syslog.h> 99 100#include <machine/cpu.h> 101#include <machine/iomap.h> 102#include <machine/scu.h> 103#include <machine/mfp.h> 104#include <atari/dev/ym2149reg.h> 105 106#include <dev/ic/z8530reg.h> 107#include <atari/dev/zsvar.h> 108#include "zs.h" 109#if NZS > 1 110#error "This driver supports only 1 85C30!" 111#endif 112 113#if NZS > 0 114 115#define PCLK (8053976) /* PCLK pin input clock rate */ 116#define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 117 118#define splzs spl5 119 120/* 121 * Software state per found chip. 122 */ 123struct zs_softc { 124 struct device zi_dev; /* base device */ 125 volatile struct zsdevice *zi_zs; /* chip registers */ 126 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 127}; 128 129static u_char cb_scheduled = 0; /* Already asked for callback? */ 130/* 131 * Define the registers for a closed port 132 */ 133static u_char zs_init_regs[16] = { 134/* 0 */ 0, 135/* 1 */ 0, 136/* 2 */ 0x60, 137/* 3 */ 0, 138/* 4 */ 0, 139/* 5 */ 0, 140/* 6 */ 0, 141/* 7 */ 0, 142/* 8 */ 0, 143/* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 144/* 10 */ ZSWR10_NRZ, 145/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 146/* 12 */ 0, 147/* 13 */ 0, 148/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 149/* 15 */ 0 150}; 151 152/* 153 * Define the machine dependant clock frequencies 154 * If BRgen feeds sender/receiver we always use a 155 * divisor 16, therefor the division by 16 can as 156 * well be done here. 157 */ 158static u_long zs_freqs_tt[] = { 159 /* 160 * Atari TT, RTxCB is generated by TT-MFP timer C, 161 * which is set to 307.2KHz during initialisation 162 * and never changed afterwards. 163 */ 164 PCLK/16, /* BRgen, PCLK, divisor 16 */ 165 229500, /* BRgen, RTxCA, divisor 16 */ 166 3672000, /* RTxCA, from PCLK4 */ 167 0, /* TRxCA, external */ 168 169 PCLK/16, /* BRgen, PCLK, divisor 16 */ 170 19200, /* BRgen, RTxCB, divisor 16 */ 171 307200, /* RTxCB, from TT-MFP TCO */ 172 2457600 /* TRxCB, from BCLK */ 173}; 174 175static u_long zs_freqs_falcon[] = { 176 /* 177 * Atari Falcon, XXX no specs available, this might be wrong 178 */ 179 PCLK/16, /* BRgen, PCLK, divisor 16 */ 180 229500, /* BRgen, RTxCA, divisor 16 */ 181 3672000, /* RTxCA, ??? */ 182 0, /* TRxCA, external */ 183 184 PCLK/16, /* BRgen, PCLK, divisor 16 */ 185 229500, /* BRgen, RTxCB, divisor 16 */ 186 3672000, /* RTxCB, ??? */ 187 2457600 /* TRxCB, ??? */ 188}; 189 190static u_long zs_freqs_hades[] = { 191 /* 192 * XXX: Channel-A unchecked!!!!! 193 */ 194 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 195 229500, /* BRgen, RTxCA, divisor 16 */ 196 3672000, /* RTxCA, from PCLK4 */ 197 0, /* TRxCA, external */ 198 199 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 200 235550, /* BRgen, RTxCB, divisor 16 */ 201 3768800, /* RTxCB, 3.7688MHz */ 202 3768800 /* TRxCB, 3.7688MHz */ 203}; 204 205static u_long zs_freqs_generic[] = { 206 /* 207 * other machines, assume only PCLK is available 208 */ 209 PCLK/16, /* BRgen, PCLK, divisor 16 */ 210 0, /* BRgen, RTxCA, divisor 16 */ 211 0, /* RTxCA, unknown */ 212 0, /* TRxCA, unknown */ 213 214 PCLK/16, /* BRgen, PCLK, divisor 16 */ 215 0, /* BRgen, RTxCB, divisor 16 */ 216 0, /* RTxCB, unknown */ 217 0 /* TRxCB, unknown */ 218}; 219static u_long *zs_frequencies; 220 221/* Definition of the driver for autoconfig. */ 222static int zsmatch __P((struct device *, struct cfdata *, void *)); 223static void zsattach __P((struct device *, struct device *, void *)); 224 225CFATTACH_DECL(zs, sizeof(struct zs_softc), 226 zsmatch, zsattach, NULL, NULL); 227 228extern struct cfdriver zs_cd; 229 230/* {b,c}devsw[] function prototypes */ 231dev_type_open(zsopen); 232dev_type_close(zsclose); 233dev_type_read(zsread); 234dev_type_write(zswrite); 235dev_type_ioctl(zsioctl); 236dev_type_stop(zsstop); 237dev_type_tty(zstty); 238dev_type_poll(zspoll); 239 240const struct cdevsw zs_cdevsw = { 241 zsopen, zsclose, zsread, zswrite, zsioctl, 242 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 243}; 244 245/* Interrupt handlers. */ 246int zshard __P((long)); 247static int zssoft __P((long)); 248static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 249static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 250static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 251 252static struct zs_chanstate *zslist; 253 254/* Routines called from other code. */ 255static void zsstart __P((struct tty *)); 256 257/* Routines purely local to this driver. */ 258static void zsoverrun __P((int, long *, const char *)); 259static int zsparam __P((struct tty *, struct termios *)); 260static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 261static int zs_modem __P((struct zs_chanstate *, int, int)); 262static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 263static void zs_shutdown __P((struct zs_chanstate *)); 264 265static int zsshortcuts; /* number of "shortcut" software interrupts */ 266 267static int 268zsmatch(pdp, cfp, auxp) 269struct device *pdp; 270struct cfdata *cfp; 271void *auxp; 272{ 273 static int zs_matched = 0; 274 275 if(strcmp("zs", auxp) || zs_matched) 276 return(0); 277 zs_matched = 1; 278 return(1); 279} 280 281/* 282 * Attach a found zs. 283 */ 284static void 285zsattach(parent, dev, aux) 286struct device *parent; 287struct device *dev; 288void *aux; 289{ 290 register struct zs_softc *zi; 291 register struct zs_chanstate *cs; 292 register volatile struct zsdevice *addr; 293 char tmp; 294 295 addr = (struct zsdevice *)AD_SCC; 296 zi = (struct zs_softc *)dev; 297 zi->zi_zs = addr; 298 cs = zi->zi_cs; 299 300 /* 301 * Get the command register into a known state. 302 */ 303 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 304 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 305 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 306 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 307 308 /* 309 * Do a hardware reset. 310 */ 311 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 312 delay(50000); /*enough ? */ 313 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 314 315 /* 316 * Initialize both channels 317 */ 318 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 319 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 320 321 if(machineid & ATARI_TT) { 322 /* 323 * ininitialise TT-MFP timer C: 307200Hz 324 * timer C and D share one control register: 325 * bits 0-2 control timer D 326 * bits 4-6 control timer C 327 */ 328 int cr = MFP2->mf_tcdcr & 7; 329 MFP2->mf_tcdcr = cr; /* stop timer C */ 330 MFP2->mf_tcdr = 1; /* counter 1 */ 331 cr |= T_Q004 << 4; /* divisor 4 */ 332 MFP2->mf_tcdcr = cr; /* start timer C */ 333 /* 334 * enable scc related interrupts 335 */ 336 SCU->vme_mask |= SCU_SCC; 337 338 zs_frequencies = zs_freqs_tt; 339 } else if (machineid & ATARI_FALCON) { 340 zs_frequencies = zs_freqs_falcon; 341 } else if (machineid & ATARI_HADES) { 342 zs_frequencies = zs_freqs_hades; 343 } else { 344 zs_frequencies = zs_freqs_generic; 345 } 346 347 /* link into interrupt list with order (A,B) (B=A+1) */ 348 cs[0].cs_next = &cs[1]; 349 cs[1].cs_next = zslist; 350 zslist = cs; 351 352 cs->cs_unit = 0; 353 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 354 cs++; 355 cs->cs_unit = 1; 356 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 357 358 printf(": serial2 on channel a and modem2 on channel b\n"); 359} 360 361/* 362 * Open a zs serial port. 363 */ 364int 365zsopen(dev, flags, mode, l) 366dev_t dev; 367int flags; 368int mode; 369struct lwp *l; 370{ 371 register struct tty *tp; 372 register struct zs_chanstate *cs; 373 struct zs_softc *zi; 374 int unit = ZS_UNIT(dev); 375 int zs = unit >> 1; 376 int error, s; 377 378 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 379 return (ENXIO); 380 cs = &zi->zi_cs[unit & 1]; 381 382 /* 383 * When port A (ser02) is selected on the TT, make sure 384 * the port is enabled. 385 */ 386 if((machineid & ATARI_TT) && !(unit & 1)) 387 ym2149_ser2(1); 388 389 if (cs->cs_rbuf == NULL) { 390 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 391 M_WAITOK); 392 } 393 394 tp = cs->cs_ttyp; 395 if(tp == NULL) { 396 cs->cs_ttyp = tp = ttymalloc(); 397 tty_attach(tp); 398 tp->t_dev = dev; 399 tp->t_oproc = zsstart; 400 tp->t_param = zsparam; 401 } 402 403 if ((tp->t_state & TS_ISOPEN) && 404 (tp->t_state & TS_XCLUDE) && 405 suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) != 0) 406 return (EBUSY); 407 408 s = spltty(); 409 410 /* 411 * Do the following iff this is a first open. 412 */ 413 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 414 if(tp->t_ispeed == 0) { 415 tp->t_iflag = TTYDEF_IFLAG; 416 tp->t_oflag = TTYDEF_OFLAG; 417 tp->t_cflag = TTYDEF_CFLAG; 418 tp->t_lflag = TTYDEF_LFLAG; 419 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 420 } 421 ttychars(tp); 422 ttsetwater(tp); 423 424 (void)zsparam(tp, &tp->t_termios); 425 426 /* 427 * Turn on DTR. We must always do this, even if carrier is not 428 * present, because otherwise we'd have to use TIOCSDTR 429 * immediately after setting CLOCAL, which applications do not 430 * expect. We always assert DTR while the device is open 431 * unless explicitly requested to deassert it. 432 */ 433 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 434 /* May never get a status intr. if DCD already on. -gwr */ 435 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 436 tp->t_state |= TS_CARR_ON; 437 if(cs->cs_softcar) 438 tp->t_state |= TS_CARR_ON; 439 } 440 441 splx(s); 442 443 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 444 if (error) 445 goto bad; 446 447 error = tp->t_linesw->l_open(dev, tp); 448 if(error) 449 goto bad; 450 return (0); 451 452bad: 453 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 454 /* 455 * We failed to open the device, and nobody else had it opened. 456 * Clean up the state as appropriate. 457 */ 458 zs_shutdown(cs); 459 } 460 return(error); 461} 462 463/* 464 * Close a zs serial port. 465 */ 466int 467zsclose(dev, flags, mode, l) 468dev_t dev; 469int flags; 470int mode; 471struct lwp *l; 472{ 473 register struct zs_chanstate *cs; 474 register struct tty *tp; 475 struct zs_softc *zi; 476 int unit = ZS_UNIT(dev); 477 478 zi = zs_cd.cd_devs[unit >> 1]; 479 cs = &zi->zi_cs[unit & 1]; 480 tp = cs->cs_ttyp; 481 482 tp->t_linesw->l_close(tp, flags); 483 ttyclose(tp); 484 485 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 486 /* 487 * Although we got a last close, the device may still be in 488 * use; e.g. if this was the dialout node, and there are still 489 * processes waiting for carrier on the non-dialout node. 490 */ 491 zs_shutdown(cs); 492 } 493 return (0); 494} 495 496/* 497 * Read/write zs serial port. 498 */ 499int 500zsread(dev, uio, flags) 501dev_t dev; 502struct uio *uio; 503int flags; 504{ 505 register struct zs_chanstate *cs; 506 register struct zs_softc *zi; 507 register struct tty *tp; 508 int unit; 509 510 unit = ZS_UNIT(dev); 511 zi = zs_cd.cd_devs[unit >> 1]; 512 cs = &zi->zi_cs[unit & 1]; 513 tp = cs->cs_ttyp; 514 515 return(tp->t_linesw->l_read(tp, uio, flags)); 516} 517 518int 519zswrite(dev, uio, flags) 520dev_t dev; 521struct uio *uio; 522int flags; 523{ 524 register struct zs_chanstate *cs; 525 register struct zs_softc *zi; 526 register struct tty *tp; 527 int unit; 528 529 unit = ZS_UNIT(dev); 530 zi = zs_cd.cd_devs[unit >> 1]; 531 cs = &zi->zi_cs[unit & 1]; 532 tp = cs->cs_ttyp; 533 534 return(tp->t_linesw->l_write(tp, uio, flags)); 535} 536 537int 538zspoll(dev, events, l) 539dev_t dev; 540int events; 541struct lwp *l; 542{ 543 register struct zs_chanstate *cs; 544 register struct zs_softc *zi; 545 register struct tty *tp; 546 int unit; 547 548 unit = ZS_UNIT(dev); 549 zi = zs_cd.cd_devs[unit >> 1]; 550 cs = &zi->zi_cs[unit & 1]; 551 tp = cs->cs_ttyp; 552 553 return ((*tp->t_linesw->l_poll)(tp, events, l)); 554} 555 556struct tty * 557zstty(dev) 558dev_t dev; 559{ 560 register struct zs_chanstate *cs; 561 register struct zs_softc *zi; 562 int unit; 563 564 unit = ZS_UNIT(dev); 565 zi = zs_cd.cd_devs[unit >> 1]; 566 cs = &zi->zi_cs[unit & 1]; 567 return(cs->cs_ttyp); 568} 569 570/* 571 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 572 * channels are kept in (A,B) pairs. 573 * 574 * Do just a little, then get out; set a software interrupt if more 575 * work is needed. 576 * 577 * We deliberately ignore the vectoring Zilog gives us, and match up 578 * only the number of `reset interrupt under service' operations, not 579 * the order. 580 */ 581 582int 583zshard(sr) 584long sr; 585{ 586 register struct zs_chanstate *a; 587#define b (a + 1) 588 register volatile struct zschan *zc; 589 register int rr3, intflags = 0, v, i; 590 591 do { 592 intflags &= ~4; 593 for(a = zslist; a != NULL; a = b->cs_next) { 594 rr3 = ZS_READ(a->cs_zc, 3); 595 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 596 intflags |= 4|2; 597 zc = a->cs_zc; 598 i = a->cs_rbput; 599 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 600 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 601 intflags |= 1; 602 } 603 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 604 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 605 intflags |= 1; 606 } 607 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 608 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 609 intflags |= 1; 610 } 611 a->cs_rbput = i; 612 } 613 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 614 intflags |= 4|2; 615 zc = b->cs_zc; 616 i = b->cs_rbput; 617 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 618 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 619 intflags |= 1; 620 } 621 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 622 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 623 intflags |= 1; 624 } 625 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 626 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 627 intflags |= 1; 628 } 629 b->cs_rbput = i; 630 } 631 } 632 } while(intflags & 4); 633#undef b 634 635 if(intflags & 1) { 636 if(BASEPRI(sr)) { 637 spl1(); 638 zsshortcuts++; 639 return(zssoft(sr)); 640 } 641 else if(!cb_scheduled) { 642 cb_scheduled++; 643 add_sicallback((si_farg)zssoft, 0, 0); 644 } 645 } 646 return(intflags & 2); 647} 648 649static int 650zsrint(cs, zc) 651register struct zs_chanstate *cs; 652register volatile struct zschan *zc; 653{ 654 register int c; 655 656 /* 657 * First read the status, because read of the received char 658 * destroy the status of this char. 659 */ 660 c = ZS_READ(zc, 1); 661 c |= (zc->zc_data << 8); 662 663 /* clear receive error & interrupt condition */ 664 zc->zc_csr = ZSWR0_RESET_ERRORS; 665 zc->zc_csr = ZSWR0_CLR_INTR; 666 667 return(ZRING_MAKE(ZRING_RINT, c)); 668} 669 670static int 671zsxint(cs, zc) 672register struct zs_chanstate *cs; 673register volatile struct zschan *zc; 674{ 675 register int i = cs->cs_tbc; 676 677 if(i == 0) { 678 zc->zc_csr = ZSWR0_RESET_TXINT; 679 zc->zc_csr = ZSWR0_CLR_INTR; 680 return(ZRING_MAKE(ZRING_XINT, 0)); 681 } 682 cs->cs_tbc = i - 1; 683 zc->zc_data = *cs->cs_tba++; 684 zc->zc_csr = ZSWR0_CLR_INTR; 685 return (0); 686} 687 688static int 689zssint(cs, zc) 690register struct zs_chanstate *cs; 691register volatile struct zschan *zc; 692{ 693 register int rr0; 694 695 rr0 = zc->zc_csr; 696 zc->zc_csr = ZSWR0_RESET_STATUS; 697 zc->zc_csr = ZSWR0_CLR_INTR; 698 /* 699 * The chip's hardware flow control is, as noted in zsreg.h, 700 * busted---if the DCD line goes low the chip shuts off the 701 * receiver (!). If we want hardware CTS flow control but do 702 * not have it, and carrier is now on, turn HFC on; if we have 703 * HFC now but carrier has gone low, turn it off. 704 */ 705 if(rr0 & ZSRR0_DCD) { 706 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 707 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 708 cs->cs_creg[3] |= ZSWR3_HFC; 709 ZS_WRITE(zc, 3, cs->cs_creg[3]); 710 } 711 } 712 else { 713 if (cs->cs_creg[3] & ZSWR3_HFC) { 714 cs->cs_creg[3] &= ~ZSWR3_HFC; 715 ZS_WRITE(zc, 3, cs->cs_creg[3]); 716 } 717 } 718 return(ZRING_MAKE(ZRING_SINT, rr0)); 719} 720 721/* 722 * Print out a ring or fifo overrun error message. 723 */ 724static void 725zsoverrun(unit, ptime, what) 726int unit; 727long *ptime; 728const char *what; 729{ 730 731 if(*ptime != time.tv_sec) { 732 *ptime = time.tv_sec; 733 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 734 (unit & 1) + 'a', what); 735 } 736} 737 738/* 739 * ZS software interrupt. Scan all channels for deferred interrupts. 740 */ 741int 742zssoft(sr) 743long sr; 744{ 745 register struct zs_chanstate *cs; 746 register volatile struct zschan *zc; 747 register struct linesw *line; 748 register struct tty *tp; 749 register int get, n, c, cc, unit, s; 750 int retval = 0; 751 752 cb_scheduled = 0; 753 s = spltty(); 754 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 755 get = cs->cs_rbget; 756again: 757 n = cs->cs_rbput; /* atomic */ 758 if(get == n) /* nothing more on this line */ 759 continue; 760 retval = 1; 761 unit = cs->cs_unit; /* set up to handle interrupts */ 762 zc = cs->cs_zc; 763 tp = cs->cs_ttyp; 764 line = tp->t_linesw; 765 /* 766 * Compute the number of interrupts in the receive ring. 767 * If the count is overlarge, we lost some events, and 768 * must advance to the first valid one. It may get 769 * overwritten if more data are arriving, but this is 770 * too expensive to check and gains nothing (we already 771 * lost out; all we can do at this point is trade one 772 * kind of loss for another). 773 */ 774 n -= get; 775 if(n > ZLRB_RING_SIZE) { 776 zsoverrun(unit, &cs->cs_rotime, "ring"); 777 get += n - ZLRB_RING_SIZE; 778 n = ZLRB_RING_SIZE; 779 } 780 while(--n >= 0) { 781 /* race to keep ahead of incoming interrupts */ 782 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 783 switch (ZRING_TYPE(c)) { 784 785 case ZRING_RINT: 786 c = ZRING_VALUE(c); 787 if(c & ZSRR1_DO) 788 zsoverrun(unit, &cs->cs_fotime, "fifo"); 789 cc = c >> 8; 790 if(c & ZSRR1_FE) 791 cc |= TTY_FE; 792 if(c & ZSRR1_PE) 793 cc |= TTY_PE; 794 line->l_rint(cc, tp); 795 break; 796 797 case ZRING_XINT: 798 /* 799 * Transmit done: change registers and resume, 800 * or clear BUSY. 801 */ 802 if(cs->cs_heldchange) { 803 int sps; 804 805 sps = splzs(); 806 c = zc->zc_csr; 807 if((c & ZSRR0_DCD) == 0) 808 cs->cs_preg[3] &= ~ZSWR3_HFC; 809 bcopy((caddr_t)cs->cs_preg, 810 (caddr_t)cs->cs_creg, 16); 811 zs_loadchannelregs(zc, cs->cs_creg); 812 splx(sps); 813 cs->cs_heldchange = 0; 814 if(cs->cs_heldtbc 815 && (tp->t_state & TS_TTSTOP) == 0) { 816 cs->cs_tbc = cs->cs_heldtbc - 1; 817 zc->zc_data = *cs->cs_tba++; 818 goto again; 819 } 820 } 821 tp->t_state &= ~TS_BUSY; 822 if(tp->t_state & TS_FLUSH) 823 tp->t_state &= ~TS_FLUSH; 824 else ndflush(&tp->t_outq,cs->cs_tba 825 - (caddr_t)tp->t_outq.c_cf); 826 line->l_start(tp); 827 break; 828 829 case ZRING_SINT: 830 /* 831 * Status line change. HFC bit is run in 832 * hardware interrupt, to avoid locking 833 * at splzs here. 834 */ 835 c = ZRING_VALUE(c); 836 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 837 cc = (c & ZSRR0_DCD) != 0; 838 if(line->l_modem(tp, cc) == 0) 839 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 840 cc ? DMBIS : DMBIC); 841 } 842 cs->cs_rr0 = c; 843 break; 844 845 default: 846 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 847 unit >> 1, (unit & 1) + 'a', c); 848 break; 849 } 850 } 851 cs->cs_rbget = get; 852 goto again; 853 } 854 splx(s); 855 return (retval); 856} 857 858int 859zsioctl(dev, cmd, data, flag, l) 860dev_t dev; 861u_long cmd; 862caddr_t data; 863int flag; 864struct lwp *l; 865{ 866 int unit = ZS_UNIT(dev); 867 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 868 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 869 register int error, s; 870 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 871 872 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 873 if(error != EPASSTHROUGH) 874 return(error); 875 876 error = ttioctl(tp, cmd, data, flag, l); 877 if(error !=EPASSTHROUGH) 878 return (error); 879 880 switch (cmd) { 881 case TIOCSBRK: 882 s = splzs(); 883 cs->cs_preg[5] |= ZSWR5_BREAK; 884 cs->cs_creg[5] |= ZSWR5_BREAK; 885 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 886 splx(s); 887 break; 888 case TIOCCBRK: 889 s = splzs(); 890 cs->cs_preg[5] &= ~ZSWR5_BREAK; 891 cs->cs_creg[5] &= ~ZSWR5_BREAK; 892 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 893 splx(s); 894 break; 895 case TIOCGFLAGS: { 896 int bits = 0; 897 898 if(cs->cs_softcar) 899 bits |= TIOCFLAG_SOFTCAR; 900 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 901 bits |= TIOCFLAG_CLOCAL; 902 if(cs->cs_creg[3] & ZSWR3_HFC) 903 bits |= TIOCFLAG_CRTSCTS; 904 *(int *)data = bits; 905 break; 906 } 907 case TIOCSFLAGS: { 908 int userbits = 0; 909 910 error = suser(l->l_proc->p_ucred, &l->l_proc->p_acflag); 911 if(error != 0) 912 return (EPERM); 913 914 userbits = *(int *)data; 915 916 /* 917 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 918 # defaulting to software flow control. 919 */ 920 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 921 return(EINVAL); 922 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 923 return(ENODEV); 924 925 s = splzs(); 926 if((userbits & TIOCFLAG_SOFTCAR)) { 927 cs->cs_softcar = 1; /* turn on softcar */ 928 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 929 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 930 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 931 } 932 else if(userbits & TIOCFLAG_CLOCAL) { 933 cs->cs_softcar = 0; /* turn off softcar */ 934 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 935 cs->cs_creg[15] |= ZSWR15_DCD_IE; 936 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 937 tp->t_termios.c_cflag |= CLOCAL; 938 } 939 if(userbits & TIOCFLAG_CRTSCTS) { 940 cs->cs_preg[15] |= ZSWR15_CTS_IE; 941 cs->cs_creg[15] |= ZSWR15_CTS_IE; 942 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 943 cs->cs_preg[3] |= ZSWR3_HFC; 944 cs->cs_creg[3] |= ZSWR3_HFC; 945 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 946 tp->t_termios.c_cflag |= CRTSCTS; 947 } 948 else { 949 /* no mdmbuf, so we must want software flow control */ 950 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 951 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 952 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 953 cs->cs_preg[3] &= ~ZSWR3_HFC; 954 cs->cs_creg[3] &= ~ZSWR3_HFC; 955 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 956 tp->t_termios.c_cflag &= ~CRTSCTS; 957 } 958 splx(s); 959 break; 960 } 961 case TIOCSDTR: 962 zs_modem(cs, ZSWR5_DTR, DMBIS); 963 break; 964 case TIOCCDTR: 965 zs_modem(cs, ZSWR5_DTR, DMBIC); 966 break; 967 case TIOCMGET: 968 zs_modem(cs, 0, DMGET); 969 break; 970 case TIOCMSET: 971 case TIOCMBIS: 972 case TIOCMBIC: 973 default: 974 return (EPASSTHROUGH); 975 } 976 return (0); 977} 978 979/* 980 * Start or restart transmission. 981 */ 982static void 983zsstart(tp) 984register struct tty *tp; 985{ 986 register struct zs_chanstate *cs; 987 register int s, nch; 988 int unit = ZS_UNIT(tp->t_dev); 989 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 990 991 cs = &zi->zi_cs[unit & 1]; 992 s = spltty(); 993 994 /* 995 * If currently active or delaying, no need to do anything. 996 */ 997 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 998 goto out; 999 1000 /* 1001 * If there are sleepers, and output has drained below low 1002 * water mark, awaken. 1003 */ 1004 if(tp->t_outq.c_cc <= tp->t_lowat) { 1005 if(tp->t_state & TS_ASLEEP) { 1006 tp->t_state &= ~TS_ASLEEP; 1007 wakeup((caddr_t)&tp->t_outq); 1008 } 1009 selwakeup(&tp->t_wsel); 1010 } 1011 1012 nch = ndqb(&tp->t_outq, 0); /* XXX */ 1013 if(nch) { 1014 register char *p = tp->t_outq.c_cf; 1015 1016 /* mark busy, enable tx done interrupts, & send first byte */ 1017 tp->t_state |= TS_BUSY; 1018 (void) splzs(); 1019 cs->cs_preg[1] |= ZSWR1_TIE; 1020 cs->cs_creg[1] |= ZSWR1_TIE; 1021 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1022 cs->cs_zc->zc_data = *p; 1023 cs->cs_tba = p + 1; 1024 cs->cs_tbc = nch - 1; 1025 } else { 1026 /* 1027 * Nothing to send, turn off transmit done interrupts. 1028 * This is useful if something is doing polled output. 1029 */ 1030 (void) splzs(); 1031 cs->cs_preg[1] &= ~ZSWR1_TIE; 1032 cs->cs_creg[1] &= ~ZSWR1_TIE; 1033 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1034 } 1035out: 1036 splx(s); 1037} 1038 1039/* 1040 * Stop output, e.g., for ^S or output flush. 1041 */ 1042void 1043zsstop(tp, flag) 1044register struct tty *tp; 1045 int flag; 1046{ 1047 register struct zs_chanstate *cs; 1048 register int s, unit = ZS_UNIT(tp->t_dev); 1049 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1050 1051 cs = &zi->zi_cs[unit & 1]; 1052 s = splzs(); 1053 if(tp->t_state & TS_BUSY) { 1054 /* 1055 * Device is transmitting; must stop it. 1056 */ 1057 cs->cs_tbc = 0; 1058 if ((tp->t_state & TS_TTSTOP) == 0) 1059 tp->t_state |= TS_FLUSH; 1060 } 1061 splx(s); 1062} 1063 1064static void 1065zs_shutdown(cs) 1066 struct zs_chanstate *cs; 1067{ 1068 struct tty *tp = cs->cs_ttyp; 1069 int s; 1070 1071 s = splzs(); 1072 1073 /* 1074 * Hang up if necessary. Wait a bit, so the other side has time to 1075 * notice even if we immediately open the port again. 1076 */ 1077 if(tp->t_cflag & HUPCL) { 1078 zs_modem(cs, 0, DMSET); 1079 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 1080 } 1081 1082 /* Clear any break condition set with TIOCSBRK. */ 1083 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1084 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1085 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1086 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1087 } 1088 1089 /* 1090 * Drop all lines and cancel interrupts 1091 */ 1092 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1093 splx(s); 1094} 1095 1096/* 1097 * Set ZS tty parameters from termios. 1098 * 1099 * This routine makes use of the fact that only registers 1100 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1101 */ 1102static int 1103zsparam(tp, t) 1104register struct tty *tp; 1105register struct termios *t; 1106{ 1107 int unit = ZS_UNIT(tp->t_dev); 1108 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1109 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1110 int cdiv, clkm, brgm, tcon; 1111 register int tmp, tmp5, cflag, s; 1112 1113 tmp = t->c_ospeed; 1114 tmp5 = t->c_ispeed; 1115 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1116 return(EINVAL); 1117 if(tmp == 0) { 1118 /* stty 0 => drop DTR and RTS */ 1119 zs_modem(cs, 0, DMSET); 1120 return(0); 1121 } 1122 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1123 if (tmp < 0) 1124 return(EINVAL); 1125 tp->t_ispeed = tp->t_ospeed = tmp; 1126 1127 cflag = tp->t_cflag = t->c_cflag; 1128 if (cflag & CSTOPB) 1129 cdiv |= ZSWR4_TWOSB; 1130 else 1131 cdiv |= ZSWR4_ONESB; 1132 if (!(cflag & PARODD)) 1133 cdiv |= ZSWR4_EVENP; 1134 if (cflag & PARENB) 1135 cdiv |= ZSWR4_PARENB; 1136 1137 switch(cflag & CSIZE) { 1138 case CS5: 1139 tmp = ZSWR3_RX_5; 1140 tmp5 = ZSWR5_TX_5; 1141 break; 1142 case CS6: 1143 tmp = ZSWR3_RX_6; 1144 tmp5 = ZSWR5_TX_6; 1145 break; 1146 case CS7: 1147 tmp = ZSWR3_RX_7; 1148 tmp5 = ZSWR5_TX_7; 1149 break; 1150 case CS8: 1151 default: 1152 tmp = ZSWR3_RX_8; 1153 tmp5 = ZSWR5_TX_8; 1154 break; 1155 } 1156 tmp |= ZSWR3_RX_ENABLE; 1157 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1158 1159 /* 1160 * Block interrupts so that state will not 1161 * be altered until we are done setting it up. 1162 */ 1163 s = splzs(); 1164 cs->cs_preg[4] = cdiv; 1165 cs->cs_preg[11] = clkm; 1166 cs->cs_preg[12] = tcon; 1167 cs->cs_preg[13] = tcon >> 8; 1168 cs->cs_preg[14] = brgm; 1169 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1170 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1171 cs->cs_preg[10] = ZSWR10_NRZ; 1172 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1173 1174 /* 1175 * Output hardware flow control on the chip is horrendous: if 1176 * carrier detect drops, the receiver is disabled. Hence we 1177 * can only do this when the carrier is on. 1178 */ 1179 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1180 tmp |= ZSWR3_HFC; 1181 cs->cs_preg[3] = tmp; 1182 cs->cs_preg[5] = tmp5; 1183 1184 /* 1185 * If nothing is being transmitted, set up new current values, 1186 * else mark them as pending. 1187 */ 1188 if(cs->cs_heldchange == 0) { 1189 if (cs->cs_ttyp->t_state & TS_BUSY) { 1190 cs->cs_heldtbc = cs->cs_tbc; 1191 cs->cs_tbc = 0; 1192 cs->cs_heldchange = 1; 1193 } else { 1194 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1195 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1196 } 1197 } 1198 splx(s); 1199 return (0); 1200} 1201 1202/* 1203 * search for the best matching baudrate 1204 */ 1205static int 1206zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1207int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1208{ 1209 int bestdiff, bestbps, source; 1210 1211 bestdiff = bestbps = 0; 1212 unit = (unit & 1) << 2; 1213 for (source = 0; source < 4; ++source) { 1214 long freq = zs_frequencies[unit + source]; 1215 int diff, bps, div, clkm, brgm, tcon; 1216 1217 bps = div = clkm = brgm = tcon = 0; 1218 switch (source) { 1219 case 0: /* BRgen, PCLK */ 1220 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1221 break; 1222 case 1: /* BRgen, RTxC */ 1223 brgm = ZSWR14_BAUD_ENA; 1224 break; 1225 case 2: /* RTxC */ 1226 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1227 break; 1228 case 3: /* TRxC */ 1229 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1230 break; 1231 } 1232 switch (source) { 1233 case 0: 1234 case 1: 1235 div = ZSWR4_CLK_X16; 1236 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1237 tcon = BPS_TO_TCONST(freq, wanted); 1238 if (tcon < 0) 1239 tcon = 0; 1240 bps = TCONST_TO_BPS(freq, tcon); 1241 break; 1242 case 2: 1243 case 3: 1244 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1245 int b2 = freq / 32, d2 = abs(b2 - wanted); 1246 int b3 = freq / 64, d3 = abs(b3 - wanted); 1247 1248 if (d1 < d2 && d1 < d3) { 1249 div = ZSWR4_CLK_X16; 1250 bps = b1; 1251 } else if (d2 < d3 && d2 < d1) { 1252 div = ZSWR4_CLK_X32; 1253 bps = b2; 1254 } else { 1255 div = ZSWR4_CLK_X64; 1256 bps = b3; 1257 } 1258 brgm = tcon = 0; 1259 break; 1260 } 1261 } 1262 diff = abs(bps - wanted); 1263 if (!source || diff < bestdiff) { 1264 *divisor = div; 1265 *clockmode = clkm; 1266 *brgenmode = brgm; 1267 *timeconst = tcon; 1268 bestbps = bps; 1269 bestdiff = diff; 1270 if (diff == 0) 1271 break; 1272 } 1273 } 1274 /* Allow deviations upto 5% */ 1275 if (20 * bestdiff > wanted) 1276 return -1; 1277 return bestbps; 1278} 1279 1280/* 1281 * Raise or lower modem control (DTR/RTS) signals. If a character is 1282 * in transmission, the change is deferred. 1283 */ 1284static int 1285zs_modem(cs, bits, how) 1286struct zs_chanstate *cs; 1287int bits, how; 1288{ 1289 int s, mbits; 1290 1291 bits &= ZSWR5_DTR | ZSWR5_RTS; 1292 1293 s = splzs(); 1294 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1295 1296 switch(how) { 1297 case DMSET: 1298 mbits = bits; 1299 break; 1300 case DMBIS: 1301 mbits |= bits; 1302 break; 1303 case DMBIC: 1304 mbits &= ~bits; 1305 break; 1306 case DMGET: 1307 splx(s); 1308 return(mbits); 1309 } 1310 1311 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1312 if(cs->cs_heldchange == 0) { 1313 if(cs->cs_ttyp->t_state & TS_BUSY) { 1314 cs->cs_heldtbc = cs->cs_tbc; 1315 cs->cs_tbc = 0; 1316 cs->cs_heldchange = 1; 1317 } 1318 else { 1319 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1320 } 1321 } 1322 splx(s); 1323 return(0); 1324} 1325 1326/* 1327 * Write the given register set to the given zs channel in the proper order. 1328 * The channel must not be transmitting at the time. The receiver will 1329 * be disabled for the time it takes to write all the registers. 1330 */ 1331static void 1332zs_loadchannelregs(zc, reg) 1333volatile struct zschan *zc; 1334u_char *reg; 1335{ 1336 int i; 1337 1338 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1339 i = zc->zc_data; /* drain fifo */ 1340 i = zc->zc_data; 1341 i = zc->zc_data; 1342 ZS_WRITE(zc, 4, reg[4]); 1343 ZS_WRITE(zc, 10, reg[10]); 1344 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1345 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1346 ZS_WRITE(zc, 1, reg[1]); 1347 ZS_WRITE(zc, 9, reg[9]); 1348 ZS_WRITE(zc, 11, reg[11]); 1349 ZS_WRITE(zc, 12, reg[12]); 1350 ZS_WRITE(zc, 13, reg[13]); 1351 ZS_WRITE(zc, 14, reg[14]); 1352 ZS_WRITE(zc, 15, reg[15]); 1353 ZS_WRITE(zc, 3, reg[3]); 1354 ZS_WRITE(zc, 5, reg[5]); 1355} 1356#endif /* NZS > 1 */ 1357