zs.c revision 1.40
1/* $NetBSD: zs.c,v 1.40 2003/07/15 01:19:53 lukem Exp $ */ 2 3/* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49/* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56 57#include <sys/cdefs.h> 58__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.40 2003/07/15 01:19:53 lukem Exp $"); 59 60#include <sys/param.h> 61#include <sys/systm.h> 62#include <sys/proc.h> 63#include <sys/device.h> 64#include <sys/conf.h> 65#include <sys/file.h> 66#include <sys/ioctl.h> 67#include <sys/malloc.h> 68#include <sys/tty.h> 69#include <sys/time.h> 70#include <sys/kernel.h> 71#include <sys/syslog.h> 72 73#include <machine/cpu.h> 74#include <machine/iomap.h> 75#include <machine/scu.h> 76#include <machine/mfp.h> 77#include <atari/dev/ym2149reg.h> 78 79#include <dev/ic/z8530reg.h> 80#include <atari/dev/zsvar.h> 81#include "zs.h" 82#if NZS > 1 83#error "This driver supports only 1 85C30!" 84#endif 85 86#if NZS > 0 87 88#define PCLK (8053976) /* PCLK pin input clock rate */ 89#define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 90 91#define splzs spl5 92 93/* 94 * Software state per found chip. 95 */ 96struct zs_softc { 97 struct device zi_dev; /* base device */ 98 volatile struct zsdevice *zi_zs; /* chip registers */ 99 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 100}; 101 102static u_char cb_scheduled = 0; /* Already asked for callback? */ 103/* 104 * Define the registers for a closed port 105 */ 106static u_char zs_init_regs[16] = { 107/* 0 */ 0, 108/* 1 */ 0, 109/* 2 */ 0x60, 110/* 3 */ 0, 111/* 4 */ 0, 112/* 5 */ 0, 113/* 6 */ 0, 114/* 7 */ 0, 115/* 8 */ 0, 116/* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 117/* 10 */ ZSWR10_NRZ, 118/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 119/* 12 */ 0, 120/* 13 */ 0, 121/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 122/* 15 */ 0 123}; 124 125/* 126 * Define the machine dependant clock frequencies 127 * If BRgen feeds sender/receiver we always use a 128 * divisor 16, therefor the division by 16 can as 129 * well be done here. 130 */ 131static u_long zs_freqs_tt[] = { 132 /* 133 * Atari TT, RTxCB is generated by TT-MFP timer C, 134 * which is set to 307.2KHz during initialisation 135 * and never changed afterwards. 136 */ 137 PCLK/16, /* BRgen, PCLK, divisor 16 */ 138 229500, /* BRgen, RTxCA, divisor 16 */ 139 3672000, /* RTxCA, from PCLK4 */ 140 0, /* TRxCA, external */ 141 142 PCLK/16, /* BRgen, PCLK, divisor 16 */ 143 19200, /* BRgen, RTxCB, divisor 16 */ 144 307200, /* RTxCB, from TT-MFP TCO */ 145 2457600 /* TRxCB, from BCLK */ 146}; 147 148static u_long zs_freqs_falcon[] = { 149 /* 150 * Atari Falcon, XXX no specs available, this might be wrong 151 */ 152 PCLK/16, /* BRgen, PCLK, divisor 16 */ 153 229500, /* BRgen, RTxCA, divisor 16 */ 154 3672000, /* RTxCA, ??? */ 155 0, /* TRxCA, external */ 156 157 PCLK/16, /* BRgen, PCLK, divisor 16 */ 158 229500, /* BRgen, RTxCB, divisor 16 */ 159 3672000, /* RTxCB, ??? */ 160 2457600 /* TRxCB, ??? */ 161}; 162 163static u_long zs_freqs_hades[] = { 164 /* 165 * XXX: Channel-A unchecked!!!!! 166 */ 167 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 168 229500, /* BRgen, RTxCA, divisor 16 */ 169 3672000, /* RTxCA, from PCLK4 */ 170 0, /* TRxCA, external */ 171 172 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 173 235550, /* BRgen, RTxCB, divisor 16 */ 174 3768800, /* RTxCB, 3.7688MHz */ 175 3768800 /* TRxCB, 3.7688MHz */ 176}; 177 178static u_long zs_freqs_generic[] = { 179 /* 180 * other machines, assume only PCLK is available 181 */ 182 PCLK/16, /* BRgen, PCLK, divisor 16 */ 183 0, /* BRgen, RTxCA, divisor 16 */ 184 0, /* RTxCA, unknown */ 185 0, /* TRxCA, unknown */ 186 187 PCLK/16, /* BRgen, PCLK, divisor 16 */ 188 0, /* BRgen, RTxCB, divisor 16 */ 189 0, /* RTxCB, unknown */ 190 0 /* TRxCB, unknown */ 191}; 192static u_long *zs_frequencies; 193 194/* Definition of the driver for autoconfig. */ 195static int zsmatch __P((struct device *, struct cfdata *, void *)); 196static void zsattach __P((struct device *, struct device *, void *)); 197 198CFATTACH_DECL(zs, sizeof(struct zs_softc), 199 zsmatch, zsattach, NULL, NULL); 200 201extern struct cfdriver zs_cd; 202 203/* {b,c}devsw[] function prototypes */ 204dev_type_open(zsopen); 205dev_type_close(zsclose); 206dev_type_read(zsread); 207dev_type_write(zswrite); 208dev_type_ioctl(zsioctl); 209dev_type_stop(zsstop); 210dev_type_tty(zstty); 211dev_type_poll(zspoll); 212 213const struct cdevsw zs_cdevsw = { 214 zsopen, zsclose, zsread, zswrite, zsioctl, 215 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 216}; 217 218/* Interrupt handlers. */ 219int zshard __P((long)); 220static int zssoft __P((long)); 221static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 222static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 223static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 224 225static struct zs_chanstate *zslist; 226 227/* Routines called from other code. */ 228static void zsstart __P((struct tty *)); 229 230/* Routines purely local to this driver. */ 231static void zsoverrun __P((int, long *, char *)); 232static int zsparam __P((struct tty *, struct termios *)); 233static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 234static int zs_modem __P((struct zs_chanstate *, int, int)); 235static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 236static void zs_shutdown __P((struct zs_chanstate *)); 237 238static int zsshortcuts; /* number of "shortcut" software interrupts */ 239 240static int 241zsmatch(pdp, cfp, auxp) 242struct device *pdp; 243struct cfdata *cfp; 244void *auxp; 245{ 246 static int zs_matched = 0; 247 248 if(strcmp("zs", auxp) || zs_matched) 249 return(0); 250 zs_matched = 1; 251 return(1); 252} 253 254/* 255 * Attach a found zs. 256 */ 257static void 258zsattach(parent, dev, aux) 259struct device *parent; 260struct device *dev; 261void *aux; 262{ 263 register struct zs_softc *zi; 264 register struct zs_chanstate *cs; 265 register volatile struct zsdevice *addr; 266 char tmp; 267 268 addr = (struct zsdevice *)AD_SCC; 269 zi = (struct zs_softc *)dev; 270 zi->zi_zs = addr; 271 cs = zi->zi_cs; 272 273 /* 274 * Get the command register into a known state. 275 */ 276 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 277 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 278 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 279 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 280 281 /* 282 * Do a hardware reset. 283 */ 284 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 285 delay(50000); /*enough ? */ 286 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 287 288 /* 289 * Initialize both channels 290 */ 291 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 292 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 293 294 if(machineid & ATARI_TT) { 295 /* 296 * ininitialise TT-MFP timer C: 307200Hz 297 * timer C and D share one control register: 298 * bits 0-2 control timer D 299 * bits 4-6 control timer C 300 */ 301 int cr = MFP2->mf_tcdcr & 7; 302 MFP2->mf_tcdcr = cr; /* stop timer C */ 303 MFP2->mf_tcdr = 1; /* counter 1 */ 304 cr |= T_Q004 << 4; /* divisor 4 */ 305 MFP2->mf_tcdcr = cr; /* start timer C */ 306 /* 307 * enable scc related interrupts 308 */ 309 SCU->vme_mask |= SCU_SCC; 310 311 zs_frequencies = zs_freqs_tt; 312 } else if (machineid & ATARI_FALCON) { 313 zs_frequencies = zs_freqs_falcon; 314 } else if (machineid & ATARI_HADES) { 315 zs_frequencies = zs_freqs_hades; 316 } else { 317 zs_frequencies = zs_freqs_generic; 318 } 319 320 /* link into interrupt list with order (A,B) (B=A+1) */ 321 cs[0].cs_next = &cs[1]; 322 cs[1].cs_next = zslist; 323 zslist = cs; 324 325 cs->cs_unit = 0; 326 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 327 cs++; 328 cs->cs_unit = 1; 329 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 330 331 printf(": serial2 on channel a and modem2 on channel b\n"); 332} 333 334/* 335 * Open a zs serial port. 336 */ 337int 338zsopen(dev, flags, mode, p) 339dev_t dev; 340int flags; 341int mode; 342struct proc *p; 343{ 344 register struct tty *tp; 345 register struct zs_chanstate *cs; 346 struct zs_softc *zi; 347 int unit = ZS_UNIT(dev); 348 int zs = unit >> 1; 349 int error, s; 350 351 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 352 return (ENXIO); 353 cs = &zi->zi_cs[unit & 1]; 354 355 /* 356 * When port A (ser02) is selected on the TT, make sure 357 * the port is enabled. 358 */ 359 if((machineid & ATARI_TT) && !(unit & 1)) 360 ym2149_ser2(1); 361 362 if (cs->cs_rbuf == NULL) { 363 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 364 M_WAITOK); 365 } 366 367 tp = cs->cs_ttyp; 368 if(tp == NULL) { 369 cs->cs_ttyp = tp = ttymalloc(); 370 tty_attach(tp); 371 tp->t_dev = dev; 372 tp->t_oproc = zsstart; 373 tp->t_param = zsparam; 374 } 375 376 if ((tp->t_state & TS_ISOPEN) && 377 (tp->t_state & TS_XCLUDE) && 378 p->p_ucred->cr_uid != 0) 379 return (EBUSY); 380 381 s = spltty(); 382 383 /* 384 * Do the following iff this is a first open. 385 */ 386 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 387 if(tp->t_ispeed == 0) { 388 tp->t_iflag = TTYDEF_IFLAG; 389 tp->t_oflag = TTYDEF_OFLAG; 390 tp->t_cflag = TTYDEF_CFLAG; 391 tp->t_lflag = TTYDEF_LFLAG; 392 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 393 } 394 ttychars(tp); 395 ttsetwater(tp); 396 397 (void)zsparam(tp, &tp->t_termios); 398 399 /* 400 * Turn on DTR. We must always do this, even if carrier is not 401 * present, because otherwise we'd have to use TIOCSDTR 402 * immediately after setting CLOCAL, which applications do not 403 * expect. We always assert DTR while the device is open 404 * unless explicitly requested to deassert it. 405 */ 406 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 407 /* May never get a status intr. if DCD already on. -gwr */ 408 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 409 tp->t_state |= TS_CARR_ON; 410 if(cs->cs_softcar) 411 tp->t_state |= TS_CARR_ON; 412 } 413 414 splx(s); 415 416 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 417 if (error) 418 goto bad; 419 420 error = tp->t_linesw->l_open(dev, tp); 421 if(error) 422 goto bad; 423 return (0); 424 425bad: 426 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 427 /* 428 * We failed to open the device, and nobody else had it opened. 429 * Clean up the state as appropriate. 430 */ 431 zs_shutdown(cs); 432 } 433 return(error); 434} 435 436/* 437 * Close a zs serial port. 438 */ 439int 440zsclose(dev, flags, mode, p) 441dev_t dev; 442int flags; 443int mode; 444struct proc *p; 445{ 446 register struct zs_chanstate *cs; 447 register struct tty *tp; 448 struct zs_softc *zi; 449 int unit = ZS_UNIT(dev); 450 451 zi = zs_cd.cd_devs[unit >> 1]; 452 cs = &zi->zi_cs[unit & 1]; 453 tp = cs->cs_ttyp; 454 455 tp->t_linesw->l_close(tp, flags); 456 ttyclose(tp); 457 458 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 459 /* 460 * Although we got a last close, the device may still be in 461 * use; e.g. if this was the dialout node, and there are still 462 * processes waiting for carrier on the non-dialout node. 463 */ 464 zs_shutdown(cs); 465 } 466 return (0); 467} 468 469/* 470 * Read/write zs serial port. 471 */ 472int 473zsread(dev, uio, flags) 474dev_t dev; 475struct uio *uio; 476int flags; 477{ 478 register struct zs_chanstate *cs; 479 register struct zs_softc *zi; 480 register struct tty *tp; 481 int unit; 482 483 unit = ZS_UNIT(dev); 484 zi = zs_cd.cd_devs[unit >> 1]; 485 cs = &zi->zi_cs[unit & 1]; 486 tp = cs->cs_ttyp; 487 488 return(tp->t_linesw->l_read(tp, uio, flags)); 489} 490 491int 492zswrite(dev, uio, flags) 493dev_t dev; 494struct uio *uio; 495int flags; 496{ 497 register struct zs_chanstate *cs; 498 register struct zs_softc *zi; 499 register struct tty *tp; 500 int unit; 501 502 unit = ZS_UNIT(dev); 503 zi = zs_cd.cd_devs[unit >> 1]; 504 cs = &zi->zi_cs[unit & 1]; 505 tp = cs->cs_ttyp; 506 507 return(tp->t_linesw->l_write(tp, uio, flags)); 508} 509 510int 511zspoll(dev, events, p) 512dev_t dev; 513int events; 514struct proc *p; 515{ 516 register struct zs_chanstate *cs; 517 register struct zs_softc *zi; 518 register struct tty *tp; 519 int unit; 520 521 unit = ZS_UNIT(dev); 522 zi = zs_cd.cd_devs[unit >> 1]; 523 cs = &zi->zi_cs[unit & 1]; 524 tp = cs->cs_ttyp; 525 526 return ((*tp->t_linesw->l_poll)(tp, events, p)); 527} 528 529struct tty * 530zstty(dev) 531dev_t dev; 532{ 533 register struct zs_chanstate *cs; 534 register struct zs_softc *zi; 535 int unit; 536 537 unit = ZS_UNIT(dev); 538 zi = zs_cd.cd_devs[unit >> 1]; 539 cs = &zi->zi_cs[unit & 1]; 540 return(cs->cs_ttyp); 541} 542 543/* 544 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 545 * channels are kept in (A,B) pairs. 546 * 547 * Do just a little, then get out; set a software interrupt if more 548 * work is needed. 549 * 550 * We deliberately ignore the vectoring Zilog gives us, and match up 551 * only the number of `reset interrupt under service' operations, not 552 * the order. 553 */ 554 555int 556zshard(sr) 557long sr; 558{ 559 register struct zs_chanstate *a; 560#define b (a + 1) 561 register volatile struct zschan *zc; 562 register int rr3, intflags = 0, v, i; 563 564 do { 565 intflags &= ~4; 566 for(a = zslist; a != NULL; a = b->cs_next) { 567 rr3 = ZS_READ(a->cs_zc, 3); 568 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 569 intflags |= 4|2; 570 zc = a->cs_zc; 571 i = a->cs_rbput; 572 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 573 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 574 intflags |= 1; 575 } 576 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 577 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 578 intflags |= 1; 579 } 580 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 581 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 582 intflags |= 1; 583 } 584 a->cs_rbput = i; 585 } 586 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 587 intflags |= 4|2; 588 zc = b->cs_zc; 589 i = b->cs_rbput; 590 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 591 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 592 intflags |= 1; 593 } 594 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 595 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 596 intflags |= 1; 597 } 598 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 599 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 600 intflags |= 1; 601 } 602 b->cs_rbput = i; 603 } 604 } 605 } while(intflags & 4); 606#undef b 607 608 if(intflags & 1) { 609 if(BASEPRI(sr)) { 610 spl1(); 611 zsshortcuts++; 612 return(zssoft(sr)); 613 } 614 else if(!cb_scheduled) { 615 cb_scheduled++; 616 add_sicallback((si_farg)zssoft, 0, 0); 617 } 618 } 619 return(intflags & 2); 620} 621 622static int 623zsrint(cs, zc) 624register struct zs_chanstate *cs; 625register volatile struct zschan *zc; 626{ 627 register int c; 628 629 /* 630 * First read the status, because read of the received char 631 * destroy the status of this char. 632 */ 633 c = ZS_READ(zc, 1); 634 c |= (zc->zc_data << 8); 635 636 /* clear receive error & interrupt condition */ 637 zc->zc_csr = ZSWR0_RESET_ERRORS; 638 zc->zc_csr = ZSWR0_CLR_INTR; 639 640 return(ZRING_MAKE(ZRING_RINT, c)); 641} 642 643static int 644zsxint(cs, zc) 645register struct zs_chanstate *cs; 646register volatile struct zschan *zc; 647{ 648 register int i = cs->cs_tbc; 649 650 if(i == 0) { 651 zc->zc_csr = ZSWR0_RESET_TXINT; 652 zc->zc_csr = ZSWR0_CLR_INTR; 653 return(ZRING_MAKE(ZRING_XINT, 0)); 654 } 655 cs->cs_tbc = i - 1; 656 zc->zc_data = *cs->cs_tba++; 657 zc->zc_csr = ZSWR0_CLR_INTR; 658 return (0); 659} 660 661static int 662zssint(cs, zc) 663register struct zs_chanstate *cs; 664register volatile struct zschan *zc; 665{ 666 register int rr0; 667 668 rr0 = zc->zc_csr; 669 zc->zc_csr = ZSWR0_RESET_STATUS; 670 zc->zc_csr = ZSWR0_CLR_INTR; 671 /* 672 * The chip's hardware flow control is, as noted in zsreg.h, 673 * busted---if the DCD line goes low the chip shuts off the 674 * receiver (!). If we want hardware CTS flow control but do 675 * not have it, and carrier is now on, turn HFC on; if we have 676 * HFC now but carrier has gone low, turn it off. 677 */ 678 if(rr0 & ZSRR0_DCD) { 679 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 680 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 681 cs->cs_creg[3] |= ZSWR3_HFC; 682 ZS_WRITE(zc, 3, cs->cs_creg[3]); 683 } 684 } 685 else { 686 if (cs->cs_creg[3] & ZSWR3_HFC) { 687 cs->cs_creg[3] &= ~ZSWR3_HFC; 688 ZS_WRITE(zc, 3, cs->cs_creg[3]); 689 } 690 } 691 return(ZRING_MAKE(ZRING_SINT, rr0)); 692} 693 694/* 695 * Print out a ring or fifo overrun error message. 696 */ 697static void 698zsoverrun(unit, ptime, what) 699int unit; 700long *ptime; 701char *what; 702{ 703 704 if(*ptime != time.tv_sec) { 705 *ptime = time.tv_sec; 706 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 707 (unit & 1) + 'a', what); 708 } 709} 710 711/* 712 * ZS software interrupt. Scan all channels for deferred interrupts. 713 */ 714int 715zssoft(sr) 716long sr; 717{ 718 register struct zs_chanstate *cs; 719 register volatile struct zschan *zc; 720 register struct linesw *line; 721 register struct tty *tp; 722 register int get, n, c, cc, unit, s; 723 int retval = 0; 724 725 cb_scheduled = 0; 726 s = spltty(); 727 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 728 get = cs->cs_rbget; 729again: 730 n = cs->cs_rbput; /* atomic */ 731 if(get == n) /* nothing more on this line */ 732 continue; 733 retval = 1; 734 unit = cs->cs_unit; /* set up to handle interrupts */ 735 zc = cs->cs_zc; 736 tp = cs->cs_ttyp; 737 line = tp->t_linesw; 738 /* 739 * Compute the number of interrupts in the receive ring. 740 * If the count is overlarge, we lost some events, and 741 * must advance to the first valid one. It may get 742 * overwritten if more data are arriving, but this is 743 * too expensive to check and gains nothing (we already 744 * lost out; all we can do at this point is trade one 745 * kind of loss for another). 746 */ 747 n -= get; 748 if(n > ZLRB_RING_SIZE) { 749 zsoverrun(unit, &cs->cs_rotime, "ring"); 750 get += n - ZLRB_RING_SIZE; 751 n = ZLRB_RING_SIZE; 752 } 753 while(--n >= 0) { 754 /* race to keep ahead of incoming interrupts */ 755 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 756 switch (ZRING_TYPE(c)) { 757 758 case ZRING_RINT: 759 c = ZRING_VALUE(c); 760 if(c & ZSRR1_DO) 761 zsoverrun(unit, &cs->cs_fotime, "fifo"); 762 cc = c >> 8; 763 if(c & ZSRR1_FE) 764 cc |= TTY_FE; 765 if(c & ZSRR1_PE) 766 cc |= TTY_PE; 767 line->l_rint(cc, tp); 768 break; 769 770 case ZRING_XINT: 771 /* 772 * Transmit done: change registers and resume, 773 * or clear BUSY. 774 */ 775 if(cs->cs_heldchange) { 776 int sps; 777 778 sps = splzs(); 779 c = zc->zc_csr; 780 if((c & ZSRR0_DCD) == 0) 781 cs->cs_preg[3] &= ~ZSWR3_HFC; 782 bcopy((caddr_t)cs->cs_preg, 783 (caddr_t)cs->cs_creg, 16); 784 zs_loadchannelregs(zc, cs->cs_creg); 785 splx(sps); 786 cs->cs_heldchange = 0; 787 if(cs->cs_heldtbc 788 && (tp->t_state & TS_TTSTOP) == 0) { 789 cs->cs_tbc = cs->cs_heldtbc - 1; 790 zc->zc_data = *cs->cs_tba++; 791 goto again; 792 } 793 } 794 tp->t_state &= ~TS_BUSY; 795 if(tp->t_state & TS_FLUSH) 796 tp->t_state &= ~TS_FLUSH; 797 else ndflush(&tp->t_outq,cs->cs_tba 798 - (caddr_t)tp->t_outq.c_cf); 799 line->l_start(tp); 800 break; 801 802 case ZRING_SINT: 803 /* 804 * Status line change. HFC bit is run in 805 * hardware interrupt, to avoid locking 806 * at splzs here. 807 */ 808 c = ZRING_VALUE(c); 809 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 810 cc = (c & ZSRR0_DCD) != 0; 811 if(line->l_modem(tp, cc) == 0) 812 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 813 cc ? DMBIS : DMBIC); 814 } 815 cs->cs_rr0 = c; 816 break; 817 818 default: 819 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 820 unit >> 1, (unit & 1) + 'a', c); 821 break; 822 } 823 } 824 cs->cs_rbget = get; 825 goto again; 826 } 827 splx(s); 828 return (retval); 829} 830 831int 832zsioctl(dev, cmd, data, flag, p) 833dev_t dev; 834u_long cmd; 835caddr_t data; 836int flag; 837struct proc *p; 838{ 839 int unit = ZS_UNIT(dev); 840 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 841 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 842 register int error, s; 843 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 844 845 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, p); 846 if(error != EPASSTHROUGH) 847 return(error); 848 849 error = ttioctl(tp, cmd, data, flag, p); 850 if(error !=EPASSTHROUGH) 851 return (error); 852 853 switch (cmd) { 854 case TIOCSBRK: 855 s = splzs(); 856 cs->cs_preg[5] |= ZSWR5_BREAK; 857 cs->cs_creg[5] |= ZSWR5_BREAK; 858 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 859 splx(s); 860 break; 861 case TIOCCBRK: 862 s = splzs(); 863 cs->cs_preg[5] &= ~ZSWR5_BREAK; 864 cs->cs_creg[5] &= ~ZSWR5_BREAK; 865 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 866 splx(s); 867 break; 868 case TIOCGFLAGS: { 869 int bits = 0; 870 871 if(cs->cs_softcar) 872 bits |= TIOCFLAG_SOFTCAR; 873 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 874 bits |= TIOCFLAG_CLOCAL; 875 if(cs->cs_creg[3] & ZSWR3_HFC) 876 bits |= TIOCFLAG_CRTSCTS; 877 *(int *)data = bits; 878 break; 879 } 880 case TIOCSFLAGS: { 881 int userbits = 0; 882 883 error = suser(p->p_ucred, &p->p_acflag); 884 if(error != 0) 885 return (EPERM); 886 887 userbits = *(int *)data; 888 889 /* 890 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 891 # defaulting to software flow control. 892 */ 893 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 894 return(EINVAL); 895 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 896 return(ENODEV); 897 898 s = splzs(); 899 if((userbits & TIOCFLAG_SOFTCAR)) { 900 cs->cs_softcar = 1; /* turn on softcar */ 901 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 902 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 903 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 904 } 905 else if(userbits & TIOCFLAG_CLOCAL) { 906 cs->cs_softcar = 0; /* turn off softcar */ 907 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 908 cs->cs_creg[15] |= ZSWR15_DCD_IE; 909 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 910 tp->t_termios.c_cflag |= CLOCAL; 911 } 912 if(userbits & TIOCFLAG_CRTSCTS) { 913 cs->cs_preg[15] |= ZSWR15_CTS_IE; 914 cs->cs_creg[15] |= ZSWR15_CTS_IE; 915 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 916 cs->cs_preg[3] |= ZSWR3_HFC; 917 cs->cs_creg[3] |= ZSWR3_HFC; 918 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 919 tp->t_termios.c_cflag |= CRTSCTS; 920 } 921 else { 922 /* no mdmbuf, so we must want software flow control */ 923 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 924 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 925 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 926 cs->cs_preg[3] &= ~ZSWR3_HFC; 927 cs->cs_creg[3] &= ~ZSWR3_HFC; 928 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 929 tp->t_termios.c_cflag &= ~CRTSCTS; 930 } 931 splx(s); 932 break; 933 } 934 case TIOCSDTR: 935 zs_modem(cs, ZSWR5_DTR, DMBIS); 936 break; 937 case TIOCCDTR: 938 zs_modem(cs, ZSWR5_DTR, DMBIC); 939 break; 940 case TIOCMGET: 941 zs_modem(cs, 0, DMGET); 942 break; 943 case TIOCMSET: 944 case TIOCMBIS: 945 case TIOCMBIC: 946 default: 947 return (EPASSTHROUGH); 948 } 949 return (0); 950} 951 952/* 953 * Start or restart transmission. 954 */ 955static void 956zsstart(tp) 957register struct tty *tp; 958{ 959 register struct zs_chanstate *cs; 960 register int s, nch; 961 int unit = ZS_UNIT(tp->t_dev); 962 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 963 964 cs = &zi->zi_cs[unit & 1]; 965 s = spltty(); 966 967 /* 968 * If currently active or delaying, no need to do anything. 969 */ 970 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 971 goto out; 972 973 /* 974 * If there are sleepers, and output has drained below low 975 * water mark, awaken. 976 */ 977 if(tp->t_outq.c_cc <= tp->t_lowat) { 978 if(tp->t_state & TS_ASLEEP) { 979 tp->t_state &= ~TS_ASLEEP; 980 wakeup((caddr_t)&tp->t_outq); 981 } 982 selwakeup(&tp->t_wsel); 983 } 984 985 nch = ndqb(&tp->t_outq, 0); /* XXX */ 986 if(nch) { 987 register char *p = tp->t_outq.c_cf; 988 989 /* mark busy, enable tx done interrupts, & send first byte */ 990 tp->t_state |= TS_BUSY; 991 (void) splzs(); 992 cs->cs_preg[1] |= ZSWR1_TIE; 993 cs->cs_creg[1] |= ZSWR1_TIE; 994 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 995 cs->cs_zc->zc_data = *p; 996 cs->cs_tba = p + 1; 997 cs->cs_tbc = nch - 1; 998 } else { 999 /* 1000 * Nothing to send, turn off transmit done interrupts. 1001 * This is useful if something is doing polled output. 1002 */ 1003 (void) splzs(); 1004 cs->cs_preg[1] &= ~ZSWR1_TIE; 1005 cs->cs_creg[1] &= ~ZSWR1_TIE; 1006 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1007 } 1008out: 1009 splx(s); 1010} 1011 1012/* 1013 * Stop output, e.g., for ^S or output flush. 1014 */ 1015void 1016zsstop(tp, flag) 1017register struct tty *tp; 1018 int flag; 1019{ 1020 register struct zs_chanstate *cs; 1021 register int s, unit = ZS_UNIT(tp->t_dev); 1022 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1023 1024 cs = &zi->zi_cs[unit & 1]; 1025 s = splzs(); 1026 if(tp->t_state & TS_BUSY) { 1027 /* 1028 * Device is transmitting; must stop it. 1029 */ 1030 cs->cs_tbc = 0; 1031 if ((tp->t_state & TS_TTSTOP) == 0) 1032 tp->t_state |= TS_FLUSH; 1033 } 1034 splx(s); 1035} 1036 1037static void 1038zs_shutdown(cs) 1039 struct zs_chanstate *cs; 1040{ 1041 struct tty *tp = cs->cs_ttyp; 1042 int s; 1043 1044 s = splzs(); 1045 1046 /* 1047 * Hang up if necessary. Wait a bit, so the other side has time to 1048 * notice even if we immediately open the port again. 1049 */ 1050 if(tp->t_cflag & HUPCL) { 1051 zs_modem(cs, 0, DMSET); 1052 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 1053 } 1054 1055 /* Clear any break condition set with TIOCSBRK. */ 1056 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1057 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1058 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1059 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1060 } 1061 1062 /* 1063 * Drop all lines and cancel interrupts 1064 */ 1065 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1066 splx(s); 1067} 1068 1069/* 1070 * Set ZS tty parameters from termios. 1071 * 1072 * This routine makes use of the fact that only registers 1073 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1074 */ 1075static int 1076zsparam(tp, t) 1077register struct tty *tp; 1078register struct termios *t; 1079{ 1080 int unit = ZS_UNIT(tp->t_dev); 1081 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1082 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1083 int cdiv, clkm, brgm, tcon; 1084 register int tmp, tmp5, cflag, s; 1085 1086 tmp = t->c_ospeed; 1087 tmp5 = t->c_ispeed; 1088 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1089 return(EINVAL); 1090 if(tmp == 0) { 1091 /* stty 0 => drop DTR and RTS */ 1092 zs_modem(cs, 0, DMSET); 1093 return(0); 1094 } 1095 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1096 if (tmp < 0) 1097 return(EINVAL); 1098 tp->t_ispeed = tp->t_ospeed = tmp; 1099 1100 cflag = tp->t_cflag = t->c_cflag; 1101 if (cflag & CSTOPB) 1102 cdiv |= ZSWR4_TWOSB; 1103 else 1104 cdiv |= ZSWR4_ONESB; 1105 if (!(cflag & PARODD)) 1106 cdiv |= ZSWR4_EVENP; 1107 if (cflag & PARENB) 1108 cdiv |= ZSWR4_PARENB; 1109 1110 switch(cflag & CSIZE) { 1111 case CS5: 1112 tmp = ZSWR3_RX_5; 1113 tmp5 = ZSWR5_TX_5; 1114 break; 1115 case CS6: 1116 tmp = ZSWR3_RX_6; 1117 tmp5 = ZSWR5_TX_6; 1118 break; 1119 case CS7: 1120 tmp = ZSWR3_RX_7; 1121 tmp5 = ZSWR5_TX_7; 1122 break; 1123 case CS8: 1124 default: 1125 tmp = ZSWR3_RX_8; 1126 tmp5 = ZSWR5_TX_8; 1127 break; 1128 } 1129 tmp |= ZSWR3_RX_ENABLE; 1130 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1131 1132 /* 1133 * Block interrupts so that state will not 1134 * be altered until we are done setting it up. 1135 */ 1136 s = splzs(); 1137 cs->cs_preg[4] = cdiv; 1138 cs->cs_preg[11] = clkm; 1139 cs->cs_preg[12] = tcon; 1140 cs->cs_preg[13] = tcon >> 8; 1141 cs->cs_preg[14] = brgm; 1142 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1143 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1144 cs->cs_preg[10] = ZSWR10_NRZ; 1145 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1146 1147 /* 1148 * Output hardware flow control on the chip is horrendous: if 1149 * carrier detect drops, the receiver is disabled. Hence we 1150 * can only do this when the carrier is on. 1151 */ 1152 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1153 tmp |= ZSWR3_HFC; 1154 cs->cs_preg[3] = tmp; 1155 cs->cs_preg[5] = tmp5; 1156 1157 /* 1158 * If nothing is being transmitted, set up new current values, 1159 * else mark them as pending. 1160 */ 1161 if(cs->cs_heldchange == 0) { 1162 if (cs->cs_ttyp->t_state & TS_BUSY) { 1163 cs->cs_heldtbc = cs->cs_tbc; 1164 cs->cs_tbc = 0; 1165 cs->cs_heldchange = 1; 1166 } else { 1167 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1168 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1169 } 1170 } 1171 splx(s); 1172 return (0); 1173} 1174 1175/* 1176 * search for the best matching baudrate 1177 */ 1178static int 1179zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1180int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1181{ 1182 int bestdiff, bestbps, source; 1183 1184 bestdiff = bestbps = 0; 1185 unit = (unit & 1) << 2; 1186 for (source = 0; source < 4; ++source) { 1187 long freq = zs_frequencies[unit + source]; 1188 int diff, bps, div, clkm, brgm, tcon; 1189 1190 bps = div = clkm = brgm = tcon = 0; 1191 switch (source) { 1192 case 0: /* BRgen, PCLK */ 1193 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1194 break; 1195 case 1: /* BRgen, RTxC */ 1196 brgm = ZSWR14_BAUD_ENA; 1197 break; 1198 case 2: /* RTxC */ 1199 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1200 break; 1201 case 3: /* TRxC */ 1202 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1203 break; 1204 } 1205 switch (source) { 1206 case 0: 1207 case 1: 1208 div = ZSWR4_CLK_X16; 1209 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1210 tcon = BPS_TO_TCONST(freq, wanted); 1211 if (tcon < 0) 1212 tcon = 0; 1213 bps = TCONST_TO_BPS(freq, tcon); 1214 break; 1215 case 2: 1216 case 3: 1217 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1218 int b2 = freq / 32, d2 = abs(b2 - wanted); 1219 int b3 = freq / 64, d3 = abs(b3 - wanted); 1220 1221 if (d1 < d2 && d1 < d3) { 1222 div = ZSWR4_CLK_X16; 1223 bps = b1; 1224 } else if (d2 < d3 && d2 < d1) { 1225 div = ZSWR4_CLK_X32; 1226 bps = b2; 1227 } else { 1228 div = ZSWR4_CLK_X64; 1229 bps = b3; 1230 } 1231 brgm = tcon = 0; 1232 break; 1233 } 1234 } 1235 diff = abs(bps - wanted); 1236 if (!source || diff < bestdiff) { 1237 *divisor = div; 1238 *clockmode = clkm; 1239 *brgenmode = brgm; 1240 *timeconst = tcon; 1241 bestbps = bps; 1242 bestdiff = diff; 1243 if (diff == 0) 1244 break; 1245 } 1246 } 1247 /* Allow deviations upto 5% */ 1248 if (20 * bestdiff > wanted) 1249 return -1; 1250 return bestbps; 1251} 1252 1253/* 1254 * Raise or lower modem control (DTR/RTS) signals. If a character is 1255 * in transmission, the change is deferred. 1256 */ 1257static int 1258zs_modem(cs, bits, how) 1259struct zs_chanstate *cs; 1260int bits, how; 1261{ 1262 int s, mbits; 1263 1264 bits &= ZSWR5_DTR | ZSWR5_RTS; 1265 1266 s = splzs(); 1267 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1268 1269 switch(how) { 1270 case DMSET: 1271 mbits = bits; 1272 break; 1273 case DMBIS: 1274 mbits |= bits; 1275 break; 1276 case DMBIC: 1277 mbits &= ~bits; 1278 break; 1279 case DMGET: 1280 splx(s); 1281 return(mbits); 1282 } 1283 1284 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1285 if(cs->cs_heldchange == 0) { 1286 if(cs->cs_ttyp->t_state & TS_BUSY) { 1287 cs->cs_heldtbc = cs->cs_tbc; 1288 cs->cs_tbc = 0; 1289 cs->cs_heldchange = 1; 1290 } 1291 else { 1292 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1293 } 1294 } 1295 splx(s); 1296 return(0); 1297} 1298 1299/* 1300 * Write the given register set to the given zs channel in the proper order. 1301 * The channel must not be transmitting at the time. The receiver will 1302 * be disabled for the time it takes to write all the registers. 1303 */ 1304static void 1305zs_loadchannelregs(zc, reg) 1306volatile struct zschan *zc; 1307u_char *reg; 1308{ 1309 int i; 1310 1311 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1312 i = zc->zc_data; /* drain fifo */ 1313 i = zc->zc_data; 1314 i = zc->zc_data; 1315 ZS_WRITE(zc, 4, reg[4]); 1316 ZS_WRITE(zc, 10, reg[10]); 1317 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1318 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1319 ZS_WRITE(zc, 1, reg[1]); 1320 ZS_WRITE(zc, 9, reg[9]); 1321 ZS_WRITE(zc, 11, reg[11]); 1322 ZS_WRITE(zc, 12, reg[12]); 1323 ZS_WRITE(zc, 13, reg[13]); 1324 ZS_WRITE(zc, 14, reg[14]); 1325 ZS_WRITE(zc, 15, reg[15]); 1326 ZS_WRITE(zc, 3, reg[3]); 1327 ZS_WRITE(zc, 5, reg[5]); 1328} 1329#endif /* NZS > 1 */ 1330