zs.c revision 1.28
1/* $NetBSD: zs.c,v 1.28 1998/01/12 18:04:17 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49/* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/proc.h> 59#include <sys/device.h> 60#include <sys/conf.h> 61#include <sys/file.h> 62#include <sys/ioctl.h> 63#include <sys/malloc.h> 64#include <sys/tty.h> 65#include <sys/time.h> 66#include <sys/kernel.h> 67#include <sys/syslog.h> 68 69#include <machine/cpu.h> 70#include <machine/iomap.h> 71#include <machine/scu.h> 72#include <machine/mfp.h> 73#include <atari/dev/ym2149reg.h> 74 75#include <dev/ic/z8530reg.h> 76#include <atari/dev/zsvar.h> 77#include "zs.h" 78#if NZS > 1 79#error "This driver supports only 1 85C30!" 80#endif 81 82#if NZS > 0 83 84#define PCLK (8053976) /* PCLK pin input clock rate */ 85#define PCLK_HD (14745600) /* PCLK on Hades pin input clock rate */ 86 87#define splzs spl5 88 89/* 90 * Software state per found chip. 91 */ 92struct zs_softc { 93 struct device zi_dev; /* base device */ 94 volatile struct zsdevice *zi_zs; /* chip registers */ 95 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 96}; 97 98static u_char cb_scheduled = 0; /* Already asked for callback? */ 99/* 100 * Define the registers for a closed port 101 */ 102static u_char zs_init_regs[16] = { 103/* 0 */ 0, 104/* 1 */ 0, 105/* 2 */ 0x60, 106/* 3 */ 0, 107/* 4 */ 0, 108/* 5 */ 0, 109/* 6 */ 0, 110/* 7 */ 0, 111/* 8 */ 0, 112/* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 113/* 10 */ ZSWR10_NRZ, 114/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115/* 12 */ 0, 116/* 13 */ 0, 117/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 118/* 15 */ 0 119}; 120 121/* 122 * Define the machine dependant clock frequencies 123 * If BRgen feeds sender/receiver we always use a 124 * divisor 16, therefor the division by 16 can as 125 * well be done here. 126 */ 127static u_long zs_freqs_tt[] = { 128 /* 129 * Atari TT, RTxCB is generated by TT-MFP timer C, 130 * which is set to 307.2KHz during initialisation 131 * and never changed afterwards. 132 */ 133 PCLK/16, /* BRgen, PCLK, divisor 16 */ 134 229500, /* BRgen, RTxCA, divisor 16 */ 135 3672000, /* RTxCA, from PCLK4 */ 136 0, /* TRxCA, external */ 137 138 PCLK/16, /* BRgen, PCLK, divisor 16 */ 139 19200, /* BRgen, RTxCB, divisor 16 */ 140 307200, /* RTxCB, from TT-MFP TCO */ 141 2457600 /* TRxCB, from BCLK */ 142}; 143 144static u_long zs_freqs_falcon[] = { 145 /* 146 * Atari Falcon, XXX no specs available, this might be wrong 147 */ 148 PCLK/16, /* BRgen, PCLK, divisor 16 */ 149 229500, /* BRgen, RTxCA, divisor 16 */ 150 3672000, /* RTxCA, ??? */ 151 0, /* TRxCA, external */ 152 153 PCLK/16, /* BRgen, PCLK, divisor 16 */ 154 229500, /* BRgen, RTxCB, divisor 16 */ 155 3672000, /* RTxCB, ??? */ 156 2457600 /* TRxCB, ??? */ 157}; 158 159static u_long zs_freqs_hades[] = { 160 /* 161 * XXX: Channel-A unchecked!!!!! 162 */ 163 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 164 229500, /* BRgen, RTxCA, divisor 16 */ 165 3672000, /* RTxCA, from PCLK4 */ 166 0, /* TRxCA, external */ 167 168 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 169 235550, /* BRgen, RTxCB, divisor 16 */ 170 3768800, /* RTxCB, 3.7688MHz */ 171 3768800 /* TRxCB, 3.7688MHz */ 172}; 173 174static u_long zs_freqs_generic[] = { 175 /* 176 * other machines, assume only PCLK is available 177 */ 178 PCLK/16, /* BRgen, PCLK, divisor 16 */ 179 0, /* BRgen, RTxCA, divisor 16 */ 180 0, /* RTxCA, unknown */ 181 0, /* TRxCA, unknown */ 182 183 PCLK/16, /* BRgen, PCLK, divisor 16 */ 184 0, /* BRgen, RTxCB, divisor 16 */ 185 0, /* RTxCB, unknown */ 186 0 /* TRxCB, unknown */ 187}; 188static u_long *zs_frequencies; 189 190/* Definition of the driver for autoconfig. */ 191static int zsmatch __P((struct device *, struct cfdata *, void *)); 192static void zsattach __P((struct device *, struct device *, void *)); 193 194struct cfattach zs_ca = { 195 sizeof(struct zs_softc), zsmatch, zsattach 196}; 197 198extern struct cfdriver zs_cd; 199 200/* {b,c}devsw[] function prototypes */ 201dev_type_open(zsopen); 202dev_type_close(zsclose); 203dev_type_read(zsread); 204dev_type_write(zswrite); 205dev_type_ioctl(zsioctl); 206dev_type_tty(zstty); 207 208/* Interrupt handlers. */ 209int zshard __P((long)); 210static int zssoft __P((long)); 211static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 212static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 213static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 214 215static struct zs_chanstate *zslist; 216 217/* Routines called from other code. */ 218static void zsstart __P((struct tty *)); 219void zsstop __P((struct tty *, int)); 220 221/* Routines purely local to this driver. */ 222static void zsoverrun __P((int, long *, char *)); 223static int zsparam __P((struct tty *, struct termios *)); 224static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 225static int zs_modem __P((struct zs_chanstate *, int, int)); 226static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 227 228static int zsshortcuts; /* number of "shortcut" software interrupts */ 229 230static int 231zsmatch(pdp, cfp, auxp) 232struct device *pdp; 233struct cfdata *cfp; 234void *auxp; 235{ 236 if(strcmp("zs", auxp) || cfp->cf_unit != 0) 237 return(0); 238 return(1); 239} 240 241/* 242 * Attach a found zs. 243 */ 244static void 245zsattach(parent, dev, aux) 246struct device *parent; 247struct device *dev; 248void *aux; 249{ 250 register struct zs_softc *zi; 251 register struct zs_chanstate *cs; 252 register volatile struct zsdevice *addr; 253 char tmp; 254 255 addr = (struct zsdevice *)AD_SCC; 256 zi = (struct zs_softc *)dev; 257 zi->zi_zs = addr; 258 cs = zi->zi_cs; 259 260 /* 261 * Get the command register into a known state. 262 */ 263 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 264 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 265 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 266 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 267 268 /* 269 * Do a hardware reset. 270 */ 271 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 272 delay(50000); /*enough ? */ 273 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 274 275 /* 276 * Initialize both channels 277 */ 278 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 279 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 280 281 if(machineid & ATARI_TT) { 282 /* 283 * ininitialise TT-MFP timer C: 307200Hz 284 * timer C and D share one control register: 285 * bits 0-2 control timer D 286 * bits 4-6 control timer C 287 */ 288 int cr = MFP2->mf_tcdcr & 7; 289 MFP2->mf_tcdcr = cr; /* stop timer C */ 290 MFP2->mf_tcdr = 1; /* counter 1 */ 291 cr |= T_Q004 << 4; /* divisor 4 */ 292 MFP2->mf_tcdcr = cr; /* start timer C */ 293 /* 294 * enable scc related interrupts 295 */ 296 SCU->vme_mask |= SCU_SCC; 297 298 zs_frequencies = zs_freqs_tt; 299 } else if (machineid & ATARI_FALCON) { 300 zs_frequencies = zs_freqs_falcon; 301 } else if (machineid & ATARI_HADES) { 302 zs_frequencies = zs_freqs_hades; 303 } else { 304 zs_frequencies = zs_freqs_generic; 305 } 306 307 /* link into interrupt list with order (A,B) (B=A+1) */ 308 cs[0].cs_next = &cs[1]; 309 cs[1].cs_next = zslist; 310 zslist = cs; 311 312 cs->cs_unit = 0; 313 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 314 cs++; 315 cs->cs_unit = 1; 316 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 317 318 printf(": serial2 on channel a and modem2 on channel b\n"); 319} 320 321/* 322 * Open a zs serial port. 323 */ 324int 325zsopen(dev, flags, mode, p) 326dev_t dev; 327int flags; 328int mode; 329struct proc *p; 330{ 331 register struct tty *tp; 332 register struct zs_chanstate *cs; 333 struct zs_softc *zi; 334 int unit = ZS_UNIT(dev); 335 int zs = unit >> 1; 336 int error, s; 337 338 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 339 return (ENXIO); 340 cs = &zi->zi_cs[unit & 1]; 341 342 /* 343 * When port A (ser02) is selected on the TT, make sure 344 * the port is enabled. 345 */ 346 if((machineid & ATARI_TT) && !(unit & 1)) 347 ym2149_ser2(1); 348 349 if (cs->cs_rbuf == NULL) { 350 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 351 M_WAITOK); 352 } 353 354 tp = cs->cs_ttyp; 355 if(tp == NULL) { 356 cs->cs_ttyp = tp = ttymalloc(); 357 tty_attach(tp); 358 tp->t_dev = dev; 359 tp->t_oproc = zsstart; 360 tp->t_param = zsparam; 361 } 362 363 s = spltty(); 364 if((tp->t_state & TS_ISOPEN) == 0) { 365 ttychars(tp); 366 if(tp->t_ispeed == 0) { 367 tp->t_iflag = TTYDEF_IFLAG; 368 tp->t_oflag = TTYDEF_OFLAG; 369 tp->t_cflag = TTYDEF_CFLAG; 370 tp->t_lflag = TTYDEF_LFLAG; 371 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 372 } 373 (void)zsparam(tp, &tp->t_termios); 374 ttsetwater(tp); 375 } 376 else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 377 splx(s); 378 return (EBUSY); 379 } 380 error = 0; 381 for(;;) { 382 /* loop, turning on the device, until carrier present */ 383 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 384 385 /* May never get a status intr. if DCD already on. -gwr */ 386 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 387 tp->t_state |= TS_CARR_ON; 388 if(cs->cs_softcar) 389 tp->t_state |= TS_CARR_ON; 390 if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL || 391 tp->t_state & TS_CARR_ON) 392 break; 393 tp->t_state |= TS_WOPEN; 394 if((error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH, 395 ttopen, 0)) != 0) { 396 if(!(tp->t_state & TS_ISOPEN)) { 397 zs_modem(cs, 0, DMSET); 398 tp->t_state &= ~TS_WOPEN; 399 ttwakeup(tp); 400 } 401 splx(s); 402 return error; 403 } 404 } 405 splx(s); 406 if(error == 0) 407 error = linesw[tp->t_line].l_open(dev, tp); 408 if(error) 409 zs_modem(cs, 0, DMSET); 410 return(error); 411} 412 413/* 414 * Close a zs serial port. 415 */ 416int 417zsclose(dev, flags, mode, p) 418dev_t dev; 419int flags; 420int mode; 421struct proc *p; 422{ 423 register struct zs_chanstate *cs; 424 register struct tty *tp; 425 struct zs_softc *zi; 426 int unit = ZS_UNIT(dev); 427 int s; 428 429 zi = zs_cd.cd_devs[unit >> 1]; 430 cs = &zi->zi_cs[unit & 1]; 431 tp = cs->cs_ttyp; 432 linesw[tp->t_line].l_close(tp, flags); 433 if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN || 434 (tp->t_state & TS_ISOPEN) == 0) { 435 zs_modem(cs, 0, DMSET); 436 /* hold low for 1 second */ 437 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 438 } 439 if(cs->cs_creg[5] & ZSWR5_BREAK) { 440 s = splzs(); 441 cs->cs_preg[5] &= ~ZSWR5_BREAK; 442 cs->cs_creg[5] &= ~ZSWR5_BREAK; 443 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 444 splx(s); 445 } 446 ttyclose(tp); 447 448 /* 449 * Drop all lines and cancel interrupts 450 */ 451 s = splzs(); 452 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 453 splx(s); 454 return (0); 455} 456 457/* 458 * Read/write zs serial port. 459 */ 460int 461zsread(dev, uio, flags) 462dev_t dev; 463struct uio *uio; 464int flags; 465{ 466 register struct zs_chanstate *cs; 467 register struct zs_softc *zi; 468 register struct tty *tp; 469 int unit; 470 471 unit = ZS_UNIT(dev); 472 zi = zs_cd.cd_devs[unit >> 1]; 473 cs = &zi->zi_cs[unit & 1]; 474 tp = cs->cs_ttyp; 475 476 return(linesw[tp->t_line].l_read(tp, uio, flags)); 477} 478 479int 480zswrite(dev, uio, flags) 481dev_t dev; 482struct uio *uio; 483int flags; 484{ 485 register struct zs_chanstate *cs; 486 register struct zs_softc *zi; 487 register struct tty *tp; 488 int unit; 489 490 unit = ZS_UNIT(dev); 491 zi = zs_cd.cd_devs[unit >> 1]; 492 cs = &zi->zi_cs[unit & 1]; 493 tp = cs->cs_ttyp; 494 495 return(linesw[tp->t_line].l_write(tp, uio, flags)); 496} 497 498struct tty * 499zstty(dev) 500dev_t dev; 501{ 502 register struct zs_chanstate *cs; 503 register struct zs_softc *zi; 504 int unit; 505 506 unit = ZS_UNIT(dev); 507 zi = zs_cd.cd_devs[unit >> 1]; 508 cs = &zi->zi_cs[unit & 1]; 509 return(cs->cs_ttyp); 510} 511 512/* 513 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 514 * channels are kept in (A,B) pairs. 515 * 516 * Do just a little, then get out; set a software interrupt if more 517 * work is needed. 518 * 519 * We deliberately ignore the vectoring Zilog gives us, and match up 520 * only the number of `reset interrupt under service' operations, not 521 * the order. 522 */ 523 524int 525zshard(sr) 526long sr; 527{ 528 register struct zs_chanstate *a; 529#define b (a + 1) 530 register volatile struct zschan *zc; 531 register int rr3, intflags = 0, v, i; 532 533 do { 534 intflags &= ~4; 535 for(a = zslist; a != NULL; a = b->cs_next) { 536 rr3 = ZS_READ(a->cs_zc, 3); 537 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 538 intflags |= 4|2; 539 zc = a->cs_zc; 540 i = a->cs_rbput; 541 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 542 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 543 intflags |= 1; 544 } 545 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 546 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 547 intflags |= 1; 548 } 549 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 550 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 551 intflags |= 1; 552 } 553 a->cs_rbput = i; 554 } 555 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 556 intflags |= 4|2; 557 zc = b->cs_zc; 558 i = b->cs_rbput; 559 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 560 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 561 intflags |= 1; 562 } 563 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 564 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 565 intflags |= 1; 566 } 567 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 568 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 569 intflags |= 1; 570 } 571 b->cs_rbput = i; 572 } 573 } 574 } while(intflags & 4); 575#undef b 576 577 if(intflags & 1) { 578 if(BASEPRI(sr)) { 579 spl1(); 580 zsshortcuts++; 581 return(zssoft(sr)); 582 } 583 else if(!cb_scheduled) { 584 cb_scheduled++; 585 add_sicallback((si_farg)zssoft, 0, 0); 586 } 587 } 588 return(intflags & 2); 589} 590 591static int 592zsrint(cs, zc) 593register struct zs_chanstate *cs; 594register volatile struct zschan *zc; 595{ 596 register int c; 597 598 /* 599 * First read the status, because read of the received char 600 * destroy the status of this char. 601 */ 602 c = ZS_READ(zc, 1); 603 c |= (zc->zc_data << 8); 604 605 /* clear receive error & interrupt condition */ 606 zc->zc_csr = ZSWR0_RESET_ERRORS; 607 zc->zc_csr = ZSWR0_CLR_INTR; 608 609 return(ZRING_MAKE(ZRING_RINT, c)); 610} 611 612static int 613zsxint(cs, zc) 614register struct zs_chanstate *cs; 615register volatile struct zschan *zc; 616{ 617 register int i = cs->cs_tbc; 618 619 if(i == 0) { 620 zc->zc_csr = ZSWR0_RESET_TXINT; 621 zc->zc_csr = ZSWR0_CLR_INTR; 622 return(ZRING_MAKE(ZRING_XINT, 0)); 623 } 624 cs->cs_tbc = i - 1; 625 zc->zc_data = *cs->cs_tba++; 626 zc->zc_csr = ZSWR0_CLR_INTR; 627 return (0); 628} 629 630static int 631zssint(cs, zc) 632register struct zs_chanstate *cs; 633register volatile struct zschan *zc; 634{ 635 register int rr0; 636 637 rr0 = zc->zc_csr; 638 zc->zc_csr = ZSWR0_RESET_STATUS; 639 zc->zc_csr = ZSWR0_CLR_INTR; 640 /* 641 * The chip's hardware flow control is, as noted in zsreg.h, 642 * busted---if the DCD line goes low the chip shuts off the 643 * receiver (!). If we want hardware CTS flow control but do 644 * not have it, and carrier is now on, turn HFC on; if we have 645 * HFC now but carrier has gone low, turn it off. 646 */ 647 if(rr0 & ZSRR0_DCD) { 648 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 649 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 650 cs->cs_creg[3] |= ZSWR3_HFC; 651 ZS_WRITE(zc, 3, cs->cs_creg[3]); 652 } 653 } 654 else { 655 if (cs->cs_creg[3] & ZSWR3_HFC) { 656 cs->cs_creg[3] &= ~ZSWR3_HFC; 657 ZS_WRITE(zc, 3, cs->cs_creg[3]); 658 } 659 } 660 return(ZRING_MAKE(ZRING_SINT, rr0)); 661} 662 663/* 664 * Print out a ring or fifo overrun error message. 665 */ 666static void 667zsoverrun(unit, ptime, what) 668int unit; 669long *ptime; 670char *what; 671{ 672 673 if(*ptime != time.tv_sec) { 674 *ptime = time.tv_sec; 675 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 676 (unit & 1) + 'a', what); 677 } 678} 679 680/* 681 * ZS software interrupt. Scan all channels for deferred interrupts. 682 */ 683int 684zssoft(sr) 685long sr; 686{ 687 register struct zs_chanstate *cs; 688 register volatile struct zschan *zc; 689 register struct linesw *line; 690 register struct tty *tp; 691 register int get, n, c, cc, unit, s; 692 int retval = 0; 693 694 cb_scheduled = 0; 695 s = spltty(); 696 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 697 get = cs->cs_rbget; 698again: 699 n = cs->cs_rbput; /* atomic */ 700 if(get == n) /* nothing more on this line */ 701 continue; 702 retval = 1; 703 unit = cs->cs_unit; /* set up to handle interrupts */ 704 zc = cs->cs_zc; 705 tp = cs->cs_ttyp; 706 line = &linesw[tp->t_line]; 707 /* 708 * Compute the number of interrupts in the receive ring. 709 * If the count is overlarge, we lost some events, and 710 * must advance to the first valid one. It may get 711 * overwritten if more data are arriving, but this is 712 * too expensive to check and gains nothing (we already 713 * lost out; all we can do at this point is trade one 714 * kind of loss for another). 715 */ 716 n -= get; 717 if(n > ZLRB_RING_SIZE) { 718 zsoverrun(unit, &cs->cs_rotime, "ring"); 719 get += n - ZLRB_RING_SIZE; 720 n = ZLRB_RING_SIZE; 721 } 722 while(--n >= 0) { 723 /* race to keep ahead of incoming interrupts */ 724 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 725 switch (ZRING_TYPE(c)) { 726 727 case ZRING_RINT: 728 c = ZRING_VALUE(c); 729 if(c & ZSRR1_DO) 730 zsoverrun(unit, &cs->cs_fotime, "fifo"); 731 cc = c >> 8; 732 if(c & ZSRR1_FE) 733 cc |= TTY_FE; 734 if(c & ZSRR1_PE) 735 cc |= TTY_PE; 736 line->l_rint(cc, tp); 737 break; 738 739 case ZRING_XINT: 740 /* 741 * Transmit done: change registers and resume, 742 * or clear BUSY. 743 */ 744 if(cs->cs_heldchange) { 745 int sps; 746 747 sps = splzs(); 748 c = zc->zc_csr; 749 if((c & ZSRR0_DCD) == 0) 750 cs->cs_preg[3] &= ~ZSWR3_HFC; 751 bcopy((caddr_t)cs->cs_preg, 752 (caddr_t)cs->cs_creg, 16); 753 zs_loadchannelregs(zc, cs->cs_creg); 754 splx(sps); 755 cs->cs_heldchange = 0; 756 if(cs->cs_heldtbc 757 && (tp->t_state & TS_TTSTOP) == 0) { 758 cs->cs_tbc = cs->cs_heldtbc - 1; 759 zc->zc_data = *cs->cs_tba++; 760 goto again; 761 } 762 } 763 tp->t_state &= ~TS_BUSY; 764 if(tp->t_state & TS_FLUSH) 765 tp->t_state &= ~TS_FLUSH; 766 else ndflush(&tp->t_outq,cs->cs_tba 767 - (caddr_t)tp->t_outq.c_cf); 768 line->l_start(tp); 769 break; 770 771 case ZRING_SINT: 772 /* 773 * Status line change. HFC bit is run in 774 * hardware interrupt, to avoid locking 775 * at splzs here. 776 */ 777 c = ZRING_VALUE(c); 778 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 779 cc = (c & ZSRR0_DCD) != 0; 780 if(line->l_modem(tp, cc) == 0) 781 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 782 cc ? DMBIS : DMBIC); 783 } 784 cs->cs_rr0 = c; 785 break; 786 787 default: 788 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 789 unit >> 1, (unit & 1) + 'a', c); 790 break; 791 } 792 } 793 cs->cs_rbget = get; 794 goto again; 795 } 796 splx(s); 797 return (retval); 798} 799 800int 801zsioctl(dev, cmd, data, flag, p) 802dev_t dev; 803u_long cmd; 804caddr_t data; 805int flag; 806struct proc *p; 807{ 808 int unit = ZS_UNIT(dev); 809 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 810 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 811 register int error, s; 812 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 813 814 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 815 if(error >= 0) 816 return(error); 817 error = ttioctl(tp, cmd, data, flag, p); 818 if(error >= 0) 819 return (error); 820 821 switch (cmd) { 822 case TIOCSBRK: 823 s = splzs(); 824 cs->cs_preg[5] |= ZSWR5_BREAK; 825 cs->cs_creg[5] |= ZSWR5_BREAK; 826 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 827 splx(s); 828 break; 829 case TIOCCBRK: 830 s = splzs(); 831 cs->cs_preg[5] &= ~ZSWR5_BREAK; 832 cs->cs_creg[5] &= ~ZSWR5_BREAK; 833 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 834 splx(s); 835 break; 836 case TIOCGFLAGS: { 837 int bits = 0; 838 839 if(cs->cs_softcar) 840 bits |= TIOCFLAG_SOFTCAR; 841 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 842 bits |= TIOCFLAG_CLOCAL; 843 if(cs->cs_creg[3] & ZSWR3_HFC) 844 bits |= TIOCFLAG_CRTSCTS; 845 *(int *)data = bits; 846 break; 847 } 848 case TIOCSFLAGS: { 849 int userbits = 0; 850 851 error = suser(p->p_ucred, &p->p_acflag); 852 if(error != 0) 853 return (EPERM); 854 855 userbits = *(int *)data; 856 857 /* 858 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 859 # defaulting to software flow control. 860 */ 861 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 862 return(EINVAL); 863 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 864 return(ENODEV); 865 866 s = splzs(); 867 if((userbits & TIOCFLAG_SOFTCAR)) { 868 cs->cs_softcar = 1; /* turn on softcar */ 869 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 870 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 871 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 872 } 873 else if(userbits & TIOCFLAG_CLOCAL) { 874 cs->cs_softcar = 0; /* turn off softcar */ 875 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 876 cs->cs_creg[15] |= ZSWR15_DCD_IE; 877 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 878 tp->t_termios.c_cflag |= CLOCAL; 879 } 880 if(userbits & TIOCFLAG_CRTSCTS) { 881 cs->cs_preg[15] |= ZSWR15_CTS_IE; 882 cs->cs_creg[15] |= ZSWR15_CTS_IE; 883 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 884 cs->cs_preg[3] |= ZSWR3_HFC; 885 cs->cs_creg[3] |= ZSWR3_HFC; 886 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 887 tp->t_termios.c_cflag |= CRTSCTS; 888 } 889 else { 890 /* no mdmbuf, so we must want software flow control */ 891 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 892 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 893 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 894 cs->cs_preg[3] &= ~ZSWR3_HFC; 895 cs->cs_creg[3] &= ~ZSWR3_HFC; 896 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 897 tp->t_termios.c_cflag &= ~CRTSCTS; 898 } 899 splx(s); 900 break; 901 } 902 case TIOCSDTR: 903 zs_modem(cs, ZSWR5_DTR, DMBIS); 904 break; 905 case TIOCCDTR: 906 zs_modem(cs, ZSWR5_DTR, DMBIC); 907 break; 908 case TIOCMGET: 909 zs_modem(cs, 0, DMGET); 910 break; 911 case TIOCMSET: 912 case TIOCMBIS: 913 case TIOCMBIC: 914 default: 915 return (ENOTTY); 916 } 917 return (0); 918} 919 920/* 921 * Start or restart transmission. 922 */ 923static void 924zsstart(tp) 925register struct tty *tp; 926{ 927 register struct zs_chanstate *cs; 928 register int s, nch; 929 int unit = ZS_UNIT(tp->t_dev); 930 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 931 932 cs = &zi->zi_cs[unit & 1]; 933 s = spltty(); 934 935 /* 936 * If currently active or delaying, no need to do anything. 937 */ 938 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 939 goto out; 940 941 /* 942 * If there are sleepers, and output has drained below low 943 * water mark, awaken. 944 */ 945 if(tp->t_outq.c_cc <= tp->t_lowat) { 946 if(tp->t_state & TS_ASLEEP) { 947 tp->t_state &= ~TS_ASLEEP; 948 wakeup((caddr_t)&tp->t_outq); 949 } 950 selwakeup(&tp->t_wsel); 951 } 952 953 nch = ndqb(&tp->t_outq, 0); /* XXX */ 954 if(nch) { 955 register char *p = tp->t_outq.c_cf; 956 957 /* mark busy, enable tx done interrupts, & send first byte */ 958 tp->t_state |= TS_BUSY; 959 (void) splzs(); 960 cs->cs_preg[1] |= ZSWR1_TIE; 961 cs->cs_creg[1] |= ZSWR1_TIE; 962 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 963 cs->cs_zc->zc_data = *p; 964 cs->cs_tba = p + 1; 965 cs->cs_tbc = nch - 1; 966 } else { 967 /* 968 * Nothing to send, turn off transmit done interrupts. 969 * This is useful if something is doing polled output. 970 */ 971 (void) splzs(); 972 cs->cs_preg[1] &= ~ZSWR1_TIE; 973 cs->cs_creg[1] &= ~ZSWR1_TIE; 974 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 975 } 976out: 977 splx(s); 978} 979 980/* 981 * Stop output, e.g., for ^S or output flush. 982 */ 983void 984zsstop(tp, flag) 985register struct tty *tp; 986 int flag; 987{ 988 register struct zs_chanstate *cs; 989 register int s, unit = ZS_UNIT(tp->t_dev); 990 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 991 992 cs = &zi->zi_cs[unit & 1]; 993 s = splzs(); 994 if(tp->t_state & TS_BUSY) { 995 /* 996 * Device is transmitting; must stop it. 997 */ 998 cs->cs_tbc = 0; 999 if ((tp->t_state & TS_TTSTOP) == 0) 1000 tp->t_state |= TS_FLUSH; 1001 } 1002 splx(s); 1003} 1004 1005/* 1006 * Set ZS tty parameters from termios. 1007 * 1008 * This routine makes use of the fact that only registers 1009 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1010 */ 1011static int 1012zsparam(tp, t) 1013register struct tty *tp; 1014register struct termios *t; 1015{ 1016 int unit = ZS_UNIT(tp->t_dev); 1017 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1018 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1019 int cdiv, clkm, brgm, tcon; 1020 register int tmp, tmp5, cflag, s; 1021 1022 tmp = t->c_ospeed; 1023 tmp5 = t->c_ispeed; 1024 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1025 return(EINVAL); 1026 if(tmp == 0) { 1027 /* stty 0 => drop DTR and RTS */ 1028 zs_modem(cs, 0, DMSET); 1029 return(0); 1030 } 1031 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1032 if (tmp < 0) 1033 return(EINVAL); 1034 tp->t_ispeed = tp->t_ospeed = tmp; 1035 1036 cflag = tp->t_cflag = t->c_cflag; 1037 if (cflag & CSTOPB) 1038 cdiv |= ZSWR4_TWOSB; 1039 else 1040 cdiv |= ZSWR4_ONESB; 1041 if (!(cflag & PARODD)) 1042 cdiv |= ZSWR4_EVENP; 1043 if (cflag & PARENB) 1044 cdiv |= ZSWR4_PARENB; 1045 1046 switch(cflag & CSIZE) { 1047 case CS5: 1048 tmp = ZSWR3_RX_5; 1049 tmp5 = ZSWR5_TX_5; 1050 break; 1051 case CS6: 1052 tmp = ZSWR3_RX_6; 1053 tmp5 = ZSWR5_TX_6; 1054 break; 1055 case CS7: 1056 tmp = ZSWR3_RX_7; 1057 tmp5 = ZSWR5_TX_7; 1058 break; 1059 case CS8: 1060 default: 1061 tmp = ZSWR3_RX_8; 1062 tmp5 = ZSWR5_TX_8; 1063 break; 1064 } 1065 tmp |= ZSWR3_RX_ENABLE; 1066 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1067 1068 /* 1069 * Block interrupts so that state will not 1070 * be altered until we are done setting it up. 1071 */ 1072 s = splzs(); 1073 cs->cs_preg[4] = cdiv; 1074 cs->cs_preg[11] = clkm; 1075 cs->cs_preg[12] = tcon; 1076 cs->cs_preg[13] = tcon >> 8; 1077 cs->cs_preg[14] = brgm; 1078 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1079 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1080 cs->cs_preg[10] = ZSWR10_NRZ; 1081 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1082 1083 /* 1084 * Output hardware flow control on the chip is horrendous: if 1085 * carrier detect drops, the receiver is disabled. Hence we 1086 * can only do this when the carrier is on. 1087 */ 1088 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1089 tmp |= ZSWR3_HFC; 1090 cs->cs_preg[3] = tmp; 1091 cs->cs_preg[5] = tmp5; 1092 1093 /* 1094 * If nothing is being transmitted, set up new current values, 1095 * else mark them as pending. 1096 */ 1097 if(cs->cs_heldchange == 0) { 1098 if (cs->cs_ttyp->t_state & TS_BUSY) { 1099 cs->cs_heldtbc = cs->cs_tbc; 1100 cs->cs_tbc = 0; 1101 cs->cs_heldchange = 1; 1102 } else { 1103 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1104 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1105 } 1106 } 1107 splx(s); 1108 return (0); 1109} 1110 1111/* 1112 * search for the best matching baudrate 1113 */ 1114static int 1115zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1116int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1117{ 1118 int bestdiff, bestbps, source; 1119 1120 bestdiff = bestbps = 0; 1121 unit = (unit & 1) << 2; 1122 for (source = 0; source < 4; ++source) { 1123 long freq = zs_frequencies[unit + source]; 1124 int diff, bps, div, clkm, brgm, tcon; 1125 1126 bps = div = clkm = brgm = tcon = 0; 1127 switch (source) { 1128 case 0: /* BRgen, PCLK */ 1129 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1130 break; 1131 case 1: /* BRgen, RTxC */ 1132 brgm = ZSWR14_BAUD_ENA; 1133 break; 1134 case 2: /* RTxC */ 1135 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1136 break; 1137 case 3: /* TRxC */ 1138 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1139 break; 1140 } 1141 switch (source) { 1142 case 0: 1143 case 1: 1144 div = ZSWR4_CLK_X16; 1145 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1146 tcon = BPS_TO_TCONST(freq, wanted); 1147 if (tcon < 0) 1148 tcon = 0; 1149 bps = TCONST_TO_BPS(freq, tcon); 1150 break; 1151 case 2: 1152 case 3: 1153 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1154 int b2 = freq / 32, d2 = abs(b2 - wanted); 1155 int b3 = freq / 64, d3 = abs(b3 - wanted); 1156 1157 if (d1 < d2 && d1 < d3) { 1158 div = ZSWR4_CLK_X16; 1159 bps = b1; 1160 } else if (d2 < d3 && d2 < d1) { 1161 div = ZSWR4_CLK_X32; 1162 bps = b2; 1163 } else { 1164 div = ZSWR4_CLK_X64; 1165 bps = b3; 1166 } 1167 brgm = tcon = 0; 1168 break; 1169 } 1170 } 1171 diff = abs(bps - wanted); 1172 if (!source || diff < bestdiff) { 1173 *divisor = div; 1174 *clockmode = clkm; 1175 *brgenmode = brgm; 1176 *timeconst = tcon; 1177 bestbps = bps; 1178 bestdiff = diff; 1179 if (diff == 0) 1180 break; 1181 } 1182 } 1183 /* Allow deviations upto 5% */ 1184 if (20 * bestdiff > wanted) 1185 return -1; 1186 return bestbps; 1187} 1188 1189/* 1190 * Raise or lower modem control (DTR/RTS) signals. If a character is 1191 * in transmission, the change is deferred. 1192 */ 1193static int 1194zs_modem(cs, bits, how) 1195struct zs_chanstate *cs; 1196int bits, how; 1197{ 1198 int s, mbits; 1199 1200 bits &= ZSWR5_DTR | ZSWR5_RTS; 1201 1202 s = splzs(); 1203 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1204 1205 switch(how) { 1206 case DMSET: 1207 mbits = bits; 1208 break; 1209 case DMBIS: 1210 mbits |= bits; 1211 break; 1212 case DMBIC: 1213 mbits &= ~bits; 1214 break; 1215 case DMGET: 1216 splx(s); 1217 return(mbits); 1218 } 1219 1220 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1221 if(cs->cs_heldchange == 0) { 1222 if(cs->cs_ttyp->t_state & TS_BUSY) { 1223 cs->cs_heldtbc = cs->cs_tbc; 1224 cs->cs_tbc = 0; 1225 cs->cs_heldchange = 1; 1226 } 1227 else { 1228 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1229 } 1230 } 1231 splx(s); 1232 return(0); 1233} 1234 1235/* 1236 * Write the given register set to the given zs channel in the proper order. 1237 * The channel must not be transmitting at the time. The receiver will 1238 * be disabled for the time it takes to write all the registers. 1239 */ 1240static void 1241zs_loadchannelregs(zc, reg) 1242volatile struct zschan *zc; 1243u_char *reg; 1244{ 1245 int i; 1246 1247 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1248 i = zc->zc_data; /* drain fifo */ 1249 i = zc->zc_data; 1250 i = zc->zc_data; 1251 ZS_WRITE(zc, 4, reg[4]); 1252 ZS_WRITE(zc, 10, reg[10]); 1253 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1254 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1255 ZS_WRITE(zc, 1, reg[1]); 1256 ZS_WRITE(zc, 9, reg[9]); 1257 ZS_WRITE(zc, 11, reg[11]); 1258 ZS_WRITE(zc, 12, reg[12]); 1259 ZS_WRITE(zc, 13, reg[13]); 1260 ZS_WRITE(zc, 14, reg[14]); 1261 ZS_WRITE(zc, 15, reg[15]); 1262 ZS_WRITE(zc, 3, reg[3]); 1263 ZS_WRITE(zc, 5, reg[5]); 1264} 1265#endif /* NZS > 1 */ 1266