zs.c revision 1.25 
1/*	$NetBSD: zs.c,v 1.25 1996/12/20 12:49:45 leo Exp $	*/
2
3/*
4 * Copyright (c) 1995 L. Weppelman (Atari modifications)
5 * Copyright (c) 1992, 1993
6 *	The Regents of the University of California.  All rights reserved.
7 *
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
11 *
12 *
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Lawrence Berkeley Laboratory.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 *    notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 *    notice, this list of conditions and the following disclaimer in the
25 *    documentation and/or other materials provided with the distribution.
26 * 3. All advertising materials mentioning features or use of this software
27 *    must display the following acknowledgement:
28 *	This product includes software developed by the University of
29 *	California, Berkeley and its contributors.
30 * 4. Neither the name of the University nor the names of its contributors
31 *    may be used to endorse or promote products derived from this software
32 *    without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
44 * SUCH DAMAGE.
45 *
46 *	@(#)zs.c	8.1 (Berkeley) 7/19/93
47 */
48
49/*
50 * Zilog Z8530 (ZSCC) driver.
51 *
52 * Runs two tty ports (modem2 and serial2) on zs0.
53 *
54 * This driver knows far too much about chip to usage mappings.
55 */
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/proc.h>
59#include <sys/device.h>
60#include <sys/conf.h>
61#include <sys/file.h>
62#include <sys/ioctl.h>
63#include <sys/malloc.h>
64#include <sys/tty.h>
65#include <sys/time.h>
66#include <sys/kernel.h>
67#include <sys/syslog.h>
68
69#include <machine/cpu.h>
70#include <machine/iomap.h>
71#include <machine/scu.h>
72#include <machine/mfp.h>
73#include <atari/dev/ym2149reg.h>
74
75#include <dev/ic/z8530reg.h>
76#include <atari/dev/zsvar.h>
77#include "zs.h"
78#if NZS > 1
79#error "This driver supports only 1 85C30!"
80#endif
81
82#if NZS > 0
83
84#define PCLK	(8053976)	/* PCLK pin input clock rate */
85#define PCLK_HD	(14745600)	/* PCLK on Hades pin input clock rate */
86
87#define splzs	spl5
88
89/*
90 * Software state per found chip.
91 */
92struct zs_softc {
93    struct	device		zi_dev;    /* base device		  */
94    volatile struct zsdevice	*zi_zs;    /* chip registers		  */
95    struct	zs_chanstate	zi_cs[2];  /* chan A and B software state */
96};
97
98static u_char	cb_scheduled = 0;	/* Already asked for callback? */
99/*
100 * Define the registers for a closed port
101 */
102static u_char zs_init_regs[16] = {
103/*  0 */	0,
104/*  1 */	0,
105/*  2 */	0x60,
106/*  3 */	0,
107/*  4 */	0,
108/*  5 */	0,
109/*  6 */	0,
110/*  7 */	0,
111/*  8 */	0,
112/*  9 */	ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT,
113/* 10 */	ZSWR10_NRZ,
114/* 11 */	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
115/* 12 */	0,
116/* 13 */	0,
117/* 14 */	ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA,
118/* 15 */	0
119};
120
121/*
122 * Define the machine dependant clock frequencies
123 * If BRgen feeds sender/receiver we always use a
124 * divisor 16, therefor the division by 16 can as
125 * well be done here.
126 */
127static u_long zs_freqs_tt[] = {
128	/*
129	 * Atari TT, RTxCB is generated by TT-MFP timer C,
130	 * which is set to 307.2KHz during initialisation
131	 * and never changed afterwards.
132	 */
133	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
134	 229500,	/* BRgen, RTxCA, divisor 16	*/
135	3672000,	/* RTxCA, from PCLK4		*/
136	      0,	/* TRxCA, external		*/
137
138	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
139	  19200,	/* BRgen, RTxCB, divisor 16	*/
140	 307200,	/* RTxCB, from TT-MFP TCO	*/
141	2457600		/* TRxCB, from BCLK		*/
142};
143
144static u_long zs_freqs_falcon[] = {
145	/*
146	 * Atari Falcon, XXX no specs available, this might be wrong
147	 */
148	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
149	 229500,	/* BRgen, RTxCA, divisor 16	*/
150	3672000,	/* RTxCA, ???			*/
151	      0,	/* TRxCA, external		*/
152
153	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
154	 229500,	/* BRgen, RTxCB, divisor 16	*/
155	3672000,	/* RTxCB, ???			*/
156	2457600		/* TRxCB, ???			*/
157};
158
159static u_long zs_freqs_hades[] = {
160	/*
161	 * XXX: Channel-A unchecked!!!!!
162	 */
163     PCLK_HD/16,	/* BRgen, PCLK,  divisor 16	*/
164	 229500,	/* BRgen, RTxCA, divisor 16	*/
165	3672000,	/* RTxCA, from PCLK4		*/
166	      0,	/* TRxCA, external		*/
167
168     PCLK_HD/16,	/* BRgen, PCLK,  divisor 16	*/
169	 235550,	/* BRgen, RTxCB, divisor 16	*/
170	3768800,	/* RTxCB, 3.7688MHz		*/
171	3768800		/* TRxCB, 3.7688MHz		*/
172};
173
174static u_long zs_freqs_generic[] = {
175	/*
176	 * other machines, assume only PCLK is available
177	 */
178	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
179	      0,	/* BRgen, RTxCA, divisor 16	*/
180	      0,	/* RTxCA, unknown		*/
181	      0,	/* TRxCA, unknown		*/
182
183	PCLK/16,	/* BRgen, PCLK,  divisor 16	*/
184	      0,	/* BRgen, RTxCB, divisor 16	*/
185	      0,	/* RTxCB, unknown		*/
186	      0		/* TRxCB, unknown		*/
187};
188static u_long *zs_frequencies;
189
190/* Definition of the driver for autoconfig. */
191static int	zsmatch __P((struct device *, struct cfdata *, void *));
192static void	zsattach __P((struct device *, struct device *, void *));
193
194struct cfattach zs_ca = {
195	sizeof(struct zs_softc), zsmatch, zsattach
196};
197
198struct cfdriver zs_cd = {
199	NULL, "zs", DV_TTY, NULL, 0
200};
201
202/* {b,c}devsw[] function prototypes */
203dev_type_open(zsopen);
204dev_type_close(zsclose);
205dev_type_read(zsread);
206dev_type_write(zswrite);
207dev_type_ioctl(zsioctl);
208dev_type_tty(zstty);
209
210/* Interrupt handlers. */
211int		zshard __P((long));
212static int	zssoft __P((long));
213static int	zsrint __P((struct zs_chanstate *, volatile struct zschan *));
214static int	zsxint __P((struct zs_chanstate *, volatile struct zschan *));
215static int	zssint __P((struct zs_chanstate *, volatile struct zschan *));
216
217static struct zs_chanstate *zslist;
218
219/* Routines called from other code. */
220static void	zsstart __P((struct tty *));
221void		zsstop __P((struct tty *, int));
222
223/* Routines purely local to this driver. */
224static void	zsoverrun __P((int, long *, char *));
225static int	zsparam __P((struct tty *, struct termios *));
226static int	zsbaudrate __P((int, int, int *, int *, int *, int *));
227static int	zs_modem __P((struct zs_chanstate *, int, int));
228static void	zs_loadchannelregs __P((volatile struct zschan *, u_char *));
229
230static int zsshortcuts;	/* number of "shortcut" software interrupts */
231
232static int
233zsmatch(pdp, cfp, auxp)
234struct device	*pdp;
235struct cfdata	*cfp;
236void		*auxp;
237{
238	if(strcmp("zs", auxp) || cfp->cf_unit != 0)
239		return(0);
240	return(1);
241}
242
243/*
244 * Attach a found zs.
245 */
246static void
247zsattach(parent, dev, aux)
248struct device	*parent;
249struct device	*dev;
250void		*aux;
251{
252	register struct zs_softc		*zi;
253	register struct zs_chanstate		*cs;
254	register volatile struct zsdevice	*addr;
255		 char				tmp;
256
257	addr      = (struct zsdevice *)AD_SCC;
258	zi        = (struct zs_softc *)dev;
259	zi->zi_zs = addr;
260	cs        = zi->zi_cs;
261
262	/*
263	 * Get the command register into a known state.
264	 */
265	tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
266	tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
267	tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
268	tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
269
270	/*
271	 * Do a hardware reset.
272	 */
273	ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET);
274	delay(50000);	/*enough ? */
275	ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0);
276
277	/*
278	 * Initialize both channels
279	 */
280	zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs);
281	zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs);
282
283	if(machineid & ATARI_TT) {
284		/*
285		 * ininitialise TT-MFP timer C: 307200Hz
286		 * timer C and D share one control register:
287		 *	bits 0-2 control timer D
288		 *	bits 4-6 control timer C
289		 */
290		int cr = MFP2->mf_tcdcr & 7;
291		MFP2->mf_tcdcr = cr;		/* stop timer C  */
292		MFP2->mf_tcdr  = 1;		/* counter 1     */
293		cr |= T_Q004 << 4;		/* divisor 4     */
294		MFP2->mf_tcdcr = cr;		/* start timer C */
295		/*
296		 * enable scc related interrupts
297		 */
298		SCU->sys_mask |= SCU_SCC;
299
300		zs_frequencies = zs_freqs_tt;
301	} else if (machineid & ATARI_FALCON) {
302		zs_frequencies = zs_freqs_falcon;
303	} else if (machineid & ATARI_HADES) {
304		zs_frequencies = zs_freqs_hades;
305	} else {
306		zs_frequencies = zs_freqs_generic;
307	}
308
309	/* link into interrupt list with order (A,B) (B=A+1) */
310	cs[0].cs_next = &cs[1];
311	cs[1].cs_next = zslist;
312	zslist        = cs;
313
314	cs->cs_unit  = 0;
315	cs->cs_zc    = &addr->zs_chan[ZS_CHAN_A];
316	cs++;
317	cs->cs_unit  = 1;
318	cs->cs_zc    = &addr->zs_chan[ZS_CHAN_B];
319
320	printf(": serial2 on channel a and modem2 on channel b\n");
321}
322
323/*
324 * Open a zs serial port.
325 */
326int
327zsopen(dev, flags, mode, p)
328dev_t		dev;
329int		flags;
330int		mode;
331struct proc	*p;
332{
333	register struct tty		*tp;
334	register struct zs_chanstate	*cs;
335		 struct zs_softc	*zi;
336		 int			unit = ZS_UNIT(dev);
337		 int			zs = unit >> 1;
338		 int			error, s;
339
340	if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL)
341		return (ENXIO);
342	cs = &zi->zi_cs[unit & 1];
343
344	/*
345	 * When port A (ser02) is selected on the TT, make sure
346	 * the port is enabled.
347	 */
348	if((machineid & ATARI_TT) && !(unit & 1))
349		ym2149_ser2_select();
350
351	if (cs->cs_rbuf == NULL) {
352		cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF,
353								   M_WAITOK);
354	}
355
356	tp = cs->cs_ttyp;
357	if(tp == NULL) {
358		cs->cs_ttyp = tp = ttymalloc();
359		tty_attach(tp);
360		tp->t_dev   = dev;
361		tp->t_oproc = zsstart;
362		tp->t_param = zsparam;
363	}
364
365	s  = spltty();
366	if((tp->t_state & TS_ISOPEN) == 0) {
367		ttychars(tp);
368		if(tp->t_ispeed == 0) {
369			tp->t_iflag = TTYDEF_IFLAG;
370			tp->t_oflag = TTYDEF_OFLAG;
371			tp->t_cflag = TTYDEF_CFLAG;
372			tp->t_lflag = TTYDEF_LFLAG;
373			tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
374		}
375		(void)zsparam(tp, &tp->t_termios);
376		ttsetwater(tp);
377	}
378	else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
379			splx(s);
380			return (EBUSY);
381	}
382	error = 0;
383	for(;;) {
384		/* loop, turning on the device, until carrier present */
385		zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET);
386
387		/* May never get a status intr. if DCD already on. -gwr */
388		if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD)
389			tp->t_state |= TS_CARR_ON;
390		if(cs->cs_softcar)
391			tp->t_state |= TS_CARR_ON;
392		if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL ||
393		    tp->t_state & TS_CARR_ON)
394			break;
395		tp->t_state |= TS_WOPEN;
396		if((error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH,
397		    ttopen, 0)) != 0) {
398			if(!(tp->t_state & TS_ISOPEN)) {
399				zs_modem(cs, 0, DMSET);
400				tp->t_state &= ~TS_WOPEN;
401				ttwakeup(tp);
402			}
403			splx(s);
404			return error;
405		}
406	}
407	splx(s);
408	if(error == 0)
409		error = linesw[tp->t_line].l_open(dev, tp);
410	if(error)
411		zs_modem(cs, 0, DMSET);
412	return(error);
413}
414
415/*
416 * Close a zs serial port.
417 */
418int
419zsclose(dev, flags, mode, p)
420dev_t		dev;
421int		flags;
422int		mode;
423struct proc	*p;
424{
425	register struct zs_chanstate	*cs;
426	register struct tty		*tp;
427		 struct zs_softc	*zi;
428		 int			unit = ZS_UNIT(dev);
429		 int			s;
430
431	zi = zs_cd.cd_devs[unit >> 1];
432	cs = &zi->zi_cs[unit & 1];
433	tp = cs->cs_ttyp;
434	linesw[tp->t_line].l_close(tp, flags);
435	if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN ||
436	    (tp->t_state & TS_ISOPEN) == 0) {
437		zs_modem(cs, 0, DMSET);
438		/* hold low for 1 second */
439		(void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz);
440	}
441	if(cs->cs_creg[5] & ZSWR5_BREAK) {
442		s = splzs();
443		cs->cs_preg[5] &= ~ZSWR5_BREAK;
444		cs->cs_creg[5] &= ~ZSWR5_BREAK;
445		ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
446		splx(s);
447	}
448	ttyclose(tp);
449
450	/*
451	 * Drop all lines and cancel interrupts
452	 */
453	s = splzs();
454	zs_loadchannelregs(cs->cs_zc, zs_init_regs);
455	splx(s);
456	return (0);
457}
458
459/*
460 * Read/write zs serial port.
461 */
462int
463zsread(dev, uio, flags)
464dev_t		dev;
465struct uio	*uio;
466int		flags;
467{
468	register struct zs_chanstate	*cs;
469	register struct zs_softc	*zi;
470	register struct tty		*tp;
471		 int			unit;
472
473	unit = ZS_UNIT(dev);
474	zi   = zs_cd.cd_devs[unit >> 1];
475	cs   = &zi->zi_cs[unit & 1];
476	tp   = cs->cs_ttyp;
477
478	return(linesw[tp->t_line].l_read(tp, uio, flags));
479}
480
481int
482zswrite(dev, uio, flags)
483dev_t		dev;
484struct uio	*uio;
485int		flags;
486{
487	register struct zs_chanstate	*cs;
488	register struct zs_softc	*zi;
489	register struct tty		*tp;
490		 int			unit;
491
492	unit = ZS_UNIT(dev);
493	zi   = zs_cd.cd_devs[unit >> 1];
494	cs   = &zi->zi_cs[unit & 1];
495	tp   = cs->cs_ttyp;
496
497	return(linesw[tp->t_line].l_write(tp, uio, flags));
498}
499
500struct tty *
501zstty(dev)
502dev_t	dev;
503{
504	register struct zs_chanstate	*cs;
505	register struct zs_softc	*zi;
506		 int			unit;
507
508	unit = ZS_UNIT(dev);
509	zi   = zs_cd.cd_devs[unit >> 1];
510	cs   = &zi->zi_cs[unit & 1];
511	return(cs->cs_ttyp);
512}
513
514/*
515 * ZS hardware interrupt.  Scan all ZS channels.  NB: we know here that
516 * channels are kept in (A,B) pairs.
517 *
518 * Do just a little, then get out; set a software interrupt if more
519 * work is needed.
520 *
521 * We deliberately ignore the vectoring Zilog gives us, and match up
522 * only the number of `reset interrupt under service' operations, not
523 * the order.
524 */
525
526int
527zshard(sr)
528long sr;
529{
530	register struct zs_chanstate	*a;
531#define	b (a + 1)
532	register volatile struct zschan *zc;
533	register int			rr3, intflags = 0, v, i;
534
535	do {
536	    intflags &= ~4;
537	    for(a = zslist; a != NULL; a = b->cs_next) {
538		rr3 = ZS_READ(a->cs_zc, 3);
539		if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) {
540			intflags |= 4|2;
541			zc = a->cs_zc;
542			i  = a->cs_rbput;
543			if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) {
544				a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
545				intflags |= 1;
546			}
547			if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) {
548				a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
549				intflags |= 1;
550			}
551			if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) {
552				a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
553				intflags |= 1;
554			}
555			a->cs_rbput = i;
556		}
557		if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) {
558			intflags |= 4|2;
559			zc = b->cs_zc;
560			i  = b->cs_rbput;
561			if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) {
562				b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
563				intflags |= 1;
564			}
565			if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) {
566				b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
567				intflags |= 1;
568			}
569			if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) {
570				b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
571				intflags |= 1;
572			}
573			b->cs_rbput = i;
574		}
575	    }
576	} while(intflags & 4);
577#undef b
578
579	if(intflags & 1) {
580		if(BASEPRI(sr)) {
581			spl1();
582			zsshortcuts++;
583			return(zssoft(sr));
584		}
585		else if(!cb_scheduled) {
586			cb_scheduled++;
587			add_sicallback((si_farg)zssoft, 0, 0);
588		}
589	}
590	return(intflags & 2);
591}
592
593static int
594zsrint(cs, zc)
595register struct zs_chanstate	*cs;
596register volatile struct zschan	*zc;
597{
598	register int c;
599
600	/*
601	 * First read the status, because read of the received char
602	 * destroy the status of this char.
603	 */
604	c = ZS_READ(zc, 1);
605	c |= (zc->zc_data << 8);
606
607	/* clear receive error & interrupt condition */
608	zc->zc_csr = ZSWR0_RESET_ERRORS;
609	zc->zc_csr = ZSWR0_CLR_INTR;
610
611	return(ZRING_MAKE(ZRING_RINT, c));
612}
613
614static int
615zsxint(cs, zc)
616register struct zs_chanstate	*cs;
617register volatile struct zschan	*zc;
618{
619	register int i = cs->cs_tbc;
620
621	if(i == 0) {
622		zc->zc_csr = ZSWR0_RESET_TXINT;
623		zc->zc_csr = ZSWR0_CLR_INTR;
624		return(ZRING_MAKE(ZRING_XINT, 0));
625	}
626	cs->cs_tbc = i - 1;
627	zc->zc_data = *cs->cs_tba++;
628	zc->zc_csr = ZSWR0_CLR_INTR;
629	return (0);
630}
631
632static int
633zssint(cs, zc)
634register struct zs_chanstate	*cs;
635register volatile struct zschan	*zc;
636{
637	register int rr0;
638
639	rr0 = zc->zc_csr;
640	zc->zc_csr = ZSWR0_RESET_STATUS;
641	zc->zc_csr = ZSWR0_CLR_INTR;
642	/*
643	 * The chip's hardware flow control is, as noted in zsreg.h,
644	 * busted---if the DCD line goes low the chip shuts off the
645	 * receiver (!).  If we want hardware CTS flow control but do
646	 * not have it, and carrier is now on, turn HFC on; if we have
647	 * HFC now but carrier has gone low, turn it off.
648	 */
649	if(rr0 & ZSRR0_DCD) {
650		if(cs->cs_ttyp->t_cflag & CCTS_OFLOW &&
651		    (cs->cs_creg[3] & ZSWR3_HFC) == 0) {
652			cs->cs_creg[3] |= ZSWR3_HFC;
653			ZS_WRITE(zc, 3, cs->cs_creg[3]);
654		}
655	}
656	else {
657		if (cs->cs_creg[3] & ZSWR3_HFC) {
658			cs->cs_creg[3] &= ~ZSWR3_HFC;
659			ZS_WRITE(zc, 3, cs->cs_creg[3]);
660		}
661	}
662	return(ZRING_MAKE(ZRING_SINT, rr0));
663}
664
665/*
666 * Print out a ring or fifo overrun error message.
667 */
668static void
669zsoverrun(unit, ptime, what)
670int	unit;
671long	*ptime;
672char	*what;
673{
674
675	if(*ptime != time.tv_sec) {
676		*ptime = time.tv_sec;
677		log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1,
678		    (unit & 1) + 'a', what);
679	}
680}
681
682/*
683 * ZS software interrupt.  Scan all channels for deferred interrupts.
684 */
685int
686zssoft(sr)
687long sr;
688{
689    register struct zs_chanstate	*cs;
690    register volatile struct zschan	*zc;
691    register struct linesw		*line;
692    register struct tty			*tp;
693    register int			get, n, c, cc, unit, s;
694 	     int			retval = 0;
695
696    cb_scheduled = 0;
697    s = spltty();
698    for(cs = zslist; cs != NULL; cs = cs->cs_next) {
699	get = cs->cs_rbget;
700again:
701	n = cs->cs_rbput;	/* atomic			*/
702	if(get == n)		/* nothing more on this line	*/
703		continue;
704	retval = 1;
705	unit   = cs->cs_unit;	/* set up to handle interrupts	*/
706	zc     = cs->cs_zc;
707	tp     = cs->cs_ttyp;
708	line   = &linesw[tp->t_line];
709	/*
710	 * Compute the number of interrupts in the receive ring.
711	 * If the count is overlarge, we lost some events, and
712	 * must advance to the first valid one.  It may get
713	 * overwritten if more data are arriving, but this is
714	 * too expensive to check and gains nothing (we already
715	 * lost out; all we can do at this point is trade one
716	 * kind of loss for another).
717	 */
718	n -= get;
719	if(n > ZLRB_RING_SIZE) {
720		zsoverrun(unit, &cs->cs_rotime, "ring");
721		get += n - ZLRB_RING_SIZE;
722		n    = ZLRB_RING_SIZE;
723	}
724	while(--n >= 0) {
725		/* race to keep ahead of incoming interrupts */
726		c = cs->cs_rbuf[get++ & ZLRB_RING_MASK];
727		switch (ZRING_TYPE(c)) {
728
729		case ZRING_RINT:
730			c = ZRING_VALUE(c);
731			if(c & ZSRR1_DO)
732				zsoverrun(unit, &cs->cs_fotime, "fifo");
733			cc = c >> 8;
734			if(c & ZSRR1_FE)
735				cc |= TTY_FE;
736			if(c & ZSRR1_PE)
737				cc |= TTY_PE;
738			line->l_rint(cc, tp);
739			break;
740
741		case ZRING_XINT:
742			/*
743			 * Transmit done: change registers and resume,
744			 * or clear BUSY.
745			 */
746			if(cs->cs_heldchange) {
747				int sps;
748
749				sps = splzs();
750				c = zc->zc_csr;
751				if((c & ZSRR0_DCD) == 0)
752					cs->cs_preg[3] &= ~ZSWR3_HFC;
753				bcopy((caddr_t)cs->cs_preg,
754				    (caddr_t)cs->cs_creg, 16);
755				zs_loadchannelregs(zc, cs->cs_creg);
756				splx(sps);
757				cs->cs_heldchange = 0;
758				if(cs->cs_heldtbc
759					&& (tp->t_state & TS_TTSTOP) == 0) {
760					cs->cs_tbc = cs->cs_heldtbc - 1;
761					zc->zc_data = *cs->cs_tba++;
762					goto again;
763				}
764			}
765			tp->t_state &= ~TS_BUSY;
766			if(tp->t_state & TS_FLUSH)
767				tp->t_state &= ~TS_FLUSH;
768			else ndflush(&tp->t_outq,cs->cs_tba
769						- (caddr_t)tp->t_outq.c_cf);
770			line->l_start(tp);
771			break;
772
773		case ZRING_SINT:
774			/*
775			 * Status line change.  HFC bit is run in
776			 * hardware interrupt, to avoid locking
777			 * at splzs here.
778			 */
779			c = ZRING_VALUE(c);
780			if((c ^ cs->cs_rr0) & ZSRR0_DCD) {
781				cc = (c & ZSRR0_DCD) != 0;
782				if(line->l_modem(tp, cc) == 0)
783					zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR,
784							cc ? DMBIS : DMBIC);
785			}
786			cs->cs_rr0 = c;
787			break;
788
789		default:
790			log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n",
791			    unit >> 1, (unit & 1) + 'a', c);
792			break;
793		}
794	}
795	cs->cs_rbget = get;
796	goto again;
797    }
798    splx(s);
799    return (retval);
800}
801
802int
803zsioctl(dev, cmd, data, flag, p)
804dev_t		dev;
805u_long		cmd;
806caddr_t		data;
807int		flag;
808struct proc	*p;
809{
810		 int			unit = ZS_UNIT(dev);
811		 struct zs_softc	*zi = zs_cd.cd_devs[unit >> 1];
812	register struct tty		*tp = zi->zi_cs[unit & 1].cs_ttyp;
813	register int			error, s;
814	register struct zs_chanstate	*cs = &zi->zi_cs[unit & 1];
815
816	error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p);
817	if(error >= 0)
818		return(error);
819	error = ttioctl(tp, cmd, data, flag, p);
820	if(error >= 0)
821		return (error);
822
823	switch (cmd) {
824	case TIOCSBRK:
825		s = splzs();
826		cs->cs_preg[5] |= ZSWR5_BREAK;
827		cs->cs_creg[5] |= ZSWR5_BREAK;
828		ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
829		splx(s);
830		break;
831	case TIOCCBRK:
832		s = splzs();
833		cs->cs_preg[5] &= ~ZSWR5_BREAK;
834		cs->cs_creg[5] &= ~ZSWR5_BREAK;
835		ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
836		splx(s);
837		break;
838	case TIOCGFLAGS: {
839		int bits = 0;
840
841		if(cs->cs_softcar)
842			bits |= TIOCFLAG_SOFTCAR;
843		if(cs->cs_creg[15] & ZSWR15_DCD_IE)
844			bits |= TIOCFLAG_CLOCAL;
845		if(cs->cs_creg[3] & ZSWR3_HFC)
846			bits |= TIOCFLAG_CRTSCTS;
847		*(int *)data = bits;
848		break;
849	}
850	case TIOCSFLAGS: {
851		int userbits = 0;
852
853		error = suser(p->p_ucred, &p->p_acflag);
854		if(error != 0)
855			return (EPERM);
856
857		userbits = *(int *)data;
858
859		/*
860		 * can have `local' or `softcar', and `rtscts' or `mdmbuf'
861		 # defaulting to software flow control.
862		 */
863		if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL)
864			return(EINVAL);
865		if(userbits & TIOCFLAG_MDMBUF)	/* don't support this (yet?) */
866			return(ENODEV);
867
868		s = splzs();
869		if((userbits & TIOCFLAG_SOFTCAR)) {
870			cs->cs_softcar = 1;	/* turn on softcar */
871			cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */
872			cs->cs_creg[15] &= ~ZSWR15_DCD_IE;
873			ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
874		}
875		else if(userbits & TIOCFLAG_CLOCAL) {
876			cs->cs_softcar = 0; 	/* turn off softcar */
877			cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */
878			cs->cs_creg[15] |= ZSWR15_DCD_IE;
879			ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
880			tp->t_termios.c_cflag |= CLOCAL;
881		}
882		if(userbits & TIOCFLAG_CRTSCTS) {
883			cs->cs_preg[15] |= ZSWR15_CTS_IE;
884			cs->cs_creg[15] |= ZSWR15_CTS_IE;
885			ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
886			cs->cs_preg[3] |= ZSWR3_HFC;
887			cs->cs_creg[3] |= ZSWR3_HFC;
888			ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
889			tp->t_termios.c_cflag |= CRTSCTS;
890		}
891		else {
892			/* no mdmbuf, so we must want software flow control */
893			cs->cs_preg[15] &= ~ZSWR15_CTS_IE;
894			cs->cs_creg[15] &= ~ZSWR15_CTS_IE;
895			ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
896			cs->cs_preg[3] &= ~ZSWR3_HFC;
897			cs->cs_creg[3] &= ~ZSWR3_HFC;
898			ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
899			tp->t_termios.c_cflag &= ~CRTSCTS;
900		}
901		splx(s);
902		break;
903	}
904	case TIOCSDTR:
905		zs_modem(cs, ZSWR5_DTR, DMBIS);
906		break;
907	case TIOCCDTR:
908		zs_modem(cs, ZSWR5_DTR, DMBIC);
909		break;
910	case TIOCMGET:
911		zs_modem(cs, 0, DMGET);
912		break;
913	case TIOCMSET:
914	case TIOCMBIS:
915	case TIOCMBIC:
916	default:
917		return (ENOTTY);
918	}
919	return (0);
920}
921
922/*
923 * Start or restart transmission.
924 */
925static void
926zsstart(tp)
927register struct tty *tp;
928{
929	register struct zs_chanstate	*cs;
930	register int			s, nch;
931		 int			unit = ZS_UNIT(tp->t_dev);
932		 struct zs_softc	*zi = zs_cd.cd_devs[unit >> 1];
933
934	cs = &zi->zi_cs[unit & 1];
935	s  = spltty();
936
937	/*
938	 * If currently active or delaying, no need to do anything.
939	 */
940	if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP))
941		goto out;
942
943	/*
944	 * If there are sleepers, and output has drained below low
945	 * water mark, awaken.
946	 */
947	if(tp->t_outq.c_cc <= tp->t_lowat) {
948		if(tp->t_state & TS_ASLEEP) {
949			tp->t_state &= ~TS_ASLEEP;
950			wakeup((caddr_t)&tp->t_outq);
951		}
952		selwakeup(&tp->t_wsel);
953	}
954
955	nch = ndqb(&tp->t_outq, 0);	/* XXX */
956	if(nch) {
957		register char *p = tp->t_outq.c_cf;
958
959		/* mark busy, enable tx done interrupts, & send first byte */
960		tp->t_state |= TS_BUSY;
961		(void) splzs();
962		cs->cs_preg[1] |= ZSWR1_TIE;
963		cs->cs_creg[1] |= ZSWR1_TIE;
964		ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
965		cs->cs_zc->zc_data = *p;
966		cs->cs_tba = p + 1;
967		cs->cs_tbc = nch - 1;
968	} else {
969		/*
970		 * Nothing to send, turn off transmit done interrupts.
971		 * This is useful if something is doing polled output.
972		 */
973		(void) splzs();
974		cs->cs_preg[1] &= ~ZSWR1_TIE;
975		cs->cs_creg[1] &= ~ZSWR1_TIE;
976		ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
977	}
978out:
979	splx(s);
980}
981
982/*
983 * Stop output, e.g., for ^S or output flush.
984 */
985void
986zsstop(tp, flag)
987register struct tty	*tp;
988	 int		flag;
989{
990	register struct zs_chanstate	*cs;
991	register int			s, unit = ZS_UNIT(tp->t_dev);
992		 struct zs_softc	*zi = zs_cd.cd_devs[unit >> 1];
993
994	cs = &zi->zi_cs[unit & 1];
995	s  = splzs();
996	if(tp->t_state & TS_BUSY) {
997		/*
998		 * Device is transmitting; must stop it.
999		 */
1000		cs->cs_tbc = 0;
1001		if ((tp->t_state & TS_TTSTOP) == 0)
1002			tp->t_state |= TS_FLUSH;
1003	}
1004	splx(s);
1005}
1006
1007/*
1008 * Set ZS tty parameters from termios.
1009 *
1010 * This routine makes use of the fact that only registers
1011 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written.
1012 */
1013static int
1014zsparam(tp, t)
1015register struct tty	*tp;
1016register struct termios	*t;
1017{
1018		 int			unit = ZS_UNIT(tp->t_dev);
1019		 struct zs_softc	*zi = zs_cd.cd_devs[unit >> 1];
1020	register struct zs_chanstate	*cs = &zi->zi_cs[unit & 1];
1021		 int			cdiv, clkm, brgm, tcon;
1022	register int			tmp, tmp5, cflag, s;
1023
1024	tmp  = t->c_ospeed;
1025	tmp5 = t->c_ispeed;
1026	if(tmp < 0 || (tmp5 && tmp5 != tmp))
1027		return(EINVAL);
1028	if(tmp == 0) {
1029		/* stty 0 => drop DTR and RTS */
1030		zs_modem(cs, 0, DMSET);
1031		return(0);
1032	}
1033	tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon);
1034	if (tmp < 0)
1035		return(EINVAL);
1036	tp->t_ispeed = tp->t_ospeed = tmp;
1037
1038	cflag = tp->t_cflag = t->c_cflag;
1039	if (cflag & CSTOPB)
1040		cdiv |= ZSWR4_TWOSB;
1041	else
1042		cdiv |= ZSWR4_ONESB;
1043	if (!(cflag & PARODD))
1044		cdiv |= ZSWR4_EVENP;
1045	if (cflag & PARENB)
1046		cdiv |= ZSWR4_PARENB;
1047
1048	switch(cflag & CSIZE) {
1049	case CS5:
1050		tmp  = ZSWR3_RX_5;
1051		tmp5 = ZSWR5_TX_5;
1052		break;
1053	case CS6:
1054		tmp  = ZSWR3_RX_6;
1055		tmp5 = ZSWR5_TX_6;
1056		break;
1057	case CS7:
1058		tmp  = ZSWR3_RX_7;
1059		tmp5 = ZSWR5_TX_7;
1060		break;
1061	case CS8:
1062	default:
1063		tmp  = ZSWR3_RX_8;
1064		tmp5 = ZSWR5_TX_8;
1065		break;
1066	}
1067	tmp  |= ZSWR3_RX_ENABLE;
1068	tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
1069
1070	/*
1071	 * Block interrupts so that state will not
1072	 * be altered until we are done setting it up.
1073	 */
1074	s = splzs();
1075	cs->cs_preg[4]  = cdiv;
1076	cs->cs_preg[11] = clkm;
1077	cs->cs_preg[12] = tcon;
1078	cs->cs_preg[13] = tcon >> 8;
1079	cs->cs_preg[14] = brgm;
1080	cs->cs_preg[1]  = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE;
1081	cs->cs_preg[9]  = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT;
1082	cs->cs_preg[10] = ZSWR10_NRZ;
1083	cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE;
1084
1085	/*
1086	 * Output hardware flow control on the chip is horrendous: if
1087	 * carrier detect drops, the receiver is disabled.  Hence we
1088	 * can only do this when the carrier is on.
1089	 */
1090	if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD)
1091		tmp |= ZSWR3_HFC;
1092	cs->cs_preg[3] = tmp;
1093	cs->cs_preg[5] = tmp5;
1094
1095	/*
1096	 * If nothing is being transmitted, set up new current values,
1097	 * else mark them as pending.
1098	 */
1099	if(cs->cs_heldchange == 0) {
1100		if (cs->cs_ttyp->t_state & TS_BUSY) {
1101			cs->cs_heldtbc = cs->cs_tbc;
1102			cs->cs_tbc = 0;
1103			cs->cs_heldchange = 1;
1104		} else {
1105			bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
1106			zs_loadchannelregs(cs->cs_zc, cs->cs_creg);
1107		}
1108	}
1109	splx(s);
1110	return (0);
1111}
1112
1113/*
1114 * search for the best matching baudrate
1115 */
1116static int
1117zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst)
1118int	unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst;
1119{
1120	int	bestdiff, bestbps, source;
1121
1122	bestdiff = bestbps = 0;
1123	unit = (unit & 1) << 2;
1124	for (source = 0; source < 4; ++source) {
1125		long	freq = zs_frequencies[unit + source];
1126		int	diff, bps, div, clkm, brgm, tcon;
1127
1128		bps = div = clkm = brgm = tcon = 0;
1129		switch (source) {
1130			case 0:	/* BRgen, PCLK */
1131				brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK;
1132				break;
1133			case 1:	/* BRgen, RTxC */
1134				brgm = ZSWR14_BAUD_ENA;
1135				break;
1136			case 2: /* RTxC */
1137				clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC;
1138				break;
1139			case 3: /* TRxC */
1140				clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC;
1141				break;
1142		}
1143		switch (source) {
1144			case 0:
1145			case 1:
1146				div  = ZSWR4_CLK_X16;
1147				clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD;
1148				tcon = BPS_TO_TCONST(freq, wanted);
1149				if (tcon < 0)
1150					tcon = 0;
1151				bps  = TCONST_TO_BPS(freq, tcon);
1152				break;
1153			case 2:
1154			case 3:
1155			{	int	b1 = freq / 16, d1 = abs(b1 - wanted);
1156				int	b2 = freq / 32, d2 = abs(b2 - wanted);
1157				int	b3 = freq / 64, d3 = abs(b3 - wanted);
1158
1159				if (d1 < d2 && d1 < d3) {
1160					div = ZSWR4_CLK_X16;
1161					bps = b1;
1162				} else if (d2 < d3 && d2 < d1) {
1163					div = ZSWR4_CLK_X32;
1164					bps = b2;
1165				} else {
1166					div = ZSWR4_CLK_X64;
1167					bps = b3;
1168				}
1169				brgm = tcon = 0;
1170				break;
1171			}
1172		}
1173		diff = abs(bps - wanted);
1174		if (!source || diff < bestdiff) {
1175			*divisor   = div;
1176			*clockmode = clkm;
1177			*brgenmode = brgm;
1178			*timeconst = tcon;
1179			bestbps    = bps;
1180			bestdiff   = diff;
1181			if (diff == 0)
1182				break;
1183		}
1184	}
1185	/* Allow deviations upto 5% */
1186	if (20 * bestdiff > wanted)
1187		return -1;
1188	return bestbps;
1189}
1190
1191/*
1192 * Raise or lower modem control (DTR/RTS) signals.  If a character is
1193 * in transmission, the change is deferred.
1194 */
1195static int
1196zs_modem(cs, bits, how)
1197struct zs_chanstate	*cs;
1198int			bits, how;
1199{
1200	int s, mbits;
1201
1202	bits  &= ZSWR5_DTR | ZSWR5_RTS;
1203
1204	s = splzs();
1205	mbits  = cs->cs_preg[5] &  (ZSWR5_DTR | ZSWR5_RTS);
1206
1207	switch(how) {
1208		case DMSET:
1209				mbits  = bits;
1210				break;
1211		case DMBIS:
1212				mbits |= bits;
1213				break;
1214		case DMBIC:
1215				mbits &= ~bits;
1216				break;
1217		case DMGET:
1218				splx(s);
1219				return(mbits);
1220	}
1221
1222	cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits;
1223	if(cs->cs_heldchange == 0) {
1224		if(cs->cs_ttyp->t_state & TS_BUSY) {
1225			cs->cs_heldtbc = cs->cs_tbc;
1226			cs->cs_tbc = 0;
1227			cs->cs_heldchange = 1;
1228		}
1229		else {
1230			ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
1231		}
1232	}
1233	splx(s);
1234	return(0);
1235}
1236
1237/*
1238 * Write the given register set to the given zs channel in the proper order.
1239 * The channel must not be transmitting at the time.  The receiver will
1240 * be disabled for the time it takes to write all the registers.
1241 */
1242static void
1243zs_loadchannelregs(zc, reg)
1244volatile struct zschan	*zc;
1245u_char			*reg;
1246{
1247	int i;
1248
1249	zc->zc_csr = ZSM_RESET_ERR;	/* reset error condition */
1250	i = zc->zc_data;		/* drain fifo */
1251	i = zc->zc_data;
1252	i = zc->zc_data;
1253	ZS_WRITE(zc,  4, reg[4]);
1254	ZS_WRITE(zc, 10, reg[10]);
1255	ZS_WRITE(zc,  3, reg[3] & ~ZSWR3_RX_ENABLE);
1256	ZS_WRITE(zc,  5, reg[5] & ~ZSWR5_TX_ENABLE);
1257	ZS_WRITE(zc,  1, reg[1]);
1258	ZS_WRITE(zc,  9, reg[9]);
1259	ZS_WRITE(zc, 11, reg[11]);
1260	ZS_WRITE(zc, 12, reg[12]);
1261	ZS_WRITE(zc, 13, reg[13]);
1262	ZS_WRITE(zc, 14, reg[14]);
1263	ZS_WRITE(zc, 15, reg[15]);
1264	ZS_WRITE(zc,  3, reg[3]);
1265	ZS_WRITE(zc,  5, reg[5]);
1266}
1267#endif /* NZS > 1 */
1268