zs.c revision 1.15
1/* $NetBSD: zs.c,v 1.15 1996/02/22 10:11:37 leo Exp $ */ 2 3/* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49/* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/proc.h> 59#include <sys/device.h> 60#include <sys/conf.h> 61#include <sys/file.h> 62#include <sys/ioctl.h> 63#include <sys/malloc.h> 64#include <sys/tty.h> 65#include <sys/time.h> 66#include <sys/kernel.h> 67#include <sys/syslog.h> 68 69#include <machine/cpu.h> 70#include <machine/iomap.h> 71#include <machine/scu.h> 72#include <machine/mfp.h> 73#include <machine/video.h> 74 75#include <dev/ic/z8530reg.h> 76#include <atari/dev/zsvar.h> 77#include "zs.h" 78#if NZS > 1 79#error "This driver supports only 1 85C30!" 80#endif 81 82#if NZS > 0 83 84#define PCLK (8053976) /* PCLK pin input clock rate */ 85 86#define splzs spl5 87 88/* 89 * Software state per found chip. 90 */ 91struct zs_softc { 92 struct device zi_dev; /* base device */ 93 volatile struct zsdevice *zi_zs; /* chip registers */ 94 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 95}; 96 97static u_char cb_scheduled = 0; /* Already asked for callback? */ 98/* 99 * Define the registers for a closed port 100 */ 101static u_char zs_init_regs[16] = { 102/* 0 */ 0, 103/* 1 */ 0, 104/* 2 */ 0x60, 105/* 3 */ 0, 106/* 4 */ 0, 107/* 5 */ 0, 108/* 6 */ 0, 109/* 7 */ 0, 110/* 8 */ 0, 111/* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 112/* 10 */ ZSWR10_NRZ, 113/* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 114/* 12 */ 0, 115/* 13 */ 0, 116/* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 117/* 15 */ 0 118}; 119 120/* 121 * Define the machine dependant clock frequencies 122 * If BRgen feeds sender/receiver we always use a 123 * divisor 16, therefor the division by 16 can as 124 * well be done here. 125 */ 126static u_long zs_freqs_tt[] = { 127 /* 128 * Atari TT, RTxCB is generated by TT-MFP timer C, 129 * which is set to 307.2KHz during initialisation 130 * and never changed afterwards. 131 */ 132 PCLK/16, /* BRgen, PCLK, divisor 16 */ 133 229500, /* BRgen, RTxCA, divisor 16 */ 134 3672000, /* RTxCA, from PCLK4 */ 135 0, /* TRxCA, external */ 136 137 PCLK/16, /* BRgen, PCLK, divisor 16 */ 138 19200, /* BRgen, RTxCB, divisor 16 */ 139 307200, /* RTxCB, from TT-MFP TCO */ 140 2457600 /* TRxCB, from BCLK */ 141}; 142static u_long zs_freqs_falcon[] = { 143 /* 144 * Atari Falcon, XXX no specs available, this might be wrong 145 */ 146 PCLK/16, /* BRgen, PCLK, divisor 16 */ 147 229500, /* BRgen, RTxCA, divisor 16 */ 148 3672000, /* RTxCA, ??? */ 149 0, /* TRxCA, external */ 150 151 PCLK/16, /* BRgen, PCLK, divisor 16 */ 152 229500, /* BRgen, RTxCB, divisor 16 */ 153 3672000, /* RTxCB, ??? */ 154 2457600 /* TRxCB, ??? */ 155}; 156static u_long zs_freqs_generic[] = { 157 /* 158 * other machines, assume only PCLK is available 159 */ 160 PCLK/16, /* BRgen, PCLK, divisor 16 */ 161 0, /* BRgen, RTxCA, divisor 16 */ 162 0, /* RTxCA, unknown */ 163 0, /* TRxCA, unknown */ 164 165 PCLK/16, /* BRgen, PCLK, divisor 16 */ 166 0, /* BRgen, RTxCB, divisor 16 */ 167 0, /* RTxCB, unknown */ 168 0 /* TRxCB, unknown */ 169}; 170static u_long *zs_frequencies; 171 172/* Definition of the driver for autoconfig. */ 173static int zsmatch __P((struct device *, struct cfdata *, void *)); 174static void zsattach __P((struct device *, struct device *, void *)); 175struct cfdriver zscd = { 176 NULL, "zs", (cfmatch_t)zsmatch, zsattach, DV_TTY, 177 sizeof(struct zs_softc), NULL, 0 }; 178 179/* {b,c}devsw[] function prototypes */ 180dev_type_open(zsopen); 181dev_type_close(zsclose); 182dev_type_read(zsread); 183dev_type_write(zswrite); 184dev_type_ioctl(zsioctl); 185 186/* Interrupt handlers. */ 187int zshard __P((long)); 188static int zssoft __P((long)); 189static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 190static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 191static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 192 193static struct zs_chanstate *zslist; 194 195/* Routines called from other code. */ 196static void zsstart __P((struct tty *)); 197void zsstop __P((struct tty *, int)); 198static int zsparam __P((struct tty *, struct termios *)); 199static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 200 201/* Routines purely local to this driver. */ 202static int zs_modem __P((struct zs_chanstate *, int, int)); 203static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 204 205static int zsshortcuts; /* number of "shortcut" software interrupts */ 206 207static int 208zsmatch(pdp, cfp, auxp) 209struct device *pdp; 210struct cfdata *cfp; 211void *auxp; 212{ 213 if(strcmp("zs", auxp) || cfp->cf_unit != 0) 214 return(0); 215 return(1); 216} 217 218/* 219 * Attach a found zs. 220 */ 221static void 222zsattach(parent, dev, aux) 223struct device *parent; 224struct device *dev; 225void *aux; 226{ 227 register struct zs_softc *zi; 228 register struct zs_chanstate *cs; 229 register volatile struct zsdevice *addr; 230 char tmp; 231 232 addr = (struct zsdevice *)AD_SCC; 233 zi = (struct zs_softc *)dev; 234 zi->zi_zs = addr; 235 cs = zi->zi_cs; 236 237 /* 238 * Get the command register into a known state. 239 */ 240 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 241 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 242 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 243 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 244 245 /* 246 * Do a hardware reset. 247 */ 248 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 249 delay(50000); /*enough ? */ 250 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 251 252 /* 253 * Initialize both channels 254 */ 255 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 256 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 257 258 if(machineid & ATARI_TT) { 259 /* 260 * ininitialise TT-MFP timer C: 307200Hz 261 * timer C and D share one control register: 262 * bits 0-2 control timer D 263 * bits 4-6 control timer C 264 */ 265 int cr = MFP2->mf_tcdcr & 7; 266 MFP2->mf_tcdcr = cr; /* stop timer C */ 267 MFP2->mf_tcdr = 1; /* counter 1 */ 268 cr |= T_Q004 << 4; /* divisor 4 */ 269 MFP2->mf_tcdcr = cr; /* start timer C */ 270 /* 271 * enable scc related interrupts 272 */ 273 SCU->sys_mask |= SCU_SCC; 274 275 zs_frequencies = zs_freqs_tt; 276 } else if (machineid & ATARI_FALCON) { 277 zs_frequencies = zs_freqs_falcon; 278 } else { 279 zs_frequencies = zs_freqs_generic; 280 } 281 282 /* link into interrupt list with order (A,B) (B=A+1) */ 283 cs[0].cs_next = &cs[1]; 284 cs[1].cs_next = zslist; 285 zslist = cs; 286 287 cs->cs_unit = 0; 288 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 289 cs++; 290 cs->cs_unit = 1; 291 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 292 293 printf(": serial2 on channel a and modem2 on channel b\n"); 294} 295 296/* 297 * Open a zs serial port. 298 */ 299int 300zsopen(dev, flags, mode, p) 301dev_t dev; 302int flags; 303int mode; 304struct proc *p; 305{ 306 register struct tty *tp; 307 register struct zs_chanstate *cs; 308 struct zs_softc *zi; 309 int unit = ZS_UNIT(dev); 310 int zs = unit >> 1; 311 int error, s; 312 313 if(zs >= zscd.cd_ndevs || (zi = zscd.cd_devs[zs]) == NULL) 314 return (ENXIO); 315 cs = &zi->zi_cs[unit & 1]; 316 317 /* 318 * When port A (ser02) is selected on the TT, make sure 319 * the port is enabled. 320 */ 321 if((machineid & ATARI_TT) && !(unit & 1)) { 322 SOUND->sd_selr = YM_IOA; 323 SOUND->sd_wdat = SOUND->sd_rdat | PA_SER2; 324 } 325 326 if (cs->cs_rbuf == NULL) { 327 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 328 M_WAITOK); 329 } 330 331 tp = cs->cs_ttyp; 332 if(tp == NULL) { 333 cs->cs_ttyp = tp = ttymalloc(); 334 tp->t_dev = dev; 335 tp->t_oproc = zsstart; 336 tp->t_param = zsparam; 337 } 338 339 s = spltty(); 340 if((tp->t_state & TS_ISOPEN) == 0) { 341 ttychars(tp); 342 if(tp->t_ispeed == 0) { 343 tp->t_iflag = TTYDEF_IFLAG; 344 tp->t_oflag = TTYDEF_OFLAG; 345 tp->t_cflag = TTYDEF_CFLAG; 346 tp->t_lflag = TTYDEF_LFLAG; 347 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 348 } 349 (void)zsparam(tp, &tp->t_termios); 350 ttsetwater(tp); 351 } 352 else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 353 splx(s); 354 return (EBUSY); 355 } 356 error = 0; 357 for(;;) { 358 /* loop, turning on the device, until carrier present */ 359 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 360 361 /* May never get a status intr. if DCD already on. -gwr */ 362 if(cs->cs_zc->zc_csr & ZSRR0_DCD) 363 tp->t_state |= TS_CARR_ON; 364 if(cs->cs_softcar) 365 tp->t_state |= TS_CARR_ON; 366 if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL || 367 tp->t_state & TS_CARR_ON) 368 break; 369 tp->t_state |= TS_WOPEN; 370 if(error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH, 371 ttopen, 0)) { 372 if(!(tp->t_state & TS_ISOPEN)) { 373 zs_modem(cs, 0, DMSET); 374 tp->t_state &= ~TS_WOPEN; 375 ttwakeup(tp); 376 } 377 splx(s); 378 return error; 379 } 380 } 381 splx(s); 382 if(error == 0) 383 error = linesw[tp->t_line].l_open(dev, tp); 384 if(error) 385 zs_modem(cs, 0, DMSET); 386 return(error); 387} 388 389/* 390 * Close a zs serial port. 391 */ 392int 393zsclose(dev, flags, mode, p) 394dev_t dev; 395int flags; 396int mode; 397struct proc *p; 398{ 399 register struct zs_chanstate *cs; 400 register struct tty *tp; 401 struct zs_softc *zi; 402 int unit = ZS_UNIT(dev); 403 int s; 404 405 zi = zscd.cd_devs[unit >> 1]; 406 cs = &zi->zi_cs[unit & 1]; 407 tp = cs->cs_ttyp; 408 linesw[tp->t_line].l_close(tp, flags); 409 if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN || 410 (tp->t_state & TS_ISOPEN) == 0) { 411 zs_modem(cs, 0, DMSET); 412 /* hold low for 1 second */ 413 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 414 } 415 if(cs->cs_creg[5] & ZSWR5_BREAK) { 416 s = splzs(); 417 cs->cs_preg[5] &= ~ZSWR5_BREAK; 418 cs->cs_creg[5] &= ~ZSWR5_BREAK; 419 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 420 splx(s); 421 } 422 ttyclose(tp); 423 424 /* 425 * Drop all lines and cancel interrupts 426 */ 427 s = splzs(); 428 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 429 splx(s); 430 return (0); 431} 432 433/* 434 * Read/write zs serial port. 435 */ 436int 437zsread(dev, uio, flags) 438dev_t dev; 439struct uio *uio; 440int flags; 441{ 442 register struct zs_chanstate *cs; 443 register struct zs_softc *zi; 444 register struct tty *tp; 445 int unit; 446 447 unit = ZS_UNIT(dev); 448 zi = zscd.cd_devs[unit >> 1]; 449 cs = &zi->zi_cs[unit & 1]; 450 tp = cs->cs_ttyp; 451 452 return(linesw[tp->t_line].l_read(tp, uio, flags)); 453} 454 455int 456zswrite(dev, uio, flags) 457dev_t dev; 458struct uio *uio; 459int flags; 460{ 461 register struct zs_chanstate *cs; 462 register struct zs_softc *zi; 463 register struct tty *tp; 464 int unit; 465 466 unit = ZS_UNIT(dev); 467 zi = zscd.cd_devs[unit >> 1]; 468 cs = &zi->zi_cs[unit & 1]; 469 tp = cs->cs_ttyp; 470 471 return(linesw[tp->t_line].l_write(tp, uio, flags)); 472} 473 474struct tty * 475zstty(dev) 476dev_t dev; 477{ 478 register struct zs_chanstate *cs; 479 register struct zs_softc *zi; 480 int unit; 481 482 unit = ZS_UNIT(dev); 483 zi = zscd.cd_devs[unit >> 1]; 484 cs = &zi->zi_cs[unit & 1]; 485 return(cs->cs_ttyp); 486} 487 488/* 489 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 490 * channels are kept in (A,B) pairs. 491 * 492 * Do just a little, then get out; set a software interrupt if more 493 * work is needed. 494 * 495 * We deliberately ignore the vectoring Zilog gives us, and match up 496 * only the number of `reset interrupt under service' operations, not 497 * the order. 498 */ 499 500int 501zshard(sr) 502long sr; 503{ 504 register struct zs_chanstate *a; 505#define b (a + 1) 506 register volatile struct zschan *zc; 507 register int rr3, intflags = 0, v, i; 508 509 do { 510 intflags &= ~4; 511 for(a = zslist; a != NULL; a = b->cs_next) { 512 rr3 = ZS_READ(a->cs_zc, 3); 513 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 514 intflags |= 4|2; 515 zc = a->cs_zc; 516 i = a->cs_rbput; 517 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 518 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 519 intflags |= 1; 520 } 521 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 522 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 523 intflags |= 1; 524 } 525 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 526 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 527 intflags |= 1; 528 } 529 a->cs_rbput = i; 530 } 531 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 532 intflags |= 4|2; 533 zc = b->cs_zc; 534 i = b->cs_rbput; 535 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 536 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 537 intflags |= 1; 538 } 539 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 540 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 541 intflags |= 1; 542 } 543 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 544 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 545 intflags |= 1; 546 } 547 b->cs_rbput = i; 548 } 549 } 550 } while(intflags & 4); 551#undef b 552 553 if(intflags & 1) { 554 if(BASEPRI(sr)) { 555 spl1(); 556 zsshortcuts++; 557 return(zssoft(sr)); 558 } 559 else if(!cb_scheduled) { 560 cb_scheduled++; 561 add_sicallback(zssoft, 0, 0); 562 } 563 } 564 return(intflags & 2); 565} 566 567static int 568zsrint(cs, zc) 569register struct zs_chanstate *cs; 570register volatile struct zschan *zc; 571{ 572 register int c; 573 574 /* 575 * First read the status, because read of the received char 576 * destroy the status of this char. 577 */ 578 c = ZS_READ(zc, 1); 579 c |= (zc->zc_data << 8); 580 581 /* clear receive error & interrupt condition */ 582 zc->zc_csr = ZSWR0_RESET_ERRORS; 583 zc->zc_csr = ZSWR0_CLR_INTR; 584 585 return(ZRING_MAKE(ZRING_RINT, c)); 586} 587 588static int 589zsxint(cs, zc) 590register struct zs_chanstate *cs; 591register volatile struct zschan *zc; 592{ 593 register int i = cs->cs_tbc; 594 595 if(i == 0) { 596 zc->zc_csr = ZSWR0_RESET_TXINT; 597 zc->zc_csr = ZSWR0_CLR_INTR; 598 return(ZRING_MAKE(ZRING_XINT, 0)); 599 } 600 cs->cs_tbc = i - 1; 601 zc->zc_data = *cs->cs_tba++; 602 zc->zc_csr = ZSWR0_CLR_INTR; 603 return (0); 604} 605 606static int 607zssint(cs, zc) 608register struct zs_chanstate *cs; 609register volatile struct zschan *zc; 610{ 611 register int rr0; 612 613 rr0 = zc->zc_csr; 614 zc->zc_csr = ZSWR0_RESET_STATUS; 615 zc->zc_csr = ZSWR0_CLR_INTR; 616 /* 617 * The chip's hardware flow control is, as noted in zsreg.h, 618 * busted---if the DCD line goes low the chip shuts off the 619 * receiver (!). If we want hardware CTS flow control but do 620 * not have it, and carrier is now on, turn HFC on; if we have 621 * HFC now but carrier has gone low, turn it off. 622 */ 623 if(rr0 & ZSRR0_DCD) { 624 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 625 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 626 cs->cs_creg[3] |= ZSWR3_HFC; 627 ZS_WRITE(zc, 3, cs->cs_creg[3]); 628 } 629 } 630 else { 631 if (cs->cs_creg[3] & ZSWR3_HFC) { 632 cs->cs_creg[3] &= ~ZSWR3_HFC; 633 ZS_WRITE(zc, 3, cs->cs_creg[3]); 634 } 635 } 636 return(ZRING_MAKE(ZRING_SINT, rr0)); 637} 638 639/* 640 * Print out a ring or fifo overrun error message. 641 */ 642static void 643zsoverrun(unit, ptime, what) 644int unit; 645long *ptime; 646char *what; 647{ 648 649 if(*ptime != time.tv_sec) { 650 *ptime = time.tv_sec; 651 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 652 (unit & 1) + 'a', what); 653 } 654} 655 656/* 657 * ZS software interrupt. Scan all channels for deferred interrupts. 658 */ 659int 660zssoft(sr) 661long sr; 662{ 663 register struct zs_chanstate *cs; 664 register volatile struct zschan *zc; 665 register struct linesw *line; 666 register struct tty *tp; 667 register int get, n, c, cc, unit, s; 668 int retval = 0; 669 670 cb_scheduled = 0; 671 s = spltty(); 672 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 673 get = cs->cs_rbget; 674again: 675 n = cs->cs_rbput; /* atomic */ 676 if(get == n) /* nothing more on this line */ 677 continue; 678 retval = 1; 679 unit = cs->cs_unit; /* set up to handle interrupts */ 680 zc = cs->cs_zc; 681 tp = cs->cs_ttyp; 682 line = &linesw[tp->t_line]; 683 /* 684 * Compute the number of interrupts in the receive ring. 685 * If the count is overlarge, we lost some events, and 686 * must advance to the first valid one. It may get 687 * overwritten if more data are arriving, but this is 688 * too expensive to check and gains nothing (we already 689 * lost out; all we can do at this point is trade one 690 * kind of loss for another). 691 */ 692 n -= get; 693 if(n > ZLRB_RING_SIZE) { 694 zsoverrun(unit, &cs->cs_rotime, "ring"); 695 get += n - ZLRB_RING_SIZE; 696 n = ZLRB_RING_SIZE; 697 } 698 while(--n >= 0) { 699 /* race to keep ahead of incoming interrupts */ 700 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 701 switch (ZRING_TYPE(c)) { 702 703 case ZRING_RINT: 704 c = ZRING_VALUE(c); 705 if(c & ZSRR1_DO) 706 zsoverrun(unit, &cs->cs_fotime, "fifo"); 707 cc = c >> 8; 708 if(c & ZSRR1_FE) 709 cc |= TTY_FE; 710 if(c & ZSRR1_PE) 711 cc |= TTY_PE; 712 line->l_rint(cc, tp); 713 break; 714 715 case ZRING_XINT: 716 /* 717 * Transmit done: change registers and resume, 718 * or clear BUSY. 719 */ 720 if(cs->cs_heldchange) { 721 int sps; 722 723 sps = splzs(); 724 c = zc->zc_csr; 725 if((c & ZSRR0_DCD) == 0) 726 cs->cs_preg[3] &= ~ZSWR3_HFC; 727 bcopy((caddr_t)cs->cs_preg, 728 (caddr_t)cs->cs_creg, 16); 729 zs_loadchannelregs(zc, cs->cs_creg); 730 splx(sps); 731 cs->cs_heldchange = 0; 732 if(cs->cs_heldtbc 733 && (tp->t_state & TS_TTSTOP) == 0) { 734 cs->cs_tbc = cs->cs_heldtbc - 1; 735 zc->zc_data = *cs->cs_tba++; 736 goto again; 737 } 738 } 739 tp->t_state &= ~TS_BUSY; 740 if(tp->t_state & TS_FLUSH) 741 tp->t_state &= ~TS_FLUSH; 742 else ndflush(&tp->t_outq,cs->cs_tba 743 - (caddr_t)tp->t_outq.c_cf); 744 line->l_start(tp); 745 break; 746 747 case ZRING_SINT: 748 /* 749 * Status line change. HFC bit is run in 750 * hardware interrupt, to avoid locking 751 * at splzs here. 752 */ 753 c = ZRING_VALUE(c); 754 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 755 cc = (c & ZSRR0_DCD) != 0; 756 if(line->l_modem(tp, cc) == 0) 757 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 758 cc ? DMBIS : DMBIC); 759 } 760 cs->cs_rr0 = c; 761 break; 762 763 default: 764 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 765 unit >> 1, (unit & 1) + 'a', c); 766 break; 767 } 768 } 769 cs->cs_rbget = get; 770 goto again; 771 } 772 splx(s); 773 return (retval); 774} 775 776int 777zsioctl(dev, cmd, data, flag, p) 778dev_t dev; 779u_long cmd; 780caddr_t data; 781int flag; 782struct proc *p; 783{ 784 int unit = ZS_UNIT(dev); 785 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 786 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 787 register int error, s; 788 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 789 790 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 791 if(error >= 0) 792 return(error); 793 error = ttioctl(tp, cmd, data, flag, p); 794 if(error >= 0) 795 return (error); 796 797 switch (cmd) { 798 case TIOCSBRK: 799 s = splzs(); 800 cs->cs_preg[5] |= ZSWR5_BREAK; 801 cs->cs_creg[5] |= ZSWR5_BREAK; 802 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 803 splx(s); 804 break; 805 case TIOCCBRK: 806 s = splzs(); 807 cs->cs_preg[5] &= ~ZSWR5_BREAK; 808 cs->cs_creg[5] &= ~ZSWR5_BREAK; 809 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 810 splx(s); 811 break; 812 case TIOCGFLAGS: { 813 int bits = 0; 814 815 if(cs->cs_softcar) 816 bits |= TIOCFLAG_SOFTCAR; 817 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 818 bits |= TIOCFLAG_CLOCAL; 819 if(cs->cs_creg[3] & ZSWR3_HFC) 820 bits |= TIOCFLAG_CRTSCTS; 821 *(int *)data = bits; 822 break; 823 } 824 case TIOCSFLAGS: { 825 int userbits = 0; 826 827 error = suser(p->p_ucred, &p->p_acflag); 828 if(error != 0) 829 return (EPERM); 830 831 userbits = *(int *)data; 832 833 /* 834 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 835 # defaulting to software flow control. 836 */ 837 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 838 return(EINVAL); 839 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 840 return(ENODEV); 841 842 s = splzs(); 843 if((userbits & TIOCFLAG_SOFTCAR)) { 844 cs->cs_softcar = 1; /* turn on softcar */ 845 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 846 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 847 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 848 } 849 else if(userbits & TIOCFLAG_CLOCAL) { 850 cs->cs_softcar = 0; /* turn off softcar */ 851 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 852 cs->cs_creg[15] |= ZSWR15_DCD_IE; 853 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 854 tp->t_termios.c_cflag |= CLOCAL; 855 } 856 if(userbits & TIOCFLAG_CRTSCTS) { 857 cs->cs_preg[15] |= ZSWR15_CTS_IE; 858 cs->cs_creg[15] |= ZSWR15_CTS_IE; 859 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 860 cs->cs_preg[3] |= ZSWR3_HFC; 861 cs->cs_creg[3] |= ZSWR3_HFC; 862 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 863 tp->t_termios.c_cflag |= CRTSCTS; 864 } 865 else { 866 /* no mdmbuf, so we must want software flow control */ 867 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 868 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 869 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 870 cs->cs_preg[3] &= ~ZSWR3_HFC; 871 cs->cs_creg[3] &= ~ZSWR3_HFC; 872 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 873 tp->t_termios.c_cflag &= ~CRTSCTS; 874 } 875 splx(s); 876 break; 877 } 878 case TIOCSDTR: 879 zs_modem(cs, ZSWR5_DTR, DMBIS); 880 break; 881 case TIOCCDTR: 882 zs_modem(cs, ZSWR5_DTR, DMBIC); 883 break; 884 case TIOCMGET: 885 zs_modem(cs, 0, DMGET); 886 break; 887 case TIOCMSET: 888 case TIOCMBIS: 889 case TIOCMBIC: 890 default: 891 return (ENOTTY); 892 } 893 return (0); 894} 895 896/* 897 * Start or restart transmission. 898 */ 899static void 900zsstart(tp) 901register struct tty *tp; 902{ 903 register struct zs_chanstate *cs; 904 register int s, nch; 905 int unit = ZS_UNIT(tp->t_dev); 906 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 907 908 cs = &zi->zi_cs[unit & 1]; 909 s = spltty(); 910 911 /* 912 * If currently active or delaying, no need to do anything. 913 */ 914 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 915 goto out; 916 917 /* 918 * If there are sleepers, and output has drained below low 919 * water mark, awaken. 920 */ 921 if(tp->t_outq.c_cc <= tp->t_lowat) { 922 if(tp->t_state & TS_ASLEEP) { 923 tp->t_state &= ~TS_ASLEEP; 924 wakeup((caddr_t)&tp->t_outq); 925 } 926 selwakeup(&tp->t_wsel); 927 } 928 929 nch = ndqb(&tp->t_outq, 0); /* XXX */ 930 if(nch) { 931 register char *p = tp->t_outq.c_cf; 932 933 /* mark busy, enable tx done interrupts, & send first byte */ 934 tp->t_state |= TS_BUSY; 935 (void) splzs(); 936 cs->cs_preg[1] |= ZSWR1_TIE; 937 cs->cs_creg[1] |= ZSWR1_TIE; 938 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 939 cs->cs_zc->zc_data = *p; 940 cs->cs_tba = p + 1; 941 cs->cs_tbc = nch - 1; 942 } else { 943 /* 944 * Nothing to send, turn off transmit done interrupts. 945 * This is useful if something is doing polled output. 946 */ 947 (void) splzs(); 948 cs->cs_preg[1] &= ~ZSWR1_TIE; 949 cs->cs_creg[1] &= ~ZSWR1_TIE; 950 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 951 } 952out: 953 splx(s); 954} 955 956/* 957 * Stop output, e.g., for ^S or output flush. 958 */ 959void 960zsstop(tp, flag) 961register struct tty *tp; 962 int flag; 963{ 964 register struct zs_chanstate *cs; 965 register int s, unit = ZS_UNIT(tp->t_dev); 966 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 967 968 cs = &zi->zi_cs[unit & 1]; 969 s = splzs(); 970 if(tp->t_state & TS_BUSY) { 971 /* 972 * Device is transmitting; must stop it. 973 */ 974 cs->cs_tbc = 0; 975 if ((tp->t_state & TS_TTSTOP) == 0) 976 tp->t_state |= TS_FLUSH; 977 } 978 splx(s); 979} 980 981/* 982 * Set ZS tty parameters from termios. 983 * 984 * This routine makes use of the fact that only registers 985 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 986 */ 987static int 988zsparam(tp, t) 989register struct tty *tp; 990register struct termios *t; 991{ 992 int unit = ZS_UNIT(tp->t_dev); 993 struct zs_softc *zi = zscd.cd_devs[unit >> 1]; 994 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 995 int cdiv, clkm, brgm, tcon; 996 register int tmp, tmp5, cflag, s; 997 998 tmp = t->c_ospeed; 999 tmp5 = t->c_ispeed; 1000 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1001 return(EINVAL); 1002 if(tmp == 0) { 1003 /* stty 0 => drop DTR and RTS */ 1004 zs_modem(cs, 0, DMSET); 1005 return(0); 1006 } 1007 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1008 if (tmp < 0) 1009 return(EINVAL); 1010 tp->t_ispeed = tp->t_ospeed = tmp; 1011 1012 cflag = tp->t_cflag = t->c_cflag; 1013 if (cflag & CSTOPB) 1014 cdiv |= ZSWR4_TWOSB; 1015 else 1016 cdiv |= ZSWR4_ONESB; 1017 if (!(cflag & PARODD)) 1018 cdiv |= ZSWR4_EVENP; 1019 if (cflag & PARENB) 1020 cdiv |= ZSWR4_PARENB; 1021 1022 switch(cflag & CSIZE) { 1023 case CS5: 1024 tmp = ZSWR3_RX_5; 1025 tmp5 = ZSWR5_TX_5; 1026 break; 1027 case CS6: 1028 tmp = ZSWR3_RX_6; 1029 tmp5 = ZSWR5_TX_6; 1030 break; 1031 case CS7: 1032 tmp = ZSWR3_RX_7; 1033 tmp5 = ZSWR5_TX_7; 1034 break; 1035 case CS8: 1036 default: 1037 tmp = ZSWR3_RX_8; 1038 tmp5 = ZSWR5_TX_8; 1039 break; 1040 } 1041 tmp |= ZSWR3_RX_ENABLE; 1042 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1043 1044 /* 1045 * Block interrupts so that state will not 1046 * be altered until we are done setting it up. 1047 */ 1048 s = splzs(); 1049 cs->cs_preg[4] = cdiv; 1050 cs->cs_preg[11] = clkm; 1051 cs->cs_preg[12] = tcon; 1052 cs->cs_preg[13] = tcon >> 8; 1053 cs->cs_preg[14] = brgm; 1054 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1055 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1056 cs->cs_preg[10] = ZSWR10_NRZ; 1057 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1058 1059 /* 1060 * Output hardware flow control on the chip is horrendous: if 1061 * carrier detect drops, the receiver is disabled. Hence we 1062 * can only do this when the carrier is on. 1063 */ 1064 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1065 tmp |= ZSWR3_HFC; 1066 cs->cs_preg[3] = tmp; 1067 cs->cs_preg[5] = tmp5; 1068 1069 /* 1070 * If nothing is being transmitted, set up new current values, 1071 * else mark them as pending. 1072 */ 1073 if(cs->cs_heldchange == 0) { 1074 if (cs->cs_ttyp->t_state & TS_BUSY) { 1075 cs->cs_heldtbc = cs->cs_tbc; 1076 cs->cs_tbc = 0; 1077 cs->cs_heldchange = 1; 1078 } else { 1079 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1080 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1081 } 1082 } 1083 splx(s); 1084 return (0); 1085} 1086 1087/* 1088 * search for the best matching baudrate 1089 */ 1090static int 1091zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1092int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1093{ 1094 int bestdiff, bestbps, source; 1095 1096 unit = (unit & 1) << 2; 1097 for (source = 0; source < 4; ++source) { 1098 long freq = zs_frequencies[unit + source]; 1099 int diff, bps, div, clkm, brgm, tcon; 1100 switch (source) { 1101 case 0: /* BRgen, PCLK */ 1102 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1103 break; 1104 case 1: /* BRgen, RTxC */ 1105 brgm = ZSWR14_BAUD_ENA; 1106 break; 1107 case 2: /* RTxC */ 1108 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1109 break; 1110 case 3: /* TRxC */ 1111 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1112 break; 1113 } 1114 switch (source) { 1115 case 0: 1116 case 1: 1117 div = ZSWR4_CLK_X16; 1118 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1119 tcon = BPS_TO_TCONST(freq, wanted); 1120 if (tcon < 0) 1121 tcon = 0; 1122 bps = TCONST_TO_BPS(freq, tcon); 1123 break; 1124 case 2: 1125 case 3: 1126 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1127 int b2 = freq / 32, d2 = abs(b2 - wanted); 1128 int b3 = freq / 64, d3 = abs(b3 - wanted); 1129 1130 if (d1 < d2 && d1 < d3) { 1131 div = ZSWR4_CLK_X16; 1132 bps = b1; 1133 } else if (d2 < d3 && d2 < d1) { 1134 div = ZSWR4_CLK_X32; 1135 bps = b2; 1136 } else { 1137 div = ZSWR4_CLK_X64; 1138 bps = b3; 1139 } 1140 brgm = tcon = 0; 1141 break; 1142 } 1143 } 1144 diff = abs(bps - wanted); 1145 if (!source || diff < bestdiff) { 1146 *divisor = div; 1147 *clockmode = clkm; 1148 *brgenmode = brgm; 1149 *timeconst = tcon; 1150 bestbps = bps; 1151 bestdiff = diff; 1152 if (diff == 0) 1153 break; 1154 } 1155 } 1156 /* Allow deviations upto 5% */ 1157 if (20 * bestdiff > wanted) 1158 return -1; 1159 return bestbps; 1160} 1161 1162/* 1163 * Raise or lower modem control (DTR/RTS) signals. If a character is 1164 * in transmission, the change is deferred. 1165 */ 1166static int 1167zs_modem(cs, bits, how) 1168struct zs_chanstate *cs; 1169int bits, how; 1170{ 1171 int s, mbits; 1172 1173 bits &= ZSWR5_DTR | ZSWR5_RTS; 1174 1175 s = splzs(); 1176 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1177 1178 switch(how) { 1179 case DMSET: 1180 mbits = bits; 1181 break; 1182 case DMBIS: 1183 mbits |= bits; 1184 break; 1185 case DMBIC: 1186 mbits &= ~bits; 1187 break; 1188 case DMGET: 1189 splx(s); 1190 return(mbits); 1191 } 1192 1193 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1194 if(cs->cs_heldchange == 0) { 1195 if(cs->cs_ttyp->t_state & TS_BUSY) { 1196 cs->cs_heldtbc = cs->cs_tbc; 1197 cs->cs_tbc = 0; 1198 cs->cs_heldchange = 1; 1199 } 1200 else { 1201 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1202 } 1203 } 1204 splx(s); 1205 return(0); 1206} 1207 1208/* 1209 * Write the given register set to the given zs channel in the proper order. 1210 * The channel must not be transmitting at the time. The receiver will 1211 * be disabled for the time it takes to write all the registers. 1212 */ 1213static void 1214zs_loadchannelregs(zc, reg) 1215volatile struct zschan *zc; 1216u_char *reg; 1217{ 1218 int i; 1219 1220 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1221 i = zc->zc_data; /* drain fifo */ 1222 i = zc->zc_data; 1223 i = zc->zc_data; 1224 ZS_WRITE(zc, 4, reg[4]); 1225 ZS_WRITE(zc, 10, reg[10]); 1226 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1227 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1228 ZS_WRITE(zc, 1, reg[1]); 1229 ZS_WRITE(zc, 9, reg[9]); 1230 ZS_WRITE(zc, 11, reg[11]); 1231 ZS_WRITE(zc, 12, reg[12]); 1232 ZS_WRITE(zc, 13, reg[13]); 1233 ZS_WRITE(zc, 14, reg[14]); 1234 ZS_WRITE(zc, 15, reg[15]); 1235 ZS_WRITE(zc, 3, reg[3]); 1236 ZS_WRITE(zc, 5, reg[5]); 1237} 1238#endif /* NZS > 1 */ 1239