1/*	$NetBSD: i80312_pci.c,v 1.20 2022/09/27 06:36:43 skrll Exp $	*/
2
3/*
4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for i80312 Companion I/O chip.
40 */
41
42#include <sys/cdefs.h>
43__KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.20 2022/09/27 06:36:43 skrll Exp $");
44
45#include "opt_pci.h"
46#include "pci.h"
47
48#include <sys/param.h>
49#include <sys/systm.h>
50#include <sys/device.h>
51#include <sys/bus.h>
52
53#include <uvm/uvm_extern.h>
54
55#include <dev/pci/pcivar.h>
56#include <dev/pci/pciconf.h>
57#include <dev/pci/ppbreg.h>
58
59#include <arm/locore.h>
60
61#include <arm/xscale/i80312reg.h>
62#include <arm/xscale/i80312var.h>
63
64void		i80312_pci_attach_hook(device_t, device_t,
65		    struct pcibus_attach_args *);
66int		i80312_pci_bus_maxdevs(void *, int);
67pcitag_t	i80312_pci_make_tag(void *, int, int, int);
68void		i80312_pci_decompose_tag(void *, pcitag_t, int *, int *,
69		    int *);
70pcireg_t	i80312_pci_conf_read(void *, pcitag_t, int);
71void		i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t);
72void		i80312_pci_conf_interrupt(void *, int, int, int, int, int *);
73
74#define	PCI_CONF_LOCK(s)	(s) = disable_interrupts(I32_bit)
75#define	PCI_CONF_UNLOCK(s)	restore_interrupts((s))
76
77void
78i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
79{
80#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
81	struct i80312_softc *sc = cookie;
82	struct pciconf_resources *pcires;
83	pcireg_t binfo;
84	int sbus;
85#endif
86
87	pc->pc_conf_v = cookie;
88	pc->pc_attach_hook = i80312_pci_attach_hook;
89	pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
90	pc->pc_make_tag = i80312_pci_make_tag;
91	pc->pc_decompose_tag = i80312_pci_decompose_tag;
92	pc->pc_conf_read = i80312_pci_conf_read;
93	pc->pc_conf_write = i80312_pci_conf_write;
94	pc->pc_conf_interrupt = i80312_pci_conf_interrupt;
95
96#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
97	/*
98	 * Configure the PCI bus.
99	 *
100	 * XXX We need to revisit this.  We only configure the Secondary
101	 * bus (and its children).  The bus configure code needs changes
102	 * to support how the busses are arranged on this chip.  We also
103	 * need to only configure devices in the private device space on
104	 * the Secondary bus.
105	 */
106
107	binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
108	/* pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo); */
109	sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo);
110
111	pcires = pciconf_resource_init();
112
113	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
114	    sc->sc_sioout_base, sc->sc_sioout_size);
115	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
116	    sc->sc_smemout_base, sc->sc_smemout_size);
117
118	aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
119	pci_configure_bus(pc, pcires, sbus, arm_dcache_align);
120
121	pciconf_resource_fini(pcires);
122#endif
123}
124
125void
126i80312_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p)
127{
128}
129
130void
131i80312_pci_attach_hook(device_t parent, device_t self,
132    struct pcibus_attach_args *pba)
133{
134
135	/* Nothing to do. */
136}
137
138int
139i80312_pci_bus_maxdevs(void *v, int busno)
140{
141
142	return (32);
143}
144
145pcitag_t
146i80312_pci_make_tag(void *v, int b, int d, int f)
147{
148
149	return ((b << 16) | (d << 11) | (f << 8));
150}
151
152void
153i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
154{
155
156	if (bp != NULL)
157		*bp = (tag >> 16) & 0xff;
158	if (dp != NULL)
159		*dp = (tag >> 11) & 0x1f;
160	if (fp != NULL)
161		*fp = (tag >> 8) & 0x7;
162}
163
164struct pciconf_state {
165	bus_addr_t ps_addr_reg;
166	bus_addr_t ps_data_reg;
167	bus_addr_t ps_csr_reg;
168	uint32_t ps_addr_val;
169
170	int ps_b, ps_d, ps_f;
171};
172
173static int
174i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset,
175    struct pciconf_state *ps)
176{
177	pcireg_t binfo;
178	int pbus, sbus;
179
180	if ((unsigned int)offset >= PCI_CONF_SIZE)
181		return (1);
182
183	i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
184
185	binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
186	pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo);
187	sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo);
188
189	/*
190	 * If the bus # is the Primary bus #, use the Primary
191	 * Address/Data registers, otherwise use the Secondary
192	 * Address/Data registers.
193	 */
194	if (ps->ps_b == pbus) {
195		ps->ps_addr_reg = I80312_ATU_POCCA;
196		ps->ps_data_reg = I80312_ATU_POCCD;
197		ps->ps_csr_reg = PCI_COMMAND_STATUS_REG;
198	} else {
199		ps->ps_addr_reg = I80312_ATU_SOCCA;
200		ps->ps_data_reg = I80312_ATU_SOCCD;
201		ps->ps_csr_reg = I80312_ATU_SACS;
202	}
203
204	/*
205	 * If the bus # is the Primary or Secondary bus #, then use
206	 * Type 0 cycles, else use Type 1.
207	 *
208	 * XXX We should filter out all non-private devices here!
209	 * XXX How does private space interact with PCI-PCI bridges?
210	 */
211	if (ps->ps_b == pbus || ps->ps_b == sbus) {
212		if (ps->ps_d > (31 - 11))
213			return (1);
214		ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) |
215		    offset;
216	} else {
217		/* The tag is already in the correct format. */
218		ps->ps_addr_val = tag | offset | 1;
219	}
220
221	return (0);
222}
223
224pcireg_t
225i80312_pci_conf_read(void *v, pcitag_t tag, int offset)
226{
227	struct i80312_softc *sc = v;
228	struct pciconf_state ps;
229	vaddr_t va;
230	pcireg_t rv;
231	u_int s;
232
233	if (i80312_pci_conf_setup(sc, tag, offset, &ps))
234		return ((pcireg_t) -1);
235
236	PCI_CONF_LOCK(s);
237
238	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
239	    ps.ps_addr_val);
240
241	va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
242	if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) {
243		/*
244		 * Clear the Master Abort by reading the PCI
245		 * Status Register.
246		 */
247		(void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
248		    ps.ps_csr_reg);
249#if 0
250		printf("conf_read: %d/%d/%d bad address\n",
251		    ps.ps_b, ps.ps_d, ps.ps_f);
252#endif
253		rv = (pcireg_t) -1;
254	}
255
256	PCI_CONF_UNLOCK(s);
257
258	return (rv);
259}
260
261void
262i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
263{
264	struct i80312_softc *sc = v;
265	struct pciconf_state ps;
266	u_int s;
267
268	if (i80312_pci_conf_setup(sc, tag, offset, &ps))
269		return;
270
271	PCI_CONF_LOCK(s);
272
273	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
274	    ps.ps_addr_val);
275	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val);
276
277	PCI_CONF_UNLOCK(s);
278}
279