vfp_init.c revision 1.61
1/* $NetBSD: vfp_init.c,v 1.61 2019/03/17 08:41:42 skrll Exp $ */ 2 3/* 4 * Copyright (c) 2008 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 25 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include "opt_cputypes.h" 33 34#include <sys/cdefs.h> 35__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.61 2019/03/17 08:41:42 skrll Exp $"); 36 37#include <sys/param.h> 38#include <sys/types.h> 39#include <sys/systm.h> 40#include <sys/device.h> 41#include <sys/proc.h> 42#include <sys/cpu.h> 43 44#include <arm/locore.h> 45#include <arm/pcb.h> 46#include <arm/undefined.h> 47#include <arm/vfpreg.h> 48#include <arm/mcontext.h> 49 50#include <uvm/uvm_extern.h> /* for pmap.h */ 51 52#ifdef FPU_VFP 53 54#ifdef CPU_CORTEX 55#define SETFPU __asm(".fpu\tvfpv4") 56#else 57#define SETFPU __asm(".fpu\tvfp") 58#endif 59SETFPU; 60 61/* FLDMD <X>, {d0-d15} */ 62static inline void 63load_vfpregs_lo(const uint64_t *p) 64{ 65 SETFPU; 66 __asm __volatile("vldmia\t%0, {d0-d15}" :: "r" (p) : "memory"); 67} 68 69/* FSTMD <X>, {d0-d15} */ 70static inline void 71save_vfpregs_lo(uint64_t *p) 72{ 73 SETFPU; 74 __asm __volatile("vstmia\t%0, {d0-d15}" :: "r" (p) : "memory"); 75} 76 77#ifdef CPU_CORTEX 78/* FLDMD <X>, {d16-d31} */ 79static inline void 80load_vfpregs_hi(const uint64_t *p) 81{ 82 SETFPU; 83 __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 84} 85 86/* FLDMD <X>, {d16-d31} */ 87static inline void 88save_vfpregs_hi(uint64_t *p) 89{ 90 SETFPU; 91 __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 92} 93#endif 94 95static inline void 96load_vfpregs(const struct vfpreg *fregs) 97{ 98 load_vfpregs_lo(fregs->vfp_regs); 99#ifdef CPU_CORTEX 100#ifdef CPU_ARM11 101 switch (curcpu()->ci_vfp_id) { 102 case FPU_VFP_CORTEXA5: 103 case FPU_VFP_CORTEXA7: 104 case FPU_VFP_CORTEXA8: 105 case FPU_VFP_CORTEXA9: 106 case FPU_VFP_CORTEXA15: 107 case FPU_VFP_CORTEXA15_QEMU: 108 case FPU_VFP_CORTEXA53: 109 case FPU_VFP_CORTEXA57: 110#endif 111 load_vfpregs_hi(fregs->vfp_regs); 112#ifdef CPU_ARM11 113 break; 114 } 115#endif 116#endif 117} 118 119static inline void 120save_vfpregs(struct vfpreg *fregs) 121{ 122 save_vfpregs_lo(fregs->vfp_regs); 123#ifdef CPU_CORTEX 124#ifdef CPU_ARM11 125 switch (curcpu()->ci_vfp_id) { 126 case FPU_VFP_CORTEXA5: 127 case FPU_VFP_CORTEXA7: 128 case FPU_VFP_CORTEXA8: 129 case FPU_VFP_CORTEXA9: 130 case FPU_VFP_CORTEXA15: 131 case FPU_VFP_CORTEXA15_QEMU: 132 case FPU_VFP_CORTEXA53: 133 case FPU_VFP_CORTEXA57: 134#endif 135 save_vfpregs_hi(fregs->vfp_regs); 136#ifdef CPU_ARM11 137 break; 138 } 139#endif 140#endif 141} 142 143/* The real handler for VFP bounces. */ 144static int vfp_handler(u_int, u_int, trapframe_t *, int); 145#ifdef CPU_CORTEX 146static int neon_handler(u_int, u_int, trapframe_t *, int); 147#endif 148 149static void vfp_state_load(lwp_t *, u_int); 150static void vfp_state_save(lwp_t *); 151static void vfp_state_release(lwp_t *); 152 153const pcu_ops_t arm_vfp_ops = { 154 .pcu_id = PCU_FPU, 155 .pcu_state_save = vfp_state_save, 156 .pcu_state_load = vfp_state_load, 157 .pcu_state_release = vfp_state_release, 158}; 159 160/* determine what bits can be changed */ 161uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM; 162/* default to run fast */ 163uint32_t vfp_fpscr_default = (VFP_FPSCR_DN | VFP_FPSCR_FZ | VFP_FPSCR_RN); 164 165/* 166 * Used to test for a VFP. The following function is installed as a coproc10 167 * handler on the undefined instruction vector and then we issue a VFP 168 * instruction. If undefined_test is non zero then the VFP did not handle 169 * the instruction so must be absent, or disabled. 170 */ 171 172static int undefined_test; 173 174static int 175vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code) 176{ 177 178 frame->tf_pc += INSN_SIZE; 179 ++undefined_test; 180 return 0; 181} 182 183#else 184/* determine what bits can be changed */ 185uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM|VFP_FPSCR_RMODE; 186#endif /* FPU_VFP */ 187 188static int 189vfp_fpscr_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 190{ 191 struct lwp * const l = curlwp; 192 const u_int regno = (insn >> 12) & 0xf; 193 /* 194 * Only match move to/from the FPSCR register and we 195 * can't be using the SP,LR,PC as a source. 196 */ 197 if ((insn & 0xffef0fff) != 0xeee10a10 || regno > 12) 198 return 1; 199 200 struct pcb * const pcb = lwp_getpcb(l); 201 202#ifdef FPU_VFP 203 /* 204 * If FPU is valid somewhere, let's just reenable VFP and 205 * retry the instruction (only safe thing to do since the 206 * pcb has a stale copy). 207 */ 208 if (pcb->pcb_vfp.vfp_fpexc & VFP_FPEXC_EN) 209 return 1; 210 211 if (__predict_false(!vfp_used_p(l))) { 212 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 213 } 214#endif 215 216 /* 217 * We now know the pcb has the saved copy. 218 */ 219 register_t * const regp = &frame->tf_r0 + regno; 220 if (insn & 0x00100000) { 221 *regp = pcb->pcb_vfp.vfp_fpscr; 222 } else { 223 pcb->pcb_vfp.vfp_fpscr &= ~vfp_fpscr_changable; 224 pcb->pcb_vfp.vfp_fpscr |= *regp & vfp_fpscr_changable; 225 } 226 227 curcpu()->ci_vfp_evs[0].ev_count++; 228 229 frame->tf_pc += INSN_SIZE; 230 return 0; 231} 232 233#ifndef FPU_VFP 234/* 235 * If we don't want VFP support, we still need to handle emulating VFP FPSCR 236 * instructions. 237 */ 238void 239vfp_attach(struct cpu_info *ci) 240{ 241 if (CPU_IS_PRIMARY(ci)) { 242 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 243 } 244 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_TRAP, NULL, 245 ci->ci_cpuname, "vfp fpscr traps"); 246} 247 248#else 249void 250vfp_attach(struct cpu_info *ci) 251{ 252 const char *model = NULL; 253 254 if (CPU_ID_ARM11_P(ci->ci_arm_cpuid) 255 || CPU_ID_MV88SV58XX_P(ci->ci_arm_cpuid) 256 || CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) { 257#if 0 258 const uint32_t nsacr = armreg_nsacr_read(); 259 const uint32_t nsacr_vfp = __BITS(VFP_COPROC,VFP_COPROC2); 260 if ((nsacr & nsacr_vfp) != nsacr_vfp) { 261 aprint_normal_dev(ci->ci_dev, 262 "VFP access denied (NSACR=%#x)\n", nsacr); 263 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 264 ci->ci_vfp_id = 0; 265 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 266 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 267 "vfp fpscr traps"); 268 return; 269 } 270#endif 271 const uint32_t cpacr_vfp = CPACR_CPn(VFP_COPROC); 272 const uint32_t cpacr_vfp2 = CPACR_CPn(VFP_COPROC2); 273 274 /* 275 * We first need to enable access to the coprocessors. 276 */ 277 uint32_t cpacr = armreg_cpacr_read(); 278 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp); 279 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2); 280 armreg_cpacr_write(cpacr); 281 282 arm_isb(); 283 284 /* 285 * If we could enable them, then they exist. 286 */ 287 cpacr = armreg_cpacr_read(); 288 bool vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) == CPACR_ALL 289 && __SHIFTOUT(cpacr, cpacr_vfp) == CPACR_ALL; 290 if (!vfp_p) { 291 aprint_normal_dev(ci->ci_dev, 292 "VFP access denied (CPACR=%#x)\n", cpacr); 293 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 294 ci->ci_vfp_id = 0; 295 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 296 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 297 "vfp fpscr traps"); 298 return; 299 } 300 } 301 302 void *uh = install_coproc_handler(VFP_COPROC, vfp_test); 303 304 undefined_test = 0; 305 306 const uint32_t fpsid = armreg_fpsid_read(); 307 308 remove_coproc_handler(uh); 309 310 if (undefined_test != 0) { 311 aprint_normal_dev(ci->ci_dev, "No VFP detected\n"); 312 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 313 ci->ci_vfp_id = 0; 314 return; 315 } 316 317 ci->ci_vfp_id = fpsid; 318 switch (fpsid & ~ VFP_FPSID_REV_MSK) { 319 case FPU_VFP10_ARM10E: 320 model = "VFP10 R1"; 321 break; 322 case FPU_VFP11_ARM11: 323 model = "VFP11"; 324 break; 325 case FPU_VFP_MV88SV58XX: 326 model = "VFP3"; 327 break; 328 case FPU_VFP_CORTEXA5: 329 case FPU_VFP_CORTEXA7: 330 case FPU_VFP_CORTEXA8: 331 case FPU_VFP_CORTEXA9: 332 case FPU_VFP_CORTEXA15: 333 case FPU_VFP_CORTEXA15_QEMU: 334 case FPU_VFP_CORTEXA53: 335 case FPU_VFP_CORTEXA57: 336 if (armreg_cpacr_read() & CPACR_V7_ASEDIS) { 337 model = "VFP 4.0+"; 338 } else { 339 model = "NEON MPE (VFP 3.0+)"; 340 cpu_neon_present = 1; 341 } 342 break; 343 default: 344 aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %#x\n", 345 fpsid); 346 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 347 vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM 348 |VFP_FPSCR_RMODE; 349 vfp_fpscr_default = 0; 350 return; 351 } 352 353 cpu_fpu_present = 1; 354 cpu_media_and_vfp_features[0] = armreg_mvfr0_read(); 355 cpu_media_and_vfp_features[1] = armreg_mvfr1_read(); 356 if (fpsid != 0) { 357 uint32_t f0 = armreg_mvfr0_read(); 358 uint32_t f1 = armreg_mvfr1_read(); 359 aprint_normal("vfp%d at %s: %s%s%s%s%s\n", 360 device_unit(ci->ci_dev), 361 device_xname(ci->ci_dev), 362 model, 363 ((f0 & ARM_MVFR0_ROUNDING_MASK) ? ", rounding" : ""), 364 ((f0 & ARM_MVFR0_EXCEPT_MASK) ? ", exceptions" : ""), 365 ((f1 & ARM_MVFR1_D_NAN_MASK) ? ", NaN propagation" : ""), 366 ((f1 & ARM_MVFR1_FTZ_MASK) ? ", denormals" : "")); 367 aprint_debug("vfp%d: mvfr: [0]=%#x [1]=%#x\n", 368 device_unit(ci->ci_dev), f0, f1); 369 if (CPU_IS_PRIMARY(ci)) { 370 if (f0 & ARM_MVFR0_ROUNDING_MASK) { 371 vfp_fpscr_changable |= VFP_FPSCR_RMODE; 372 } 373 if (f1 & ARM_MVFR0_EXCEPT_MASK) { 374 vfp_fpscr_changable |= VFP_FPSCR_ESUM; 375 } 376 // If hardware supports propagation of NaNs, select it. 377 if (f1 & ARM_MVFR1_D_NAN_MASK) { 378 vfp_fpscr_default &= ~VFP_FPSCR_DN; 379 vfp_fpscr_changable |= VFP_FPSCR_DN; 380 } 381 // If hardware supports denormalized numbers, use it. 382 if (cpu_media_and_vfp_features[1] & ARM_MVFR1_FTZ_MASK) { 383 vfp_fpscr_default &= ~VFP_FPSCR_FZ; 384 vfp_fpscr_changable |= VFP_FPSCR_FZ; 385 } 386 } 387 } 388 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_MISC, NULL, 389 ci->ci_cpuname, "vfp coproc use"); 390 evcnt_attach_dynamic(&ci->ci_vfp_evs[1], EVCNT_TYPE_MISC, NULL, 391 ci->ci_cpuname, "vfp coproc re-use"); 392 evcnt_attach_dynamic(&ci->ci_vfp_evs[2], EVCNT_TYPE_TRAP, NULL, 393 ci->ci_cpuname, "vfp coproc fault"); 394 install_coproc_handler(VFP_COPROC, vfp_handler); 395 install_coproc_handler(VFP_COPROC2, vfp_handler); 396#ifdef CPU_CORTEX 397 if (cpu_neon_present) 398 install_coproc_handler(CORE_UNKNOWN_HANDLER, neon_handler); 399#endif 400} 401 402/* The real handler for VFP bounces. */ 403static int 404vfp_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 405{ 406 struct cpu_info * const ci = curcpu(); 407 408 /* This shouldn't ever happen. */ 409 if (fault_code != FAULT_USER) 410 panic("VFP fault at %#x in non-user mode", frame->tf_pc); 411 412 if (ci->ci_vfp_id == 0) { 413 /* No VFP detected, just fault. */ 414 return 1; 415 } 416 417 /* 418 * If we already own the FPU and it's enabled (and no exception), raise 419 * SIGILL. If there is an exception, drop through to raise a SIGFPE. 420 */ 421 if (curcpu()->ci_pcu_curlwp[PCU_FPU] == curlwp 422 && (armreg_fpexc_read() & (VFP_FPEXC_EX|VFP_FPEXC_EN)) == VFP_FPEXC_EN) 423 return 1; 424 425 /* 426 * Make sure we own the FP. 427 */ 428 pcu_load(&arm_vfp_ops); 429 430 uint32_t fpexc = armreg_fpexc_read(); 431 if (fpexc & VFP_FPEXC_EX) { 432 ksiginfo_t ksi; 433 KASSERT(fpexc & VFP_FPEXC_EN); 434 435 curcpu()->ci_vfp_evs[2].ev_count++; 436 437 /* 438 * Need the clear the exception condition so any signal 439 * and future use can proceed. 440 */ 441 armreg_fpexc_write(fpexc & ~(VFP_FPEXC_EX|VFP_FPEXC_FSUM)); 442 443 pcu_save(&arm_vfp_ops, curlwp); 444 445 /* 446 * XXX Need to emulate bounce instructions here to get correct 447 * XXX exception codes, etc. 448 */ 449 KSI_INIT_TRAP(&ksi); 450 ksi.ksi_signo = SIGFPE; 451 if (fpexc & VFP_FPEXC_IXF) 452 ksi.ksi_code = FPE_FLTRES; 453 else if (fpexc & VFP_FPEXC_UFF) 454 ksi.ksi_code = FPE_FLTUND; 455 else if (fpexc & VFP_FPEXC_OFF) 456 ksi.ksi_code = FPE_FLTOVF; 457 else if (fpexc & VFP_FPEXC_DZF) 458 ksi.ksi_code = FPE_FLTDIV; 459 else if (fpexc & VFP_FPEXC_IOF) 460 ksi.ksi_code = FPE_FLTINV; 461 ksi.ksi_addr = (uint32_t *)address; 462 ksi.ksi_trap = 0; 463 trapsignal(curlwp, &ksi); 464 return 0; 465 } 466 467 /* Need to restart the faulted instruction. */ 468// frame->tf_pc -= INSN_SIZE; 469 return 0; 470} 471 472#ifdef CPU_CORTEX 473/* The real handler for NEON bounces. */ 474static int 475neon_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 476{ 477 struct cpu_info * const ci = curcpu(); 478 479 if (ci->ci_vfp_id == 0) 480 /* No VFP detected, just fault. */ 481 return 1; 482 483 if ((insn & 0xfe000000) != 0xf2000000 484 && (insn & 0xfe000000) != 0xf4000000) 485 /* Not NEON instruction, just fault. */ 486 return 1; 487 488 /* This shouldn't ever happen. */ 489 if (fault_code != FAULT_USER) 490 panic("NEON fault in non-user mode"); 491 492 /* if we already own the FPU and it's enabled, raise SIGILL */ 493 if (curcpu()->ci_pcu_curlwp[PCU_FPU] == curlwp 494 && (armreg_fpexc_read() & VFP_FPEXC_EN) != 0) 495 return 1; 496 497 pcu_load(&arm_vfp_ops); 498 499 /* Need to restart the faulted instruction. */ 500// frame->tf_pc -= INSN_SIZE; 501 return 0; 502} 503#endif 504 505static void 506vfp_state_load(lwp_t *l, u_int flags) 507{ 508 struct pcb * const pcb = lwp_getpcb(l); 509 struct vfpreg * const fregs = &pcb->pcb_vfp; 510 511 /* 512 * Instrument VFP usage -- if a process has not previously 513 * used the VFP, mark it as having used VFP for the first time, 514 * and count this event. 515 * 516 * If a process has used the VFP, count a "used VFP, and took 517 * a trap to use it again" event. 518 */ 519 if (__predict_false((flags & PCU_VALID) == 0)) { 520 curcpu()->ci_vfp_evs[0].ev_count++; 521 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 522 } else { 523 curcpu()->ci_vfp_evs[1].ev_count++; 524 } 525 526 KASSERT((armreg_fpexc_read() & VFP_FPEXC_EN) == 0); 527 /* 528 * If the VFP is already enabled we must be bouncing an instruction. 529 */ 530 if (flags & PCU_REENABLE) { 531 uint32_t fpexc = armreg_fpexc_read(); 532 armreg_fpexc_write(fpexc | VFP_FPEXC_EN); 533 fregs->vfp_fpexc |= VFP_FPEXC_EN; 534 return; 535 } 536 KASSERT((fregs->vfp_fpexc & VFP_FPEXC_EN) == 0); 537 538 /* 539 * Load and Enable the VFP (so that we can write the registers). 540 */ 541 fregs->vfp_fpexc |= VFP_FPEXC_EN; 542 armreg_fpexc_write(fregs->vfp_fpexc); 543 KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == NULL); 544 KASSERT(l->l_pcu_cpu[PCU_FPU] == NULL); 545 546 load_vfpregs(fregs); 547 armreg_fpscr_write(fregs->vfp_fpscr); 548 549 if (fregs->vfp_fpexc & VFP_FPEXC_EX) { 550 /* Need to restore the exception handling state. */ 551 armreg_fpinst_write(fregs->vfp_fpinst); 552 if (fregs->vfp_fpexc & VFP_FPEXC_FP2V) 553 armreg_fpinst2_write(fregs->vfp_fpinst2); 554 } 555} 556 557void 558vfp_state_save(lwp_t *l) 559{ 560 struct pcb * const pcb = lwp_getpcb(l); 561 struct vfpreg * const fregs = &pcb->pcb_vfp; 562 uint32_t fpexc = armreg_fpexc_read(); 563 564 KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == l); 565 KASSERT(curcpu() == l->l_pcu_cpu[PCU_FPU]); 566 KASSERT(curlwp == l || curlwp->l_pcu_cpu[PCU_FPU] != curcpu()); 567 /* 568 * Enable the VFP (so we can read the registers). 569 * Make sure the exception bit is cleared so that we can 570 * safely dump the registers. 571 */ 572 armreg_fpexc_write((fpexc | VFP_FPEXC_EN) & ~VFP_FPEXC_EX); 573 574 fregs->vfp_fpexc = fpexc; 575 if (fpexc & VFP_FPEXC_EX) { 576 /* Need to save the exception handling state */ 577 fregs->vfp_fpinst = armreg_fpinst_read(); 578 if (fpexc & VFP_FPEXC_FP2V) 579 fregs->vfp_fpinst2 = armreg_fpinst2_read(); 580 } 581 fregs->vfp_fpscr = armreg_fpscr_read(); 582 save_vfpregs(fregs); 583 584 /* Disable the VFP. */ 585 armreg_fpexc_write(fpexc & ~VFP_FPEXC_EN); 586} 587 588void 589vfp_state_release(lwp_t *l) 590{ 591 struct pcb * const pcb = lwp_getpcb(l); 592 593 /* 594 * Now mark the VFP as disabled (and our state 595 * has been already saved or is being discarded). 596 */ 597 pcb->pcb_vfp.vfp_fpexc &= ~VFP_FPEXC_EN; 598 599 /* 600 * Turn off the FPU so the next time a VFP instruction is issued 601 * an exception happens. We don't know if this LWP's state was 602 * loaded but if we turned off the FPU for some other LWP, when 603 * pcu_load invokes vfp_state_load it will see that VFP_FPEXC_EN 604 * is still set so it just restore fpexc and return since its 605 * contents are still sitting in the VFP. 606 */ 607 armreg_fpexc_write(armreg_fpexc_read() & ~VFP_FPEXC_EN); 608} 609 610void 611vfp_savecontext(lwp_t *l) 612{ 613 pcu_save(&arm_vfp_ops, l); 614} 615 616void 617vfp_discardcontext(lwp_t *l, bool used_p) 618{ 619 pcu_discard(&arm_vfp_ops, l, used_p); 620} 621 622bool 623vfp_used_p(const lwp_t *l) 624{ 625 return pcu_valid_p(&arm_vfp_ops, l); 626} 627 628void 629vfp_getcontext(struct lwp *l, mcontext_t *mcp, int *flagsp) 630{ 631 if (vfp_used_p(l)) { 632 const struct pcb * const pcb = lwp_getpcb(l); 633 634 pcu_save(&arm_vfp_ops, l); 635 mcp->__fpu.__vfpregs.__vfp_fpscr = pcb->pcb_vfp.vfp_fpscr; 636 memcpy(mcp->__fpu.__vfpregs.__vfp_fstmx, pcb->pcb_vfp.vfp_regs, 637 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 638 *flagsp |= _UC_FPU|_UC_ARM_VFP; 639 } 640} 641 642void 643vfp_setcontext(struct lwp *l, const mcontext_t *mcp) 644{ 645 struct pcb * const pcb = lwp_getpcb(l); 646 647 pcu_discard(&arm_vfp_ops, l, true); 648 pcb->pcb_vfp.vfp_fpscr = mcp->__fpu.__vfpregs.__vfp_fpscr; 649 memcpy(pcb->pcb_vfp.vfp_regs, mcp->__fpu.__vfpregs.__vfp_fstmx, 650 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 651} 652 653#endif /* FPU_VFP */ 654