vexpress_platform.c revision 1.3 
1/* $NetBSD: vexpress_platform.c,v 1.3 2017/06/06 09:56:57 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "opt_multiprocessor.h"
30#include "opt_fdt_arm.h"
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.3 2017/06/06 09:56:57 jmcneill Exp $");
34
35#include <sys/param.h>
36#include <sys/bus.h>
37#include <sys/cpu.h>
38#include <sys/device.h>
39#include <sys/termios.h>
40
41#include <dev/fdt/fdtvar.h>
42
43#include <uvm/uvm_extern.h>
44
45#include <machine/bootconfig.h>
46#include <arm/cpufunc.h>
47
48#include <arm/fdt/arm_fdtvar.h>
49
50#include <arm/cortex/gtmr_var.h>
51
52#include <arm/cortex/gic_reg.h>
53
54#include <evbarm/dev/plcomvar.h>
55
56#include <arm/vexpress/vexpress_platform.h>
57
58#include <libfdt.h>
59
60#define	VEXPRESS_CLCD_NODE_PATH	\
61	"/smb@08000000/motherboard/iofpga@3,00000000/clcd@1f0000"
62#define	VEXPRESS_REF_FREQ	24000000
63
64#define	DEVMAP_ALIGN(a)	((a) & ~L1_S_OFFSET)
65#define	DEVMAP_SIZE(s)	roundup2((s), L1_S_SIZE)
66#define	DEVMAP_ENTRY(va, pa, sz)			\
67	{						\
68		.pd_va = DEVMAP_ALIGN(va),		\
69		.pd_pa = DEVMAP_ALIGN(pa),		\
70		.pd_size = DEVMAP_SIZE(sz),		\
71		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
72		.pd_cache = PTE_NOCACHE			\
73	}
74#define	DEVMAP_ENTRY_END	{ 0 }
75
76extern struct bus_space armv7_generic_bs_tag;
77extern struct bus_space armv7_generic_a4x_bs_tag;
78extern struct arm32_bus_dma_tag armv7_generic_dma_tag;
79
80#define	SYSREG_BASE		0x1c010000
81#define	SYSREG_SIZE		0x1000
82
83#define	SYS_FLAGS		0x0030
84#define	SYS_FLAGSCLR		0x0034
85#define	SYS_CFGDATA		0x00a0
86#define	SYS_CFGCTRL		0x00a4
87#define	 SYS_CFGCTRL_START	__BIT(31)
88#define	 SYS_CFGCTRL_WRITE	__BIT(30)
89#define	 SYS_CFGCTRL_DCC	__BITS(29,26)
90#define	 SYS_CFGCTRL_FUNCTION	__BITS(25,20)
91#define	  SYS_CFGCTRL_FUNCTION_SHUTDOWN	8
92#define	  SYS_CFGCTRL_FUNCTION_REBOOT	9
93#define	 SYS_CFGCTRL_SITE	__BITS(17,16)
94#define	 SYS_CFGCTRL_POSITION	__BITS(15,12)
95#define	 SYS_CFGCTRL_DEVICE	__BITS(11,0)
96#define	SYS_CFGSTAT		0x00a8
97#define	 SYS_CFGSTAT_ERROR	__BIT(1)
98#define	 SYS_CFGSTAT_COMPLETE	__BIT(0)
99
100static bus_space_tag_t sysreg_bst = &armv7_generic_bs_tag;
101static bus_space_handle_t sysreg_bsh;
102
103#define	SYSREG_WRITE(o, v)	\
104	bus_space_write_4(sysreg_bst, sysreg_bsh, (o), (v))
105
106
107static void
108vexpress_a15_smp_init(void)
109{
110	extern void cortex_mpstart(void);
111	bus_space_tag_t gicd_bst = &armv7_generic_bs_tag;
112	bus_space_handle_t gicd_bsh;
113	int started = 0;
114
115	/* Bitmask of CPUs (non-BSP) to start */
116	for (int i = 1; i < arm_cpu_max; i++)
117		started |= __BIT(i);
118
119	/* Write init vec to SYS_FLAGS register */
120	SYSREG_WRITE(SYS_FLAGSCLR, 0xffffffff);
121	SYSREG_WRITE(SYS_FLAGS, (uint32_t)cortex_mpstart);
122
123	/* Map GIC distributor */
124	bus_space_map(gicd_bst, VEXPRESS_GIC_PBASE + GICD_BASE,
125	    0x1000, 0, &gicd_bsh);
126
127	/* Enable GIC distributor */
128	bus_space_write_4(gicd_bst, gicd_bsh,
129	    GICD_CTRL, GICD_CTRL_Enable);
130
131	/* Send sw interrupt to APs */
132	const uint32_t sgir = GICD_SGIR_TargetListFilter_NotMe;
133	bus_space_write_4(gicd_bst, gicd_bsh, GICD_SGIR, sgir);
134
135	/* Wait for APs to start */
136	for (u_int i = 0x10000000; i > 0; i--) {
137		arm_dmb();
138		if (arm_cpu_hatched == started)
139			break;
140	}
141
142	/* Disable GIC distributor */
143	bus_space_write_4(gicd_bst, gicd_bsh, GICD_CTRL, 0);
144}
145
146
147static const struct pmap_devmap *
148vexpress_platform_devmap(void)
149{
150	static const struct pmap_devmap devmap[] = {
151		DEVMAP_ENTRY(VEXPRESS_CORE_VBASE,
152			     VEXPRESS_CORE_PBASE,
153			     VEXPRESS_CORE_SIZE),
154		DEVMAP_ENTRY(VEXPRESS_GIC_VBASE,
155			     VEXPRESS_GIC_PBASE,
156			     VEXPRESS_GIC_SIZE),
157		DEVMAP_ENTRY_END
158	};
159
160	return devmap;
161}
162
163static void
164vexpress_platform_bootstrap(void)
165{
166	bus_space_map(sysreg_bst, SYSREG_BASE, SYSREG_SIZE, 0,
167	    &sysreg_bsh);
168
169	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
170
171	vexpress_a15_smp_init();
172
173	if (match_bootconf_option(boot_args, "console", "fb")) {
174		void *fdt_data = __UNCONST(fdtbus_get_data());
175		const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
176		if (chosen_off >= 0)
177			fdt_setprop_string(fdt_data, chosen_off, "stdout-path",
178			    VEXPRESS_CLCD_NODE_PATH);
179	}
180}
181
182static void
183vexpress_platform_init_attach_args(struct fdt_attach_args *faa)
184{
185	faa->faa_bst = &armv7_generic_bs_tag;
186	faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
187	faa->faa_dmat = &armv7_generic_dma_tag;
188}
189
190static void
191vexpress_platform_early_putchar(char c)
192{
193}
194
195static void
196vexpress_platform_device_register(device_t self, void *aux)
197{
198}
199
200static void
201vexpress_platform_reset(void)
202{
203	SYSREG_WRITE(SYS_CFGSTAT, 0);
204	SYSREG_WRITE(SYS_CFGDATA, 0);
205	SYSREG_WRITE(SYS_CFGCTRL,
206	    SYS_CFGCTRL_START |
207	    SYS_CFGCTRL_WRITE |
208	    __SHIFTIN(SYS_CFGCTRL_FUNCTION_REBOOT,
209		      SYS_CFGCTRL_FUNCTION));
210}
211
212static u_int
213vexpress_platform_uart_freq(void)
214{
215	return VEXPRESS_REF_FREQ;
216}
217
218static const struct arm_platform vexpress_platform = {
219	.devmap = vexpress_platform_devmap,
220	.bootstrap = vexpress_platform_bootstrap,
221	.init_attach_args = vexpress_platform_init_attach_args,
222	.early_putchar = vexpress_platform_early_putchar,
223	.device_register = vexpress_platform_device_register,
224	.reset = vexpress_platform_reset,
225	.delay = gtmr_delay,
226	.uart_freq = vexpress_platform_uart_freq,
227};
228
229ARM_PLATFORM(vexpress, "arm,vexpress", &vexpress_platform);
230