ti_iicreg.h revision 1.2 
1/*	$NetBSD: ti_iicreg.h,v 1.2 2019/10/29 10:54:10 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2013 Manuel Bouyer.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/* register definitions for the i2c controller found in the
28 * Texas Instrument AM335x SOC
29 */
30
31#ifndef _OMAP2IICREG_H
32#define _OMAP2IICREG_H
33
34#define OMAP2_I2C_REVNB_LO		0x00
35#define		I2C_REVNB_LO_RTL(x)		(((x) >> 11) & 0x01f)
36#define		I2C_REVNB_LO_MAJOR(x)		(((x) >>  8) & 0x007)
37#define		I2C_REVNB_LO_CUSTOM(x)		(((x) >>  6) & 0x003)
38#define		I2C_REVNB_LO_MINOR(x)		(((x) >>  0) & 0x01f)
39#define		I2C_REV_SCHEME_0_MAJOR(r)	(((r) >> 4) && 0xf)
40#define		I2C_REV_SCHEME_0_MINOR(r)	(((r) >> 0) && 0xf)
41#define OMAP2_I2C_REVNB_HI		0x04
42#define		I2C_REVNB_HI_SCHEME(x)		(((x) >> 14) & 0x003)
43#define		I2C_REVNB_HI_FUNC(x)		(((x) >>  0) & 0xfff)
44#define OMAP2_I2C_SYSC			0x10
45#define		I2C_SYSC_CLKACTIVITY_OCP	0x0010
46#define		I2C_SYSC_CLKACTIVITY_SYSTEM	0x0020
47#define		I2C_SYSC_IDLE_MASK		0x0018
48#define		I2C_SYSC_IDLE_FORCE		0x0000
49#define		I2C_SYSC_IDLE_SMART		0x0010
50#define		I2C_SYSC_IDLE_NONE		0x0008
51#define		I2C_SYSC_ENAWAKEUP		0x0004
52#define		I2C_SYSC_SRST			0x0002
53#define		I2C_SYSC_AUTOIDLE		0x0001
54#define OMAP2_I2C_IRQSTATUS_RAW		0x24
55#define OMAP2_I2C_IRQSTATUS		0x28
56#define OMAP2_I2C_IRQENABLE_SET		0x2C
57#define OMAP2_I2C_IRQENABLE_CLR		0x30
58#define OMAP2_I2C_WE			0x34
59#define		I2C_IRQSTATUS_XDR		0x4000
60#define		I2C_IRQSTATUS_RDR		0x2000
61#define		I2C_IRQSTATUS_BB		0x1000
62#define		I2C_IRQSTATUS_ROVR		0x0800
63#define		I2C_IRQSTATUS_XUDF		0x0400
64#define		I2C_IRQSTATUS_AAS		0x0200
65#define		I2C_IRQSTATUS_BF		0x0100
66#define		I2C_IRQSTATUS_AERR		0x0080
67#define		I2C_IRQSTATUS_STC		0x0040
68#define		I2C_IRQSTATUS_GC		0x0020
69#define		I2C_IRQSTATUS_XRDY		0x0010
70#define		I2C_IRQSTATUS_RRDY		0x0008
71#define		I2C_IRQSTATUS_ARDY		0x0004
72#define		I2C_IRQSTATUS_NACK		0x0002
73#define		I2C_IRQSTATUS_AL		0x0001
74#define OMAP2_I2C_DMARXENABLE_SET	0x38
75#define OMAP2_I2C_DMATXENABLE_SET	0x3C
76#define OMAP2_I2C_DMARXENABLE_CLR	0x40
77#define		I2C_DMARXENABLE			0x0001
78#define OMAP2_I2C_DMATXENABLE_CLR	0x44
79#define		I2C_DMATXENABLE			0x0001
80#define OMAP2_I2C_DMARXWAKE_EN		0x48
81	/* use same bits as IRQ */
82#define OMAP2_I2C_DMATXWAKE_EN		0x4C
83	/* use same bits as IRQ */
84#define OMAP2_I2C_SYSS			0x90
85#define		I2C_SYSS_RDONE			0x0001
86#define OMAP2_I2C_BUF			0x94
87#define		I2C_BUF_RDMA_EN			0x8000
88#define		I2C_BUF_RXFIFO_CLR		0x4000
89#define		I2C_BUF_RXTRSH_MASK		0x3f00
90#define		I2C_BUF_RXTRSH(x)		((x) << 8)
91#define		I2C_BUF_XDMA_EN			0x0080
92#define		I2C_BUF_TXFIFO_CLR		0x0040
93#define		I2C_BUF_TXTRSH_MASK		0x003f
94#define		I2C_BUF_TXTRSH(x)		((x) << 0)
95#define OMAP2_I2C_CNT			0x98
96#define		I2C_CNT_MASK			0xffff
97#define OMAP2_I2C_DATA			0x9C
98#define		I2C_DATA_MASK			0x00ff
99#define OMAP2_I2C_CON			0xA4
100#define		I2C_CON_EN			0x8000
101#define		I2C_CON_STB			0x0800
102#define		I2C_CON_MST			0x0400
103#define		I2C_CON_TRX			0x0200
104#define		I2C_CON_XSA			0x0100
105#define		I2C_CON_XOA0			0x0080
106#define		I2C_CON_XOA1			0x0040
107#define		I2C_CON_XOA2			0x0020
108#define		I2C_CON_XOA3			0x0010
109#define		I2C_CON_STP			0x0002
110#define		I2C_CON_STT			0x0001
111#define OMAP2_I2C_OA			0xA8
112#define		I2C_OA_MASK			0x03ff
113#define OMAP2_I2C_SA			0xAC
114#define		I2C_SA_MASK			0x03ff
115#define OMAP2_I2C_PSC			0xB0
116#define		I2C_PSC_MASK			0x000f
117#define OMAP2_I2C_SCLL			0xB4
118#define		I2C_SCLL_MASK			0x000f
119#define OMAP2_I2C_SCLH			0xB8
120#define		I2C_SCLH_MASK			0x000f
121#define OMAP2_I2C_SYSTEST		0xBC
122#define OMAP2_I2C_BUFSTAT		0xC0
123#define		I2C_BUFSTAT_FIFODEPTH(x)	(((x) >> 14) & 0x03)
124#define		I2C_BUFSTAT_RXSTAT(x)		(((x) >>  8) & 0x3f)
125#define		I2C_BUFSTAT_TXSTAT(x)		(((x) >>  0) & 0x3f)
126#define OMAP2_I2C_OA1			0xC4
127#define OMAP2_I2C_OA2			0xC8
128#define OMAP2_I2C_OA3			0xCC
129	/* same bits as I2C_OA */
130#define OMAP2_I2C_ACTOA			0xD0
131#define OMAP2_I2C_SBLOCK		0xD4
132#define		I2C_ACTOA_OA3_ACT		0x0008
133#define		I2C_ACTOA_OA2_ACT		0x0004
134#define		I2C_ACTOA_OA1_ACT		0x0002
135#define		I2C_ACTOA_OA0_ACT		0x0001
136
137#endif /* _OMAP2IICREG_H */
138