sunxi_usbphy.c revision 1.9 
1/* $NetBSD: sunxi_usbphy.c,v 1.9 2017/10/06 22:25:05 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.9 2017/10/06 22:25:05 jmcneill Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42/* PHY control registers */
43#define	PHYCTL_ICR		0x00
44#define	 PHYCTL_ICR_ID_PULLUP	__BIT(17)
45#define	 PHYCTL_ICR_DPDM_PULLUP	__BIT(16)
46#define	 PHYCTL_ICR_FORCE_ID	__BITS(15,14)
47#define	  PHYCTL_ICR_FORCE_ID_LOW	2
48#define	  PHYCTL_ICR_FORCE_ID_HIGH	3
49#define	 PHYCTL_ICR_FORCE_VBUS	__BITS(13,12)
50#define	  PHYCTL_ICR_FORCE_VBUS_LOW	2
51#define	  PHYCTL_ICR_FORCE_VBUS_HIGH	3
52#define	PHYCTL_A10		0x04
53#define	PHYCTL_A33		0x10
54#define	 PHYCTL_ADDR		__BITS(15,8)
55#define	 PHYCTL_DATA		__BIT(7)
56#define	PHYCTL_OTG_CFG		0x20
57#define	 PHYCTL_OTG_ROUTE_OTG	__BIT(0)
58
59/* PHY registers */
60#define	PHY_RES45_CAL_EN	0x0c
61#define	PHY_TX_AMPLITUDE_TUNE	0x20
62#define	PHY_DISCON_TH_SEL	0x2a
63
64/* PMU registers */
65#define	PMU_CFG			0x00
66#define	 AHB_INCR8		__BIT(10)
67#define	 AHB_INCR4		__BIT(9)
68#define	 AHB_INCRX_ALIGN	__BIT(8)
69#define	 ULPI_BYPASS		__BIT(0)
70#define	PMU_UNK_H3		0x10
71#define	 PMU_UNK_H3_CLR		__BIT(1)
72
73static int sunxi_usbphy_match(device_t, cfdata_t, void *);
74static void sunxi_usbphy_attach(device_t, device_t, void *);
75
76enum sunxi_usbphy_type {
77	USBPHY_A10 = 1,
78	USBPHY_A13,
79	USBPHY_A20,
80	USBPHY_A31,
81	USBPHY_H3,
82	USBPHY_A64,
83};
84
85static const struct of_compat_data compat_data[] = {
86	{ "allwinner,sun4i-a10-usb-phy",	USBPHY_A10 },
87	{ "allwinner,sun5i-a13-usb-phy",	USBPHY_A13 },
88	{ "allwinner,sun6i-a31-usb-phy",	USBPHY_A31 },
89	{ "allwinner,sun7i-a20-usb-phy",	USBPHY_A20 },
90	{ "allwinner,sun8i-h3-usb-phy",		USBPHY_H3 },
91	{ "allwinner,sun50i-a64-usb-phy",	USBPHY_A64 },
92	{ NULL }
93};
94
95#define	SUNXI_MAXUSBPHY		4
96
97struct sunxi_usbphy {
98	u_int			phy_index;
99	bus_space_handle_t	phy_bsh;
100	struct fdtbus_regulator *phy_reg;
101};
102
103struct sunxi_usbphy_softc {
104	device_t		sc_dev;
105	bus_space_tag_t		sc_bst;
106	bus_space_handle_t	sc_bsh_phy_ctrl;
107	enum sunxi_usbphy_type	sc_type;
108
109	struct sunxi_usbphy	sc_phys[SUNXI_MAXUSBPHY];
110	u_int			sc_nphys;
111
112	struct fdtbus_gpio_pin	*sc_gpio_id_det;
113	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
114};
115
116#define	PHYCTL_READ(sc, reg)				\
117	bus_space_read_4((sc)->sc_bst,			\
118	    (sc)->sc_bsh_phy_ctrl, (reg))
119#define	PHYCTL_WRITE(sc, reg, val)			\
120	bus_space_write_4((sc)->sc_bst,			\
121	    (sc)->sc_bsh_phy_ctrl, (reg), (val))
122#define	PMU_READ(sc, id, reg)			\
123	bus_space_read_4((sc)->sc_bst,			\
124	    (sc)->sc_phys[(id)].phy_bsh, (reg))
125#define	PMU_WRITE(sc, id, reg, val)			\
126	bus_space_write_4((sc)->sc_bst,			\
127	    (sc)->sc_phys[(id)].phy_bsh, (reg), (val))
128
129CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc),
130	sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL);
131
132static void
133sunxi_usbphy_write(struct sunxi_usbphy_softc *sc,
134    struct sunxi_usbphy *phy, u_int bit_addr, u_int bits,
135    u_int len)
136{
137	const uint32_t usbc_mask = __BIT(phy->phy_index * 2);;
138	bus_size_t reg;
139	uint32_t val;
140
141	switch (sc->sc_type) {
142	case USBPHY_A10:
143	case USBPHY_A13:
144	case USBPHY_A20:
145	case USBPHY_A31:
146		reg = PHYCTL_A10;
147		break;
148	case USBPHY_H3:
149	case USBPHY_A64:
150		reg = PHYCTL_A33;
151		break;
152	default:
153		panic("unsupported phy type");
154	}
155
156	if (reg == PHYCTL_A33)
157		PHYCTL_WRITE(sc, reg, 0);
158
159	for (; len > 0; bit_addr++, bits >>= 1, len--) {
160		val = PHYCTL_READ(sc, reg);
161		val &= ~PHYCTL_ADDR;
162		val |= __SHIFTIN(bit_addr, PHYCTL_ADDR);
163		PHYCTL_WRITE(sc, reg, val);
164
165		val = PHYCTL_READ(sc, reg);
166		val &= ~PHYCTL_DATA;
167		val |= __SHIFTIN(bits & 1, PHYCTL_DATA);
168		PHYCTL_WRITE(sc, reg, val);
169
170		PHYCTL_READ(sc, reg);
171		val |= usbc_mask;
172		PHYCTL_WRITE(sc, reg, val);
173
174		PHYCTL_READ(sc, reg);
175		val &= ~usbc_mask;
176		PHYCTL_WRITE(sc, reg, val);
177	}
178}
179
180static bool
181sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc)
182{
183	if (sc->sc_gpio_vbus_det)
184		return fdtbus_gpio_read(sc->sc_gpio_vbus_det);
185	return 1;
186}
187
188static void *
189sunxi_usbphy_acquire(device_t dev, const void *data, size_t len)
190{
191	struct sunxi_usbphy_softc * const sc = device_private(dev);
192
193	if (len != 4)
194		return NULL;
195
196	const int phy_id = be32dec(data);
197	if (phy_id >= sc->sc_nphys)
198		return NULL;
199
200	return &sc->sc_phys[phy_id];
201}
202
203static void
204sunxi_usbphy_release(device_t dev, void *priv)
205{
206}
207
208static int
209sunxi_usbphy_enable(device_t dev, void *priv, bool enable)
210{
211	struct sunxi_usbphy_softc * const sc = device_private(dev);
212	struct sunxi_usbphy * const phy = priv;
213	u_int disc_thresh;
214	bool phy0_reroute;
215	uint32_t val;
216
217	switch (sc->sc_type) {
218	case USBPHY_A13:
219		disc_thresh = 0x2;
220		phy0_reroute = false;
221		break;
222	case USBPHY_A10:
223	case USBPHY_A20:
224	case USBPHY_A31:
225		disc_thresh = 0x3;
226		phy0_reroute = false;
227		break;
228	case USBPHY_A64:
229	case USBPHY_H3:
230		disc_thresh = 0x3;
231		phy0_reroute = true;
232		break;
233	default:
234		aprint_error_dev(dev, "unsupported board\n");
235		return ENXIO;
236	}
237
238	if (phy->phy_bsh) {
239		/* Enable/disable passby */
240		const uint32_t mask =
241		    ULPI_BYPASS|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN;
242		val = PMU_READ(sc, phy->phy_index, PMU_CFG);
243		if (enable)
244			val |= mask;
245		else
246			val &= ~mask;
247		PMU_WRITE(sc, phy->phy_index, PMU_CFG, val);
248	}
249
250	switch (sc->sc_type) {
251	case USBPHY_H3:
252	case USBPHY_A64:
253		if (enable && phy->phy_bsh) {
254			val = PMU_READ(sc, phy->phy_index, PMU_UNK_H3);
255			val &= ~PMU_UNK_H3_CLR;
256			PMU_WRITE(sc, phy->phy_index, PMU_UNK_H3, val);
257		}
258		break;
259	default:
260		break;
261	}
262
263	if (enable) {
264		if (phy->phy_index == 0)
265			sunxi_usbphy_write(sc, phy, PHY_RES45_CAL_EN, 0x1, 1);
266		sunxi_usbphy_write(sc, phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
267		sunxi_usbphy_write(sc, phy, PHY_DISCON_TH_SEL, disc_thresh, 2);
268	}
269
270	if (phy->phy_index == 0) {
271		const uint32_t mask =
272		    PHYCTL_ICR_ID_PULLUP|PHYCTL_ICR_DPDM_PULLUP;
273		val = PHYCTL_READ(sc, PHYCTL_ICR);
274
275		if (enable)
276			val |= mask;
277		else
278			val &= ~mask;
279
280		/* XXX only host mode is supported */
281		val &= ~PHYCTL_ICR_FORCE_ID;
282		val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID);
283		val &= ~PHYCTL_ICR_FORCE_VBUS;
284		val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS);
285
286		PHYCTL_WRITE(sc, PHYCTL_ICR, val);
287
288		if (phy0_reroute) {
289			val = PHYCTL_READ(sc, PHYCTL_OTG_CFG);
290			val &= ~PHYCTL_OTG_ROUTE_OTG;
291			PHYCTL_WRITE(sc, PHYCTL_OTG_CFG, val);
292		}
293	}
294
295	if (phy->phy_reg == NULL)
296		return 0;
297
298	if (enable) {
299		/* If an external vbus is detected, do not enable phy 0 */
300		if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc))
301			return 0;
302		return fdtbus_regulator_enable(phy->phy_reg);
303	} else {
304		return fdtbus_regulator_disable(phy->phy_reg);
305	}
306}
307
308const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = {
309	.acquire = sunxi_usbphy_acquire,
310	.release = sunxi_usbphy_release,
311	.enable = sunxi_usbphy_enable,
312};
313
314static int
315sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux)
316{
317	struct fdt_attach_args * const faa = aux;
318
319	return of_match_compat_data(faa->faa_phandle, compat_data);
320}
321
322static void
323sunxi_usbphy_attach(device_t parent, device_t self, void *aux)
324{
325	struct sunxi_usbphy_softc * const sc = device_private(self);
326	struct fdt_attach_args * const faa = aux;
327	const int phandle = faa->faa_phandle;
328	struct fdtbus_reset *rst;
329	struct sunxi_usbphy *phy;
330	struct clk *clk;
331	bus_addr_t addr;
332	bus_size_t size;
333	char pname[20];
334	u_int n;
335
336	sc->sc_dev = self;
337	sc->sc_bst = faa->faa_bst;
338	sc->sc_type = of_search_compatible(phandle, compat_data)->data;
339
340	if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) {
341		aprint_error(": couldn't get phy ctrl registers\n");
342		return;
343	}
344	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) {
345		aprint_error(": couldn't map phy ctrl registers\n");
346		return;
347	}
348
349	for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) {
350		phy = &sc->sc_phys[sc->sc_nphys];
351		phy->phy_index = sc->sc_nphys;
352		snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys);
353		if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) {
354			/* There may be no registers for OTG PHY */
355			if (sc->sc_nphys > 0)
356				break;
357		} else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) {
358			aprint_error(": failed to map reg #%d\n", sc->sc_nphys);
359			return;
360		}
361		/* Get optional regulator */
362		snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys);
363		phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
364	}
365
366	/* Enable clocks */
367	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
368		if (clk_enable(clk) != 0) {
369			aprint_error(": couldn't enable clock #%d\n", n);
370			return;
371		}
372	/* De-assert resets */
373	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
374		if (fdtbus_reset_deassert(rst) != 0) {
375			aprint_error(": couldn't de-assert reset #%d\n", n);
376			return;
377		}
378
379	aprint_naive("\n");
380	aprint_normal(": USB PHY\n");
381
382	fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs);
383}
384