sunxi_usbphy.c revision 1.6 
1/* $NetBSD: sunxi_usbphy.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.6 2017/09/07 01:07:04 jmcneill Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	OTG_PHY_CFG		0x20
43#define	 OTG_PHY_ROUTE_OTG	__BIT(0)
44
45#define	HCI_ICR			0x00
46#define	 HCI_AHB_INCR8		__BIT(10)
47#define	 HCI_AHB_INCR4		__BIT(9)
48#define	 HCI_AHB_INCRX_ALIGN	__BIT(8)
49#define	 HCI_ULPI_BYPASS	__BIT(0)
50#define	PMU_UNK_H3		0x10
51#define	 PMU_UNK_H3_CLR		__BIT(1)
52
53static int sunxi_usbphy_match(device_t, cfdata_t, void *);
54static void sunxi_usbphy_attach(device_t, device_t, void *);
55
56enum sunxi_usbphy_type {
57	USBPHY_A13,
58	USBPHY_A31,
59	USBPHY_H3,
60	USBPHY_A64,
61};
62
63static const struct of_compat_data compat_data[] = {
64	{ "allwinner,sun5i-a13-usb-phy",	USBPHY_A13 },
65	{ "allwinner,sun6i-a31-usb-phy",	USBPHY_A31 },
66	{ "allwinner,sun8i-h3-usb-phy",		USBPHY_H3 },
67	{ "allwinner,sun50i-a64-usb-phy",	USBPHY_A64 },
68	{ NULL }
69};
70
71#define	SUNXI_MAXUSBPHY		4
72
73struct sunxi_usbphy {
74	u_int			phy_index;
75	bus_space_handle_t	phy_bsh;
76	struct fdtbus_regulator *phy_reg;
77};
78
79struct sunxi_usbphy_softc {
80	device_t		sc_dev;
81	bus_space_tag_t		sc_bst;
82	bus_space_handle_t	sc_bsh_phy_ctrl;
83	enum sunxi_usbphy_type	sc_type;
84
85	struct sunxi_usbphy	sc_phys[SUNXI_MAXUSBPHY];
86	u_int			sc_nphys;
87
88	struct fdtbus_gpio_pin	*sc_gpio_id_det;
89	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
90};
91
92#define	USBPHY_READ(sc, id, reg)			\
93	bus_space_read_4((sc)->sc_bst,			\
94	    (sc)->sc_phys[(id)].phy_bsh, (reg))
95#define	USBPHY_WRITE(sc, id, reg, val)			\
96	bus_space_write_4((sc)->sc_bst,			\
97	    (sc)->sc_phys[(id)].phy_bsh, (reg), (val))
98
99CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc),
100	sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL);
101
102static bool
103sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc)
104{
105	if (sc->sc_gpio_vbus_det)
106		return fdtbus_gpio_read(sc->sc_gpio_vbus_det);
107	return 1;
108}
109
110static void *
111sunxi_usbphy_acquire(device_t dev, const void *data, size_t len)
112{
113	struct sunxi_usbphy_softc * const sc = device_private(dev);
114
115	if (len != 4)
116		return NULL;
117
118	const int phy_id = be32dec(data);
119	if (phy_id >= sc->sc_nphys)
120		return NULL;
121
122	return &sc->sc_phys[phy_id];
123}
124
125static void
126sunxi_usbphy_release(device_t dev, void *priv)
127{
128}
129
130static int
131sunxi_usbphy_enable(device_t dev, void *priv, bool enable)
132{
133	struct sunxi_usbphy_softc * const sc = device_private(dev);
134	struct sunxi_usbphy * const phy = priv;
135	uint32_t val;
136
137	if (phy->phy_index > 0) {
138		/* Enable passby */
139		val = USBPHY_READ(sc, phy->phy_index, HCI_ICR);
140		val |= HCI_ULPI_BYPASS;
141		val |= HCI_AHB_INCR8;
142		val |= HCI_AHB_INCR4;
143		val |= HCI_AHB_INCRX_ALIGN;
144		USBPHY_WRITE(sc, phy->phy_index, HCI_ICR, val);
145	}
146
147	if (sc->sc_type == USBPHY_H3) {
148		/* H3-specific */
149		val = USBPHY_READ(sc, phy->phy_index, PMU_UNK_H3);
150		val &= ~PMU_UNK_H3_CLR;
151		USBPHY_WRITE(sc, phy->phy_index, PMU_UNK_H3, val);
152	}
153
154	if (phy->phy_reg == NULL)
155		return 0;
156
157	if (enable) {
158		/* If an external vbus is detected, do not enable phy 0 */
159		if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc))
160			return 0;
161		return fdtbus_regulator_enable(phy->phy_reg);
162	} else {
163		return fdtbus_regulator_disable(phy->phy_reg);
164	}
165}
166
167const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = {
168	.acquire = sunxi_usbphy_acquire,
169	.release = sunxi_usbphy_release,
170	.enable = sunxi_usbphy_enable,
171};
172
173static int
174sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux)
175{
176	struct fdt_attach_args * const faa = aux;
177
178	return of_match_compat_data(faa->faa_phandle, compat_data);
179}
180
181static void
182sunxi_usbphy_attach(device_t parent, device_t self, void *aux)
183{
184	struct sunxi_usbphy_softc * const sc = device_private(self);
185	struct fdt_attach_args * const faa = aux;
186	const int phandle = faa->faa_phandle;
187	struct fdtbus_reset *rst;
188	struct sunxi_usbphy *phy;
189	struct clk *clk;
190	bus_addr_t addr;
191	bus_size_t size;
192	char pname[20];
193	u_int n;
194
195	sc->sc_dev = self;
196	sc->sc_bst = faa->faa_bst;
197	sc->sc_type = of_search_compatible(phandle, compat_data)->data;
198
199	if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) {
200		aprint_error(": couldn't get phy ctrl registers\n");
201		return;
202	}
203	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) {
204		aprint_error(": couldn't map phy ctrl registers\n");
205		return;
206	}
207
208	for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) {
209		phy = &sc->sc_phys[sc->sc_nphys];
210		phy->phy_index = sc->sc_nphys;
211		snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys);
212		if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) {
213			/* There may be no registers for OTG PHY */
214			if (sc->sc_nphys > 0)
215				break;
216		} else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) {
217			aprint_error(": failed to map reg #%d\n", sc->sc_nphys);
218			return;
219		}
220		/* Get optional regulator */
221		snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys);
222		phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
223	}
224
225	/* Enable clocks */
226	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
227		if (clk_enable(clk) != 0) {
228			aprint_error(": couldn't enable clock #%d\n", n);
229			return;
230		}
231	/* De-assert resets */
232	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
233		if (fdtbus_reset_deassert(rst) != 0) {
234			aprint_error(": couldn't de-assert reset #%d\n", n);
235			return;
236		}
237
238	aprint_naive("\n");
239	aprint_normal(": USB PHY\n");
240
241	fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs);
242}
243