sunxi_usbphy.c revision 1.5 
1/* $NetBSD: sunxi_usbphy.c,v 1.5 2017/08/25 12:28:51 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.5 2017/08/25 12:28:51 jmcneill Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	OTG_PHY_CFG		0x20
43#define	 OTG_PHY_ROUTE_OTG	__BIT(0)
44
45#define	HCI_ICR			0x00
46#define	 HCI_AHB_INCR8		__BIT(10)
47#define	 HCI_AHB_INCR4		__BIT(9)
48#define	 HCI_AHB_INCRX_ALIGN	__BIT(8)
49#define	 HCI_ULPI_BYPASS	__BIT(0)
50#define	PMU_UNK_H3		0x10
51#define	 PMU_UNK_H3_CLR		__BIT(1)
52
53static int sunxi_usbphy_match(device_t, cfdata_t, void *);
54static void sunxi_usbphy_attach(device_t, device_t, void *);
55
56enum sunxi_usbphy_type {
57	USBPHY_A13,
58	USBPHY_A31,
59	USBPHY_H3,
60};
61
62static const struct of_compat_data compat_data[] = {
63	{ "allwinner,sun5i-a13-usb-phy",	USBPHY_A13 },
64	{ "allwinner,sun6i-a31-usb-phy",	USBPHY_A31 },
65	{ "allwinner,sun8i-h3-usb-phy",		USBPHY_H3 },
66	{ NULL }
67};
68
69#define	SUNXI_MAXUSBPHY		4
70
71struct sunxi_usbphy {
72	u_int			phy_index;
73	bus_space_handle_t	phy_bsh;
74	struct fdtbus_regulator *phy_reg;
75};
76
77struct sunxi_usbphy_softc {
78	device_t		sc_dev;
79	bus_space_tag_t		sc_bst;
80	bus_space_handle_t	sc_bsh_phy_ctrl;
81	enum sunxi_usbphy_type	sc_type;
82
83	struct sunxi_usbphy	sc_phys[SUNXI_MAXUSBPHY];
84	u_int			sc_nphys;
85
86	struct fdtbus_gpio_pin	*sc_gpio_id_det;
87	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
88};
89
90#define	USBPHY_READ(sc, id, reg)			\
91	bus_space_read_4((sc)->sc_bst,			\
92	    (sc)->sc_phys[(id)].phy_bsh, (reg))
93#define	USBPHY_WRITE(sc, id, reg, val)			\
94	bus_space_write_4((sc)->sc_bst,			\
95	    (sc)->sc_phys[(id)].phy_bsh, (reg), (val))
96
97CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc),
98	sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL);
99
100static bool
101sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc)
102{
103	if (sc->sc_gpio_vbus_det)
104		return fdtbus_gpio_read(sc->sc_gpio_vbus_det);
105	return 1;
106}
107
108static void *
109sunxi_usbphy_acquire(device_t dev, const void *data, size_t len)
110{
111	struct sunxi_usbphy_softc * const sc = device_private(dev);
112
113	if (len != 4)
114		return NULL;
115
116	const int phy_id = be32dec(data);
117	if (phy_id >= sc->sc_nphys)
118		return NULL;
119
120	return &sc->sc_phys[phy_id];
121}
122
123static void
124sunxi_usbphy_release(device_t dev, void *priv)
125{
126}
127
128static int
129sunxi_usbphy_enable(device_t dev, void *priv, bool enable)
130{
131	struct sunxi_usbphy_softc * const sc = device_private(dev);
132	struct sunxi_usbphy * const phy = priv;
133	uint32_t val;
134
135	if (phy->phy_index > 0) {
136		/* Enable passby */
137		val = USBPHY_READ(sc, phy->phy_index, HCI_ICR);
138		val |= HCI_ULPI_BYPASS;
139		val |= HCI_AHB_INCR8;
140		val |= HCI_AHB_INCR4;
141		val |= HCI_AHB_INCRX_ALIGN;
142		USBPHY_WRITE(sc, phy->phy_index, HCI_ICR, val);
143	}
144
145	if (sc->sc_type == USBPHY_H3) {
146		/* H3-specific */
147		val = USBPHY_READ(sc, phy->phy_index, PMU_UNK_H3);
148		val &= ~PMU_UNK_H3_CLR;
149		USBPHY_WRITE(sc, phy->phy_index, PMU_UNK_H3, val);
150	}
151
152	if (phy->phy_reg == NULL)
153		return 0;
154
155	if (enable) {
156		/* If an external vbus is detected, do not enable phy 0 */
157		if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc))
158			return 0;
159		return fdtbus_regulator_enable(phy->phy_reg);
160	} else {
161		return fdtbus_regulator_disable(phy->phy_reg);
162	}
163}
164
165const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = {
166	.acquire = sunxi_usbphy_acquire,
167	.release = sunxi_usbphy_release,
168	.enable = sunxi_usbphy_enable,
169};
170
171static int
172sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux)
173{
174	struct fdt_attach_args * const faa = aux;
175
176	return of_match_compat_data(faa->faa_phandle, compat_data);
177}
178
179static void
180sunxi_usbphy_attach(device_t parent, device_t self, void *aux)
181{
182	struct sunxi_usbphy_softc * const sc = device_private(self);
183	struct fdt_attach_args * const faa = aux;
184	const int phandle = faa->faa_phandle;
185	struct fdtbus_reset *rst;
186	struct sunxi_usbphy *phy;
187	struct clk *clk;
188	bus_addr_t addr;
189	bus_size_t size;
190	char pname[20];
191	u_int n;
192
193	sc->sc_dev = self;
194	sc->sc_bst = faa->faa_bst;
195	sc->sc_type = of_search_compatible(phandle, compat_data)->data;
196
197	if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) {
198		aprint_error(": couldn't get phy ctrl registers\n");
199		return;
200	}
201	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) {
202		aprint_error(": couldn't map phy ctrl registers\n");
203		return;
204	}
205
206	for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) {
207		phy = &sc->sc_phys[sc->sc_nphys];
208		phy->phy_index = sc->sc_nphys;
209		snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys);
210		if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) {
211			/* There may be no registers for OTG PHY */
212			if (sc->sc_nphys > 0)
213				break;
214		} else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) {
215			aprint_error(": failed to map reg #%d\n", sc->sc_nphys);
216			return;
217		}
218		/* Get optional regulator */
219		snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys);
220		phy->phy_reg = fdtbus_regulator_acquire(phandle, pname);
221	}
222
223	/* Enable clocks */
224	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
225		if (clk_enable(clk) != 0) {
226			aprint_error(": couldn't enable clock #%d\n", n);
227			return;
228		}
229	/* De-assert resets */
230	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
231		if (fdtbus_reset_deassert(rst) != 0) {
232			aprint_error(": couldn't de-assert reset #%d\n", n);
233			return;
234		}
235
236	aprint_naive("\n");
237	aprint_normal(": USB PHY\n");
238
239	fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs);
240}
241