1/* $NetBSD: sunxi_musb.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: sunxi_musb.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/pool.h>
39
40#include <dev/usb/usb.h>
41#include <dev/usb/usbdi.h>
42#include <dev/usb/usbdivar.h>
43#include <dev/usb/motgvar.h>
44#include <dev/usb/motgreg.h>
45
46#include <dev/fdt/fdtvar.h>
47
48#include <machine/bus_defs.h>
49
50#define	MUSB2_REG_AWIN_VEND0	0x43
51
52static int	sunxi_musb_match(device_t, cfdata_t, void *);
53static void	sunxi_musb_attach(device_t, device_t, void *);
54
55struct sunxi_musb_softc {
56	struct motg_softc	sc_otg;
57	struct bus_space	sc_bs;
58};
59
60CFATTACH_DECL_NEW(sunxi_musb, sizeof(struct sunxi_musb_softc),
61	sunxi_musb_match, sunxi_musb_attach, NULL, NULL);
62
63static const struct device_compatible_entry compat_data[] = {
64	{ .compat = "allwinner,sun4i-a10-musb",		.value = 5 },
65	{ .compat = "allwinner,sun6i-a13-musb",		.value = 5 },
66	{ .compat = "allwinner,sun8i-h3-musb",		.value = 4 },
67	{ .compat = "allwinner,sun8i-a33-musb",		.value = 5 },
68	DEVICE_COMPAT_EOL
69};
70
71#define	REMAPFLAG	0x8000
72#define	REGDECL(a, b)	[(a)] = ((b) | REMAPFLAG)
73
74/* Allwinner USB DRD register mappings */
75static const uint16_t sunxi_musb_regmap[] = {
76	REGDECL(MUSB2_REG_EPFIFO(0),	0x0000),
77	REGDECL(MUSB2_REG_EPFIFO(1),	0x0004),
78	REGDECL(MUSB2_REG_EPFIFO(2),	0x0008),
79	REGDECL(MUSB2_REG_EPFIFO(3),	0x000c),
80	REGDECL(MUSB2_REG_EPFIFO(4),	0x0010),
81	REGDECL(MUSB2_REG_EPFIFO(5),	0x0014),
82	REGDECL(MUSB2_REG_POWER,	0x0040),
83	REGDECL(MUSB2_REG_DEVCTL,	0x0041),
84	REGDECL(MUSB2_REG_EPINDEX,	0x0042),
85	REGDECL(MUSB2_REG_AWIN_VEND0,	0x0043),
86	REGDECL(MUSB2_REG_INTTX,	0x0044),
87	REGDECL(MUSB2_REG_INTRX,	0x0046),
88	REGDECL(MUSB2_REG_INTTXE,	0x0048),
89	REGDECL(MUSB2_REG_INTRXE,	0x004a),
90	REGDECL(MUSB2_REG_INTUSB,	0x004c),
91	REGDECL(MUSB2_REG_INTUSBE,	0x0050),
92	REGDECL(MUSB2_REG_FRAME,	0x0054),
93	REGDECL(MUSB2_REG_TESTMODE,	0x007c),
94	REGDECL(MUSB2_REG_TXMAXP,	0x0080),
95	REGDECL(MUSB2_REG_TXCSRL,	0x0082),
96	REGDECL(MUSB2_REG_TXCSRH,	0x0083),
97	REGDECL(MUSB2_REG_RXMAXP,	0x0084),
98	REGDECL(MUSB2_REG_RXCSRL,	0x0086),
99	REGDECL(MUSB2_REG_RXCSRH,	0x0087),
100	REGDECL(MUSB2_REG_RXCOUNT,	0x0088),
101	REGDECL(MUSB2_REG_TXTI,		0x008c),
102	REGDECL(MUSB2_REG_TXNAKLIMIT,	0x008d),
103	REGDECL(MUSB2_REG_RXNAKLIMIT,	0x008d),
104	REGDECL(MUSB2_REG_RXTI,		0x008e),
105	REGDECL(MUSB2_REG_TXFIFOSZ,	0x0090),
106	REGDECL(MUSB2_REG_TXFIFOADD,	0x0092),
107	REGDECL(MUSB2_REG_RXFIFOSZ,	0x0094),
108	REGDECL(MUSB2_REG_RXFIFOADD,	0x0096),
109	REGDECL(MUSB2_REG_FADDR,	0x0098),
110	REGDECL(MUSB2_REG_TXFADDR(0),	0x0098),
111	REGDECL(MUSB2_REG_TXHADDR(0),	0x009a),
112	REGDECL(MUSB2_REG_TXHUBPORT(0),	0x009b),
113	REGDECL(MUSB2_REG_RXFADDR(0),	0x009c),
114	REGDECL(MUSB2_REG_RXHADDR(0),	0x009e),
115	REGDECL(MUSB2_REG_RXHUBPORT(0),	0x009f),
116	REGDECL(MUSB2_REG_TXFADDR(1),	0x0098),
117	REGDECL(MUSB2_REG_TXHADDR(1),	0x009a),
118	REGDECL(MUSB2_REG_TXHUBPORT(1),	0x009b),
119	REGDECL(MUSB2_REG_RXFADDR(1),	0x009c),
120	REGDECL(MUSB2_REG_RXHADDR(1),	0x009e),
121	REGDECL(MUSB2_REG_RXHUBPORT(1),	0x009f),
122	REGDECL(MUSB2_REG_TXFADDR(2),	0x0098),
123	REGDECL(MUSB2_REG_TXHADDR(2),	0x009a),
124	REGDECL(MUSB2_REG_TXHUBPORT(2),	0x009b),
125	REGDECL(MUSB2_REG_RXFADDR(2),	0x009c),
126	REGDECL(MUSB2_REG_RXHADDR(2),	0x009e),
127	REGDECL(MUSB2_REG_RXHUBPORT(2),	0x009f),
128	REGDECL(MUSB2_REG_TXFADDR(3),	0x0098),
129	REGDECL(MUSB2_REG_TXHADDR(3),	0x009a),
130	REGDECL(MUSB2_REG_TXHUBPORT(3),	0x009b),
131	REGDECL(MUSB2_REG_RXFADDR(3),	0x009c),
132	REGDECL(MUSB2_REG_RXHADDR(3),	0x009e),
133	REGDECL(MUSB2_REG_RXHUBPORT(3),	0x009f),
134	REGDECL(MUSB2_REG_TXFADDR(4),	0x0098),
135	REGDECL(MUSB2_REG_TXHADDR(4),	0x009a),
136	REGDECL(MUSB2_REG_TXHUBPORT(4),	0x009b),
137	REGDECL(MUSB2_REG_RXFADDR(4),	0x009c),
138	REGDECL(MUSB2_REG_RXHADDR(4),	0x009e),
139	REGDECL(MUSB2_REG_RXHUBPORT(4),	0x009f),
140	REGDECL(MUSB2_REG_TXFADDR(5),	0x0098),
141	REGDECL(MUSB2_REG_TXHADDR(5),	0x009a),
142	REGDECL(MUSB2_REG_TXHUBPORT(5),	0x009b),
143	REGDECL(MUSB2_REG_RXFADDR(5),	0x009c),
144	REGDECL(MUSB2_REG_RXHADDR(5),	0x009e),
145	REGDECL(MUSB2_REG_RXHUBPORT(5),	0x009f),
146	REGDECL(MUSB2_REG_CONFDATA,	0x00c0),
147};
148
149static bus_size_t
150sunxi_musb_reg(bus_size_t o)
151{
152	bus_size_t v;
153
154	if (o >= __arraycount(sunxi_musb_regmap))
155		return o;
156
157	v = sunxi_musb_regmap[o];
158	KASSERTMSG((v & REMAPFLAG) != 0, "%s: reg %#lx not in regmap",
159	    __func__, o);
160
161	return v & ~REMAPFLAG;
162}
163
164static int
165sunxi_musb_filt(bus_size_t o)
166{
167	switch (o) {
168	case MUSB2_REG_MISC:
169	case MUSB2_REG_RXDBDIS:
170	case MUSB2_REG_TXDBDIS:
171		return 1;
172	default:
173		return 0;
174	}
175}
176
177static uint8_t
178sunxi_musb_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
179{
180	switch (o) {
181	case MUSB2_REG_HWVERS:
182		return 0;	/* no known equivalent */
183	}
184
185	return bus_space_read_1((bus_space_tag_t)t, h, sunxi_musb_reg(o));
186}
187
188static uint16_t
189sunxi_musb_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
190{
191	return bus_space_read_2((bus_space_tag_t)t, h, sunxi_musb_reg(o));
192}
193
194static void
195sunxi_musb_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o,
196    uint8_t v)
197{
198	if (sunxi_musb_filt(o) != 0)
199		return;
200
201	bus_space_write_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), v);
202}
203
204static void
205sunxi_musb_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o,
206    uint16_t v)
207{
208	if (sunxi_musb_filt(o) != 0)
209		return;
210
211	bus_space_write_2((bus_space_tag_t)t, h, sunxi_musb_reg(o), v);
212}
213
214static void
215sunxi_musb_bs_rm_1(void *t, bus_space_handle_t h, bus_size_t o,
216    uint8_t *d, bus_size_t c)
217{
218	bus_space_read_multi_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c);
219}
220
221static void
222sunxi_musb_bs_rm_4(void *t, bus_space_handle_t h, bus_size_t o,
223    uint32_t *d, bus_size_t c)
224{
225	bus_space_read_multi_4((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c);
226}
227
228static void
229sunxi_musb_bs_wm_1(void *t, bus_space_handle_t h, bus_size_t o,
230    const uint8_t *d, bus_size_t c)
231{
232	if (sunxi_musb_filt(o) != 0)
233		return;
234
235	bus_space_write_multi_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c);
236}
237
238static void
239sunxi_musb_bs_wm_4(void *t, bus_space_handle_t h, bus_size_t o,
240    const uint32_t *d, bus_size_t c)
241{
242	if (sunxi_musb_filt(o) != 0)
243		return;
244
245	bus_space_write_multi_4((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c);
246}
247
248static void
249sunxi_musb_bs_barrier(void *t, bus_space_handle_t h, bus_size_t o,
250    bus_size_t l, int f)
251{
252	bus_space_barrier((bus_space_tag_t)t, h, o, l, f);
253}
254
255static int
256sunxi_musb_intr(void *priv)
257{
258	struct motg_softc * const sc = priv;
259	uint16_t inttx, intrx;
260	uint8_t intusb;
261
262	mutex_enter(&sc->sc_intr_lock);
263
264	intusb = bus_space_read_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB);
265	inttx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX);
266	intrx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX);
267	if (!intusb && !inttx && !intrx) {
268		mutex_exit(&sc->sc_intr_lock);
269		return 0;
270	}
271
272	if (intusb)
273		bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB, intusb);
274	if (inttx)
275		bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX, inttx);
276	if (intrx)
277		bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX, intrx);
278
279	motg_intr(sc, intrx, inttx, intusb);
280
281	mutex_exit(&sc->sc_intr_lock);
282
283	return 1;
284}
285
286static void
287sunxi_musb_poll(void *priv)
288{
289	sunxi_musb_intr(priv);
290}
291
292static int
293sunxi_musb_match(device_t parent, cfdata_t cf, void *aux)
294{
295	struct fdt_attach_args * const faa = aux;
296
297	return of_compatible_match(faa->faa_phandle, compat_data);
298}
299
300static void
301sunxi_musb_attach(device_t parent, device_t self, void *aux)
302{
303	struct sunxi_musb_softc * const msc = device_private(self);
304	struct motg_softc * const sc = &msc->sc_otg;
305	struct fdt_attach_args * const faa = aux;
306	const int phandle = faa->faa_phandle;
307	struct fdtbus_reset *rst;
308	struct fdtbus_phy *phy;
309	struct clk *clk;
310	char intrstr[128];
311	const char *dr_mode;
312	bus_addr_t addr;
313	bus_size_t size;
314	void *ih;
315	u_int n;
316
317	/* Only "host" mode is supported */
318	dr_mode = fdtbus_get_string(phandle, "dr_mode");
319	if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) {
320		aprint_normal(": '%s' mode not supported\n", dr_mode);
321		return;
322	}
323
324	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
325		aprint_error(": couldn't get registers\n");
326		return;
327	}
328
329	/* Enable clocks */
330	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
331		if (clk_enable(clk) != 0) {
332			aprint_error(": couldn't enable clock #%d\n", n);
333			return;
334		}
335	/* De-assert resets */
336	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
337		if (fdtbus_reset_deassert(rst) != 0) {
338			aprint_error(": couldn't de-assert reset #%d\n", n);
339			return;
340		}
341
342	/* Enable optional phy */
343	phy = fdtbus_phy_get(phandle, "usb");
344	if (phy && fdtbus_phy_enable(phy, true) != 0) {
345		aprint_error(": couldn't enable phy\n");
346		return;
347	}
348
349	/* Create custom bus space tag for remapping registers */
350	msc->sc_bs.bs_cookie = faa->faa_bst;
351	msc->sc_bs.bs_r_1 = sunxi_musb_bs_r_1;
352	msc->sc_bs.bs_r_2 = sunxi_musb_bs_r_2;
353	msc->sc_bs.bs_w_1 = sunxi_musb_bs_w_1;
354	msc->sc_bs.bs_w_2 = sunxi_musb_bs_w_2;
355	msc->sc_bs.bs_rm_1 = sunxi_musb_bs_rm_1;
356	msc->sc_bs.bs_rm_4 = sunxi_musb_bs_rm_4;
357	msc->sc_bs.bs_wm_1 = sunxi_musb_bs_wm_1;
358	msc->sc_bs.bs_wm_4 = sunxi_musb_bs_wm_4;
359	msc->sc_bs.bs_barrier = sunxi_musb_bs_barrier;
360
361	sc->sc_dev = self;
362	sc->sc_bus.ub_hcpriv = sc;
363	sc->sc_bus.ub_dmatag = faa->faa_dmat;
364	sc->sc_size = size;
365	sc->sc_iot = &msc->sc_bs;
366	if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_ioh) != 0) {
367		aprint_error(": couldn't map registers\n");
368		return;
369	}
370	sc->sc_intr_poll = sunxi_musb_poll;
371	sc->sc_intr_poll_arg = sc;
372	sc->sc_mode = MOTG_MODE_HOST;
373	sc->sc_ep_max = of_compatible_lookup(phandle, compat_data)->value;
374	sc->sc_ep_fifosize = 512;
375
376	aprint_naive("\n");
377	aprint_normal(": USB OTG\n");
378
379	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
380		aprint_error_dev(self, "failed to decode interrupt\n");
381		return;
382	}
383
384	ih = fdtbus_intr_establish_xname(phandle, 0, IPL_USB, FDT_INTR_MPSAFE,
385	    sunxi_musb_intr, sc, device_xname(self));
386	if (ih == NULL) {
387		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
388		    intrstr);
389		return;
390	}
391	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
392
393	bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_AWIN_VEND0, 0);
394
395	motg_init(sc);
396}
397