sunxi_intc.c revision 1.2
1/* $NetBSD: sunxi_intc.c,v 1.2 2017/10/11 00:17:03 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#define _INTR_PRIVATE 30 31#include <sys/cdefs.h> 32__KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.2 2017/10/11 00:17:03 jmcneill Exp $"); 33 34#include <sys/param.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/device.h> 38#include <sys/intr.h> 39#include <sys/systm.h> 40 41#include <dev/fdt/fdtvar.h> 42 43#include <arm/cpu.h> 44#include <arm/pic/picvar.h> 45#include <arm/fdt/arm_fdtvar.h> 46 47#define INTC_MAX_SOURCES 96 48#define INTC_MAX_GROUPS 3 49 50#define INTC_VECTOR_REG 0x00 51#define INTC_BASE_ADDR_REG 0x04 52#define INTC_PROTECT_REG 0x08 53#define INTC_PROTECT_EN __BIT(0) 54#define INTC_NMII_CTRL_REG 0x0c 55#define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4)) 56#define INTC_FIQ_PEND_REG(n) (0x20 + ((n) * 4)) 57#define INTC_SEL_REG(n) (0x30 + ((n) * 4)) 58#define INTC_EN_REG(n) (0x40 + ((n) * 4)) 59#define INTC_MASK_REG(n) (0x50 + ((n) * 4)) 60#define INTC_RESP_REG(n) (0x60 + ((n) * 4)) 61#define INTC_FORCE_REG(n) (0x70 + ((n) * 4)) 62#define INTC_SRC_PRIO_REG(n) (0x80 + ((n) * 4)) 63 64static const char * const compatible[] = { 65 "allwinner,sun4i-a10-ic", 66 NULL 67}; 68 69struct sunxi_intc_softc { 70 device_t sc_dev; 71 bus_space_tag_t sc_bst; 72 bus_space_handle_t sc_bsh; 73 int sc_phandle; 74 75 uint32_t sc_enabled_irqs[INTC_MAX_GROUPS]; 76 77 struct pic_softc sc_pic; 78}; 79 80static struct sunxi_intc_softc *intc_softc; 81 82#define PICTOSOFTC(pic) \ 83 ((void *)((uintptr_t)(pic) - offsetof(struct sunxi_intc_softc, sc_pic))) 84 85#define INTC_READ(sc, reg) \ 86 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 87#define INTC_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 90static void 91sunxi_intc_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 92{ 93 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 94 const u_int group = irqbase / 32; 95 96 KASSERT((mask & sc->sc_enabled_irqs[group]) == 0); 97 sc->sc_enabled_irqs[group] |= mask; 98 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 99} 100 101static void 102sunxi_intc_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 103{ 104 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 105 const u_int group = irqbase / 32; 106 107 sc->sc_enabled_irqs[group] &= ~mask; 108 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 109} 110 111static void 112sunxi_intc_establish_irq(struct pic_softc *pic, struct intrsource *is) 113{ 114 KASSERT(is->is_irq < INTC_MAX_SOURCES); 115 KASSERT(is->is_type == IST_LEVEL); 116} 117 118static void 119sunxi_intc_set_priority(struct pic_softc *pic, int ipl) 120{ 121} 122 123static const struct pic_ops sunxi_intc_picops = { 124 .pic_unblock_irqs = sunxi_intc_unblock_irqs, 125 .pic_block_irqs = sunxi_intc_block_irqs, 126 .pic_establish_irq = sunxi_intc_establish_irq, 127 .pic_set_priority = sunxi_intc_set_priority, 128}; 129 130static void * 131sunxi_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 132 int (*func)(void *), void *arg) 133{ 134 /* 1st cell is the interrupt number */ 135 const u_int irq = be32toh(specifier[0]); 136 137 if (irq >= INTC_MAX_SOURCES) { 138#ifdef DIAGNOSTIC 139 device_printf(dev, "IRQ %u is invalid\n", irq); 140#endif 141 return NULL; 142 } 143 144 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 145 146 return intr_establish(irq, ipl, IST_LEVEL | mpsafe, func, arg); 147} 148 149static void 150sunxi_intc_fdt_disestablish(device_t dev, void *ih) 151{ 152 intr_disestablish(ih); 153} 154 155static bool 156sunxi_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 157{ 158 /* 1st cell is the interrupt number */ 159 if (!specifier) 160 return false; 161 const u_int irq = be32toh(specifier[0]); 162 163 snprintf(buf, buflen, "INTC irq %d", irq); 164 165 return true; 166} 167 168static const struct fdtbus_interrupt_controller_func sunxi_intc_fdt_funcs = { 169 .establish = sunxi_intc_fdt_establish, 170 .disestablish = sunxi_intc_fdt_disestablish, 171 .intrstr = sunxi_intc_fdt_intrstr, 172}; 173 174static int 175sunxi_intc_find_pending_irqs(struct sunxi_intc_softc *sc, u_int group) 176{ 177 uint32_t pend; 178 179 pend = INTC_READ(sc, INTC_IRQ_PEND_REG(group)); 180 pend &= sc->sc_enabled_irqs[group]; 181 182 if (pend == 0) 183 return 0; 184 185 INTC_WRITE(sc, INTC_IRQ_PEND_REG(group), pend); 186 187 return pic_mark_pending_sources(&sc->sc_pic, group * 32, pend); 188} 189 190static void 191sunxi_intc_irq_handler(void *frame) 192{ 193 struct cpu_info * const ci = curcpu(); 194 struct sunxi_intc_softc * const sc = intc_softc; 195 const int oldipl = ci->ci_cpl; 196 const uint32_t oldipl_mask = __BIT(oldipl); 197 int ipl_mask = 0; 198 199 ci->ci_data.cpu_nintr++; 200 201 if (sc->sc_enabled_irqs[0]) 202 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 0); 203 if (sc->sc_enabled_irqs[1]) 204 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 1); 205 if (sc->sc_enabled_irqs[2]) 206 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 2); 207 208 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 209 pic_do_pending_ints(I32_bit, oldipl, frame); 210} 211 212static int 213sunxi_intc_match(device_t parent, cfdata_t cf, void *aux) 214{ 215 struct fdt_attach_args * const faa = aux; 216 217 return of_match_compatible(faa->faa_phandle, compatible); 218} 219 220static void 221sunxi_intc_attach(device_t parent, device_t self, void *aux) 222{ 223 struct sunxi_intc_softc * const sc = device_private(self); 224 struct fdt_attach_args * const faa = aux; 225 const int phandle = faa->faa_phandle; 226 bus_addr_t addr; 227 bus_size_t size; 228 int error, i; 229 230 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 231 aprint_error(": couldn't get registers\n"); 232 return; 233 } 234 235 sc->sc_dev = self; 236 sc->sc_phandle = phandle; 237 sc->sc_bst = faa->faa_bst; 238 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 239 aprint_error(": couldn't map registers\n"); 240 return; 241 } 242 243 aprint_naive("\n"); 244 aprint_normal(": Interrupt Controller\n"); 245 246 /* Disable IRQs */ 247 for (i = 0; i < INTC_MAX_GROUPS; i++) { 248 INTC_WRITE(sc, INTC_EN_REG(i), 0); 249 INTC_WRITE(sc, INTC_MASK_REG(i), 0); 250 INTC_WRITE(sc, INTC_IRQ_PEND_REG(i), 251 INTC_READ(sc, INTC_IRQ_PEND_REG(i))); 252 } 253 /* Disable user mode access to intc registers */ 254 INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN); 255 256 sc->sc_pic.pic_ops = &sunxi_intc_picops; 257 sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES; 258 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 259 pic_add(&sc->sc_pic, 0); 260 261 error = fdtbus_register_interrupt_controller(self, phandle, 262 &sunxi_intc_fdt_funcs); 263 if (error) { 264 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 265 error); 266 return; 267 } 268 269 KASSERT(intc_softc == NULL); 270 intc_softc = sc; 271 arm_fdt_irq_set_handler(sunxi_intc_irq_handler); 272} 273 274CFATTACH_DECL_NEW(sunxi_intc, sizeof(struct sunxi_intc_softc), 275 sunxi_intc_match, sunxi_intc_attach, NULL, NULL); 276