sunxi_gmacclk.c revision 1.1 
1/* $NetBSD: sunxi_gmacclk.c,v 1.1 2017/10/07 13:28:59 jmcneill Exp $ */
2
3/*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: sunxi_gmacclk.c,v 1.1 2017/10/07 13:28:59 jmcneill Exp $");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/device.h>
35#include <sys/kmem.h>
36#include <sys/bus.h>
37
38#include <dev/clk/clk_backend.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	GMAC_CLK_PIT		__BIT(2)
43#define	 GMAC_CLK_PIT_MII	0
44#define	 GMAC_CLK_PIT_RGMII	1
45#define	GMAC_CLK_SRC		__BITS(1,0)
46#define	 GMAC_CLK_SRC_MII	0
47#define	 GMAC_CLK_SRC_EXT_RGMII	1
48#define	 GMAC_CLK_SRC_RGMII	2
49
50static int	sunxi_gmacclk_match(device_t, cfdata_t, void *);
51static void	sunxi_gmacclk_attach(device_t, device_t, void *);
52
53static struct clk *sunxi_gmacclk_decode(device_t, const void *, size_t);
54
55static const struct fdtbus_clock_controller_func sunxi_gmacclk_fdt_funcs = {
56	.decode = sunxi_gmacclk_decode
57};
58
59static struct clk *sunxi_gmacclk_get(void *, const char *);
60static void	sunxi_gmacclk_put(void *, struct clk *);
61static int	sunxi_gmacclk_set_rate(void *, struct clk *, u_int);
62static u_int	sunxi_gmacclk_get_rate(void *, struct clk *);
63static struct clk *sunxi_gmacclk_get_parent(void *, struct clk *);
64
65static const struct clk_funcs sunxi_gmacclk_clk_funcs = {
66	.get = sunxi_gmacclk_get,
67	.put = sunxi_gmacclk_put,
68	.set_rate = sunxi_gmacclk_set_rate,
69	.get_rate = sunxi_gmacclk_get_rate,
70	.get_parent = sunxi_gmacclk_get_parent,
71};
72
73struct sunxi_gmacclk_softc {
74	device_t		sc_dev;
75	int			sc_phandle;
76	bus_space_tag_t		sc_bst;
77	bus_space_handle_t	sc_bsh;
78
79	struct clk_domain	sc_clkdom;
80	struct clk		sc_clk;
81	struct clk		*sc_parent[2];
82};
83
84#define	RD4(sc, reg)			\
85	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
86#define	WR4(sc, reg, val)		\
87	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
88
89CFATTACH_DECL_NEW(sunxi_gmacclk, sizeof(struct sunxi_gmacclk_softc),
90    sunxi_gmacclk_match, sunxi_gmacclk_attach, NULL, NULL);
91
92static int
93sunxi_gmacclk_match(device_t parent, cfdata_t cf, void *aux)
94{
95	const char * const compatible[] = { "allwinner,sun7i-a20-gmac-clk", NULL };
96	const struct fdt_attach_args *faa = aux;
97
98	return of_match_compatible(faa->faa_phandle, compatible);
99}
100
101static void
102sunxi_gmacclk_attach(device_t parent, device_t self, void *aux)
103{
104	struct sunxi_gmacclk_softc * const sc = device_private(self);
105	const struct fdt_attach_args *faa = aux;
106	const int phandle = faa->faa_phandle;
107	bus_addr_t addr;
108	bus_size_t size;
109
110	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
111		aprint_error(": couldn't get registers\n");
112		return;
113	}
114
115	sc->sc_dev = self;
116	sc->sc_phandle = phandle;
117	sc->sc_bst = faa->faa_bst;
118	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
119		aprint_error(": couldn't map registers\n");
120		return;
121	}
122	sc->sc_parent[0] = fdtbus_clock_get_index(phandle, 0);
123	sc->sc_parent[1] = fdtbus_clock_get_index(phandle, 1);
124	if (sc->sc_parent[0] == NULL || sc->sc_parent[1] == NULL) {
125		aprint_error(": couldn't get parent clocks\n");
126		return;
127	}
128
129	sc->sc_clkdom.funcs = &sunxi_gmacclk_clk_funcs;
130	sc->sc_clkdom.priv = sc;
131
132	sc->sc_clk.domain = &sc->sc_clkdom;
133	sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name);
134
135	aprint_naive("\n");
136	aprint_normal(": GMAC MII/RGMII clock mux\n");
137
138	fdtbus_register_clock_controller(self, phandle, &sunxi_gmacclk_fdt_funcs);
139}
140
141static struct clk *
142sunxi_gmacclk_decode(device_t dev, const void *data, size_t len)
143{
144	struct sunxi_gmacclk_softc * const sc = device_private(dev);
145
146	if (len != 0)
147		return NULL;
148
149	return &sc->sc_clk;
150}
151
152static struct clk *
153sunxi_gmacclk_get(void *priv, const char *name)
154{
155	struct sunxi_gmacclk_softc * const sc = priv;
156
157	if (strcmp(name, sc->sc_clk.name) != 0)
158		return NULL;
159
160	return &sc->sc_clk;
161}
162
163static void
164sunxi_gmacclk_put(void *priv, struct clk *clk)
165{
166}
167
168static int
169sunxi_gmacclk_set_rate(void *priv, struct clk *clk, u_int rate)
170{
171	struct sunxi_gmacclk_softc * const sc = priv;
172	uint32_t val;
173
174	val = RD4(sc, 0);
175	val &= ~(GMAC_CLK_PIT|GMAC_CLK_SRC);
176	if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_MII])) {
177		/* MII clock */
178		val |= __SHIFTIN(GMAC_CLK_PIT_MII, GMAC_CLK_PIT);
179		val |= __SHIFTIN(GMAC_CLK_SRC_MII, GMAC_CLK_SRC);
180	} else if (rate == clk_get_rate(sc->sc_parent[GMAC_CLK_PIT_RGMII])) {
181		/* RGMII clock */
182		val |= __SHIFTIN(GMAC_CLK_PIT_RGMII, GMAC_CLK_PIT);
183		val |= __SHIFTIN(GMAC_CLK_SRC_RGMII, GMAC_CLK_SRC);
184	} else {
185		return ENXIO;
186	}
187	WR4(sc, 0, val);
188
189	return 0;
190}
191
192static u_int
193sunxi_gmacclk_get_rate(void *priv, struct clk *clk)
194{
195	struct clk *clk_parent = clk_get_parent(clk);
196
197	return clk_get_rate(clk_parent);
198}
199
200static struct clk *
201sunxi_gmacclk_get_parent(void *priv, struct clk *clk)
202{
203	struct sunxi_gmacclk_softc * const sc = priv;
204	uint32_t val;
205	u_int sel;
206
207	val = RD4(sc, 0);
208	sel = __SHIFTOUT(val, GMAC_CLK_PIT);
209
210	return sc->sc_parent[sel];
211}
212